CN106874235B - Analog DPRAM communication system and method based on SPI serial link - Google Patents
Analog DPRAM communication system and method based on SPI serial link Download PDFInfo
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- CN106874235B CN106874235B CN201710071503.1A CN201710071503A CN106874235B CN 106874235 B CN106874235 B CN 106874235B CN 201710071503 A CN201710071503 A CN 201710071503A CN 106874235 B CN106874235 B CN 106874235B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
The invention relates to an analog DPRAM communication system and method based on SPI serial link, the communication system includes: the system comprises a main control CPU, an analog DPRAM, an IO bus control CPU, SPI driving equipment and an SPI peripheral; the analog DPRAM comprises an analog DPRAM interface; the analog DPRAM interface, the master control CPU, the SPI driving device, the SPI peripheral and the IO bus control CPU are sequentially connected. The invention realizes the mode of simulating the DPRAM by adopting the SPI interface, thereby reducing the cost, meeting the performance requirement of communication and being helpful for reducing the size of the PCB. Importantly, other parts of the software can be unmodified and kept consistent with the software architecture adopting the DPRAM.
Description
Technical Field
The invention relates to the field of communication, in particular to an analog DPRAM communication system and method based on an SPI serial link.
Background
The SPI (Serial Peripheral Interface) bus system is a synchronous Serial Peripheral Interface that allows the MCU to communicate with various Peripheral devices in a Serial manner to exchange information. The SPI has three registers: a control register SPCR, a status register SPSR, a data register SPDR. The peripheral equipment comprises a FLASHRAM, a network controller, an LCD display driver, an A/D converter, an MCU and the like. The SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers, typically using 4 wires: serial Clock Line (SCLK), master input/slave output data line MISO, master output/slave input data line MOSI, and low active slave select line NSS (some SPI interface chips with interrupt signal line INT, some SPI interface chips without master output/slave input data line MOSI).
The SPI interface was first defined by Motorola on its MC68HCXX family of processors. The SPI interface is mainly applied to EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.
The SPI interface carries out synchronous serial data transmission between a CPU and a peripheral low-speed device, under the shift pulse of a main device, data are transmitted according to bits, the high bit is in front, the low bit is behind, full-duplex communication is realized, the data transmission speed is generally faster than that of an I2C bus, and the speed can reach several Mbps.
In order to reduce the load of the main control CPU and improve the performance of the field bus in the PLC architecture, a method of using a single CPU for the field bus is considered, and thus a dual-CPU architecture occurs. The implementation of such an architecture needs to consider the communication performance between two CPUs, and a DPRAM (fully called DualPort RAM or dual port RAM) is generally adopted, so that the data transmission capability between the CPUs can be improved.
DPRAM provides storage space for the following data:
1) host to PMAC data:
command position of the motor, command speed of the motor, on-line command of the machine tool, and control variable value in the motion program.
2) Data from PMAC to host:
the motor state variable, the actual position of the motor, the actual speed of the motor, the actual acceleration of the motor, the following error of the motor, the switching values of a machine tool and a control panel, and the pulse numerical value of a hand pulse generator.
In PMAC, a PLC program is run at regular time intervals, and in the PLC program, the data can be read out, and the data is written into the DPRAM after simple conversion, and the host can read out and process the data.
The data transmission performance is greatly improved by selecting the DPRAM as a communication link between CPUs, but the influence of two aspects needs to be considered at the same time, firstly, the cost of the whole product is increased, which is mainly reflected in that the DPRAM devices are added, the CPUs supporting the external SRAM need to be selected when the DPRAM is used, and the CPUs supporting the external SRAM in the same series of CPUs which all belong to middle and high grades are relatively high in price. And secondly, the DPRAM is increased, so that the space of the PCB is occupied, meanwhile, because the DPRAM adopts a parallel transmission mode, certain challenges are brought to the wiring of the PCB, and great challenges are brought to the signal integrity and the EMC performance of the PCB.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide an SPI serial link-based analog DPRAM communication system and method, which adopt an SPI interface analog DPRAM mode to reduce the cost and meet the performance requirements of communication.
The purpose of the invention is realized by adopting the following technical scheme:
the invention provides an analog DPRAM communication system based on SPI serial link, its improvement lies in that the communication system includes: the main control CPU, the analog DPRAM and the IO bus control CPU; the main control CPU and the IO bus control CPU respectively comprise an SPI control device, an SPI driving device and an SPI peripheral which are connected in sequence; the analog DPRAM comprises an analog DPRAM interface; and the main control CPU and the IO bus control CPU realize data transmission through the analog DPRAM interface.
Further, the main control CPU is connected with the SPI peripheral through an analog DPRAM interface; the SPI peripheral is connected with the IO bus control CPU through an analog DPRAM interface; and the SPI driving equipment is used for realizing the transceiving control of the main control CPU and the IO bus control CPU.
Further, the main control CPU is an SPI control main device; and the IO bus control CPU controls slave equipment for the SPI.
Further, the analog DPRAM further comprises a RAM and an SPI register, and the RAM and the SPI register are connected in sequence.
Furthermore, the analog DPRAM interface is used for providing an interface read-write mode similar to DPRAM and packaging the realization of a communication system.
Further, the SPI control master and the SPI control slave, both for read and write control from the RAM to the SPI register.
The SPI control master device refers to a device capable of initiatively initiating SPI communication, and the SPI control slave device refers to a peripheral device with an SPI interface, namely an SPI device.
Furthermore, the master control CPU, the analog DPRAM, the IO bus control CPU, the SPI driving device and the SPI peripheral are all packaged in a single chip microcomputer, and the number of the single chip microcomputers is 2; the SPI peripheral is an application program running in the single chip microcomputer.
Further, the single chip microcomputer is realized by adopting a logic controller PLC.
The invention also provides a communication method of an analog DPRAM communication system based on the SPI serial link, and the improvement is that the method comprises the following steps:
step 1: an analog DPRAM interface is adopted to provide an interface read-write mode similar to DPRAM, and the internal implementation is packaged;
step 2: the master control CPU controls the SPI and comprises reading and writing control from the RAM to an SPI register;
and step 3: the SPI driving device realizes the transceiving control of the SPI control master device and the SPI control slave device;
and 4, step 4: the SPI peripheral provides an SPI interface for communication to exchange information;
and 5: and controlling the IO bus control CPU.
Compared with the closest prior art, the technical scheme provided by the invention has the following beneficial effects:
the technical scheme provided by the invention realizes the mode of simulating the DPRAM by adopting the SPI interface, thereby reducing the cost, meeting the performance requirement of communication and being helpful for reducing the size of the PCB. Importantly, other parts of the software can be unmodified and kept consistent with the software architecture adopting the DPRAM.
According to the definition in the logic, connect two independent singlechip (CPU) through SPI physically to need set for main control CPU and be SPI main equipment, IO bus control CPU is SPI slave unit, can alleviate CPU's burden, thereby has very big promotion to entire system's performance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a logic diagram of an analog DPRAM communication system based on SPI serial links;
fig. 2 is a schematic diagram of a physical implementation of an analog DPRAM communication system based on an SPI serial link.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without any inventive step, are within the scope of the present invention.
First preferred technical solution
The physical device DPRAM is adopted as a communication mode between the dual CPUs, so that high performance can be provided, but the cost is high, the DPRAM devices need to be added, high-grade CPUs supporting SRAM interfaces need to be selected, and the area of the PCB is increased. Aiming at the fact that the DPRAM is used as a main mode of communication between CPUs in a PLC framework, the invention provides a novel communication mode which can achieve the communication performance of the DPRAM and keep the interface of the DPRAM so as to keep the consistency of a software framework.
And (3) performance calculation: assuming that the SPI uses a 16MHz rate (which is basically achieved by the SPI peripherals of the single-chip), the time required to transmit 4KB of data (4 KB transmitted, 4KB received) is (4 × 1000 × 8)/16 ═ 2000us ═ 2 ms. This time can satisfy most PLC controller requirements.
The invention provides an SPI serial link-based analog DPRAM communication system, as shown in a logic schematic diagram of the SPI serial link-based analog DPRAM communication system in fig. 1 and a physical implementation schematic diagram of the SPI serial link-based analog DPRAM communication system in fig. 2, the communication system comprises: the main control CPU, the analog DPRAM and the IO bus control CPU; the main control CPU and the IO bus control CPU respectively comprise an SPI control device, an SPI driving device and an SPI peripheral which are connected in sequence; the analog DPRAM comprises an analog DPRAM interface; and the main control CPU and the IO bus control CPU realize data transmission through the analog DPRAM interface.
In the above preferred technical solution, the main control CPU is connected to the SPI peripheral through an analog DPRAM interface; the SPI peripheral is connected with the IO bus control CPU through an analog DPRAM interface; and the SPI driving equipment is used for realizing the transceiving control of the main control CPU and the IO bus control CPU.
In the above preferred technical solution, the main control CPU is an SPI control master device; and the IO bus control CPU controls slave equipment for the SPI.
In the above preferred technical solution, the analog DPRAM further includes a RAM and an SPI register, and the RAM and the SPI register are connected in sequence.
In the above preferred technical solution, the analog DPRAM interface is used to provide an interface read-write mode similar to DPRAM, and to encapsulate the implementation of the communication system.
In the above preferred technical solution, the SPI control master device and the SPI control slave device are both used for read and write control from the RAM to the SPI register.
In the above preferred technical solution, the SPI peripheral includes an SPI device inside the single chip microcomputer.
In the preferred technical scheme, the master control CPU, the analog DPRAM, the IO bus control CPU, the SPI driving device and the SPI peripheral are all packaged in a single chip microcomputer.
In the above preferred technical scheme, the single chip microcomputer is implemented by a logic controller PLC.
This scheme has realized adopting SPI interface simulation DPRAM's mode, can satisfy the performance requirement of communication when reduce cost like this, also helps to PCB's size reduction.
Second preferred embodiment
The invention realizes a DPRAM communication interface logically, and is mainly characterized in that an operation mode very similar to a real DPRAM device is provided, thus being convenient for software transplantation. The implementation is logically divided into four layers:
the analog DPRAM interface mainly provides an interface reading and writing mode similar to the DPRAM, and encapsulates internal implementation.
SPI control, mainly including read and write control from RAM to SPI register.
And the SPI drive mainly realizes SPI master-slave transceiving control.
-SPI peripheral, SPI device inside the single chip.
This application is two singlechips that have SPI interface, comes the simulation to realize dpram. The SPI driver is a program running inside the single chip microcomputer.
The invention also provides a communication method of the analog DPRAM communication system based on the SPI serial link, which comprises the following steps:
step 1: an analog DPRAM interface is adopted to provide an interface read-write mode similar to DPRAM, and the internal implementation is packaged;
step 2: the master control CPU controls the SPI and comprises reading and writing control from the RAM to an SPI register;
and step 3: the SPI driving device realizes the transceiving control of the SPI control master device and the SPI control slave device;
and 4, step 4: the SPI peripheral provides an SPI interface for communication to exchange information;
and 5: and controlling the IO bus control CPU.
According to the definition on the logic, two independent single-chip microcomputers (CPU) are connected through the SPI physically to main control CPU needs to be set as SPI master equipment, and IO bus control CPU is SPI slave equipment. One physical implementation listed in fig. 2 employs SPI + DMA, which can reduce the burden on the CPU, thereby greatly improving the performance of the entire system.
The technical scheme adopted by the invention overcomes the defects that a physical device DPRAM is adopted as a communication mode between double CPUs in the prior art, although higher performance can be provided, the cost is higher, a DPRAM device is required to be added, a high-grade CPU supporting an SRAM interface is required to be selected, and the area of a PCB is increased.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. An analog DPRAM communication system based on an SPI serial link, the communication system comprising: the main control CPU, the analog DPRAM and the IO bus control CPU;
the main control CPU and the IO bus control CPU respectively comprise an SPI control device, an SPI driving device and an SPI peripheral which are connected in sequence;
the analog DPRAM comprises an analog DPRAM interface; the main control CPU and the IO bus control CPU realize data transmission through the analog DPRAM interface;
the analog DPRAM also comprises an RAM and an SPI register which are connected in sequence;
the analog DPRAM interface is used for providing an interface read-write mode similar to DPRAM and packaging the realization of a communication system; the SPI control equipment is used for reading and writing control from the RAM to the SPI register; the SPI driving equipment is used for realizing the transceiving control of the main control CPU and the IO bus control CPU; the SPI peripheral hardware is used for providing an interface, so that communication is carried out to exchange information, and the interface connection mode of the DPRAM is simulated based on an SPI interface formed by the SPI control equipment, the SPI driving equipment and the SPI peripheral hardware.
2. The SPI serial link based analog DPRAM communication system of claim 1, wherein the master control CPU is an SPI control master; and the IO bus control CPU controls slave equipment for the SPI.
3. An SPI serial link based analog DPRAM communication system according to claim 2, wherein said SPI control master and SPI control slave are both used for read and write control from RAM to SPI registers.
4. An SPI serial link based analog DPRAM communication system according to claim 1, wherein said SPI peripheral comprises an SPI device internal to the single chip.
5. The SPI serial link-based analog DPRAM communication system of claim 1, wherein the master control CPU, analog DPRAM, IO bus control CPU are all packaged in a single chip microcomputer, the number of which is 2; the SPI peripheral is an application program running in the single chip microcomputer.
6. The SPI serial link-based analog DPRAM communication system of claim 5, wherein the single chip microcomputer is implemented with a logic controller PLC.
7. A communication method of an SPI serial link based analog DPRAM communication system according to any one of claims 1 to 5, characterized in that it comprises the following steps:
step 1: an analog DPRAM interface is adopted to provide an interface read-write mode similar to DPRAM, and the internal implementation is packaged;
step 2: the master control CPU controls the SPI and comprises reading and writing control from the RAM to an SPI register;
and step 3: the SPI driving device realizes the transceiving control of the SPI control master device and the SPI control slave device;
and 4, step 4: the SPI peripheral provides an SPI interface for communication to exchange information;
and 5: and controlling the IO bus control CPU.
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| US9418030B2 (en) * | 2012-02-09 | 2016-08-16 | Intel Corporation | Inter-component communication including posted and non-posted transactions |
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| US9418030B2 (en) * | 2012-02-09 | 2016-08-16 | Intel Corporation | Inter-component communication including posted and non-posted transactions |
| CN105021911A (en) * | 2014-04-28 | 2015-11-04 | 苏州华天国科电力科技有限公司 | Intelligent energy-saving potential and electric energy quality diagnostic device for individual line user |
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