CN215526657U

CN215526657U - High-speed communication module and variable frequency controller of ARM chip and FPGA chip

Info

Publication number: CN215526657U
Application number: CN202122210785.3U
Authority: CN
Inventors: 刘�东
Original assignee: Ceristar Electric Co ltd; MCC Capital Engineering and Research Incorporation Ltd
Current assignee: Ceristar Electric Co ltd; MCC Capital Engineering and Research Incorporation Ltd
Priority date: 2021-09-13
Filing date: 2021-09-13
Publication date: 2022-01-14
Anticipated expiration: 2031-09-13

Abstract

The utility model discloses a high-speed communication module and a variable frequency controller of an ARM chip and an FPGA chip, wherein the high-speed communication module comprises: an ARM chip and an FPGA chip; the ARM chip and the FPGA chip are connected through a 16-bit data bus or an address bus, and data are transmitted in a parallel mode. According to the utility model, the ARM chip is connected with the FPGA chip through the 16-bit data bus or the address bus, data is transmitted in a parallel mode, and high-speed data transmission can be realized between the ARM chip and the FPGA chip.

Description

High-speed communication module and variable frequency controller of ARM chip and FPGA chip

Technical Field

The utility model relates to the field of electronic circuits, in particular to a high-speed communication module of an ARM chip and an FPGA chip and a variable frequency controller.

Background

This section is intended to provide a background or context to the embodiments of the utility model that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

In the frequency conversion controller, the ARM chip is used as a main control chip of the frequency converter, the FPGA chip is used as a peripheral interface chip of the frequency converter, various complex algorithms can be realized by the ARM chip, high-speed parallel data transmission can be realized by the FPGA chip, quick response and high-precision frequency conversion control can also be realized, and the frequency conversion controller is strong in real-time performance and high in flexibility.

When the communication of ARM chip and FPGA chip is realized, prior art adopts SPI bus or RS485 bus to carry out data bidirectional switching, and data receives external signal's interference easily in transmission process, and transmission data efficiency is lower simultaneously, and data transmission speed is slow, is not suitable for the transmission of block data.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a high-speed communication module of an ARM chip and an FPGA chip, which is used for realizing high-speed data transmission between the ARM chip and the FPGA chip, and comprises: an ARM chip and an FPGA chip; the ARM chip and the FPGA chip are connected through a 16-bit data bus or an address bus, and data are transmitted in a parallel mode.

Further, in the high-speed communication module provided in the embodiment of the present invention, the ARM chip is iMX6 QD; the FPGA chip adopts an XC6SLX16-3FTG256C & W25Q80VSS chip.

Further, in the high-speed communication module provided in the embodiment of the present invention, the signal pin D16, the signal pin D17, the signal pin D18, the signal pin D19, the signal pin EIM _ D19, the signal pin 19, the EIM _ D19, the signal pin, the EIM _ 19, the signal pin 19, the EIM _ D _ 19, the signal pin, the EIM _ 19, the signal pin, the EIM _ 19, the signal pin, respectively, for implementing 16-bit data signaling.

Further, in the high-speed communication module provided in the embodiment of the present invention, the EB0 signal pin, the EB1 signal pin, the EB2 signal pin, and the EB3 signal pin of the ARM chip are respectively connected to the EIM _ EB0 signal pin, the EIM _ EB1 signal pin, the EIM _ EB2 signal pin, and the EIM _ EB3 signal pin of the FPGA chip, so as to implement block data transmission.

Further, in the high-speed communication module provided in the embodiment of the present invention, the BCLK signal pin of the ARM chip is connected to the EIM _ BCLK signal pin of the FPGA chip, so as to implement clock signal transmission.

Further, in the high-speed communication module provided in the embodiment of the present invention, the CS0 signal pin, the CS1 signal pin, the WE _ B signal pin, the WAIT signal pin, and the OE _ B signal pin of the ARM chip are respectively connected to the EIM _ CS0 signal pin, the EIM _ CS1 signal pin, the EIM _ WE _ B signal pin, the EIM _ WAIT signal pin, and the EIM _ OE _ B signal pin of the FPGA chip, so as to implement enable signal transmission.

Further, in the high-speed communication module provided in the embodiment of the present invention, the DA0 signal pin, the DA1 signal pin, the DA2 signal pin, the DA3 signal pin, the EIM _ DA3 signal pin of the FPGA chip, the EIM _ DA3 signal pin, the EIM _ DA _ 3 signal pin, the EIM _ DA _ 3 signal 3, the EIM _ 3 signal pin, the EIM _ DA _ 3 signal pin, the EIM _ 3 signal 3, the EIM _ DA _ 3 signal pin, the EIM _ 3 signal pin, the EIM _ 3 signal 3, the EIM _ signal pin, the EIM _ DA _ 3 signal pin, the EIM _ 3 signal pin, the EIM _ 3 signal 3, the EIM _ DA _ signal 3, the EIM _ signal pin, the EIM _ 3, respectively, for implementing address signaling.

Further, in the high-speed communication module provided in the embodiment of the present invention, the CPU _ FPGA0 signal pin, the CPU _ FPGA1 signal pin, the CPU _ FPGA2 signal pin, the CPU _ FPGA3 signal pin, the CPU _ FPGA4 signal pin, the CPU _ FPGA5 signal pin, the CPU _ FPGA6 signal pin, and the CPU _ FPGA7 signal pin of the ARM chip are respectively connected to the CSI0_ DAT4 signal pin, the CSI0_ DAT5 signal pin, the CSI0_ DAT6 signal pin, the CSI0_ DAT7 signal pin, the CSI0_ DAT12 signal pin, the CSI0_ DAT13 signal pin, the CSI0_ DAT16 signal pin, and the CSI0_ DAT17 signal pin of the FPGA chip, so as to implement interrupt signal transmission.

The embodiment of the utility model also provides a frequency conversion controller, which is used for realizing high-speed data transmission between the ARM chip and the FPGA chip and comprises: the high-speed communication module of the ARM chip and the FPGA chip.

Further, the variable frequency controller further comprises: the FPGA chip is used for transmitting the control signal output by the ARM chip to a plurality of external frequency conversion devices in parallel.

Further, the variable frequency controller further comprises: and the external expansion board is connected with the FPGA chip and is used for expanding various field buses or Ethernet buses.

The high-speed communication module and the variable frequency controller of the ARM chip and the FPGA chip provided by the embodiment of the utility model connect the ARM chip and the FPGA chip through a 16-bit data bus or an address bus, transmit data in a parallel mode and realize high-speed data transmission between the ARM chip and the FPGA chip.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. In the drawings:

FIG. 1 is a schematic diagram of a high-speed communication module of an ARM chip and an FPGA chip according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a frequency conversion controller according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.

The embodiment of the present invention provides a high-speed communication module of an ARM chip and an FPGA chip, fig. 1 is a schematic diagram of a high-speed communication module of an ARM chip and an FPGA chip in the embodiment of the present invention, as shown in fig. 1, the high-speed communication module includes: an ARM chip 10 and an FPGA chip 20; the ARM chip 10 and the FPGA chip 20 are connected through a 16-bit data bus or an address bus, and data are transmitted in a parallel mode.

In one embodiment, in the high-speed communication module provided in the embodiment of the present invention, the ARM chip 10 is iMX6 QD; the FPGA chip 20 adopts an XC6SLX16-3FTG256C & W25Q80VSS chip. Table 1 shows signal pins of iMX6QD chips and XC6SLX16-3FTG256C & W25Q80VSS chips.

TABLE 1

iMX6QD is a high-end ARM chip capable of running Linux operating system; high-speed data exchange and transmission are performed through data lines, address lines, read commands, write commands, general input/output lines, and the like. The method aims to give part of quick tasks to the FPGA for operation and processing, and simultaneously complete multiple complex tasks by utilizing the advantage of parallel computation of the FPGA.

For the iMX6QD chip, the external FPGA is an intelligent coprocessor, and after data is written into the FPGA according to a strict time sequence and sequence, the external FPGA waits for a signal processed by the FPGA to be completed, and then reads a result calculated by the FPGA. For software programming iMX6, the external FPGA is equivalent to a dual port RAM.

For the FGPA chip, iMX6QD is equivalent to a block dual-port RAM, and data can be read and written in a strict timing and order.

It should be noted that the XC6SLX16-3FTG256C & W25Q80VSS chip belongs to the Spartan-6FPGA series, and is a low-cost and low-power consumption FPGA of Xilinx corporation. The sixth generation Spartan series are based on low power consumption 45nm, 9 metallic copper layer, dual-gate oxide layer process technology and advanced power consumption management technology.

In order to implement data signal transmission, as shown in table 1, the D16 signal pin, the D17 signal pin, the D18 signal pin, the D19 signal pin, the D20 signal pin, the D21 signal pin, the D22 signal pin, the D23 signal pin, the D24 signal pin, the D25 signal pin, the D26 signal pin, the D27 signal pin, the D28 signal pin, the D29 signal pin, the D30 signal pin, the D31 signal pin of the ARM chip 10, and is connected to the EIM _ D16 signal pin, the EIM _ D17 signal pin, the EIM _ D18 signal pin, the EIM _ D19 signal pin, the EIM _ D20 signal pin, the EIM _ D21 signal pin, the EIM _ D22 signal pin, the EIM _ D23 signal pin, the EIM _ D24 signal pin, the EIM _ D25 signal pin, the EIM _ D26 signal pin, the EIM _ D27 signal pin, the EIM _ D28 signal pin, the EIM _ D29 signal pin, the EIM _ D30 signal pin, and the EIM _ D31 signal pin of the FPGA chip 20, respectively, so as to implement 16-bit data signal transmission.

In order to realize block data transmission, as shown in table 1, the EB0 signal pin, the EB1 signal pin, the EB2 signal pin, and the EB3 signal pin of the ARM chip 10 are respectively connected to the EIM _ EB0 signal pin, the EIM _ EB1 signal pin, the EIM _ EB2 signal pin, and the EIM _ EB3 signal pin of the FPGA chip 20, and are used for realizing block data transmission.

In order to realize clock signal transmission, as shown in table 1, the BCLK signal pin of the ARM chip 10 is connected to the EIM _ BCLK signal pin of the FPGA chip 20, and is used to realize clock signal transmission.

In order to realize the enable signal transmission, as shown in table 1, the CS0 signal pin, the CS1 signal pin, the WE _ B signal pin, the WAIT signal pin, and the OE _ B signal pin of the ARM chip 10 are respectively connected to the EIM _ CS0 signal pin, the EIM _ CS1 signal pin, the EIM _ WE _ B signal pin, the EIM _ WAIT signal pin, and the EIM _ OE _ B signal pin of the FPGA chip 20, so as to realize the enable signal transmission.

To implement address signal transmission, as shown in table 1, the DA0 signal pin, DA1 signal pin, DA2 signal pin, DA3 signal pin, DA4 signal pin, DA5 signal pin, DA6 signal pin, DA7 signal pin, DA8 signal pin, DA9 signal pin, DA10 signal pin, DA11 signal pin, DA12 signal pin, DA13 signal pin, DA14 signal pin, DA15 signal pin of the ARM chip 10, the signal pin is connected with an EIM _ DA0 signal pin, an EIM _ DA1 signal pin, an EIM _ DA2 signal pin, an EIM _ DA3 signal pin, an EIM _ DA4 signal pin, an EIM _ DA5 signal pin, an EIM _ DA6 signal pin, an EIM _ DA7 signal pin, an EIM _ DA8 signal pin, an EIM _ DA9 signal pin, an EIM _ DA10 signal pin, an EIM _ DA11 signal pin, an EIM _ DA12 signal pin, an EIM _ DA13 signal pin, an EIM _ DA14 signal pin, and an EIM _ DA15 signal pin of the FPGA chip 20, respectively, and is used for realizing address signal transmission.

To implement interrupt signal transmission, as shown in table 1, the CPU _ FPGA0 signal pin, the CPU _ FPGA1 signal pin, the CPU _ FPGA2 signal pin, the CPU _ FPGA3 signal pin, the CPU _ FPGA4 signal pin, the CPU _ FPGA5 signal pin, the CPU _ FPGA6 signal pin, and the CPU _ FPGA7 signal pin of the ARM chip 10 are respectively connected with the CSI0_ DAT4 signal pin, the CSI0_ DAT5 signal pin, the CSI0_ DAT6 signal pin, the CSI0_ DAT7 signal pin, the CSI0_ DAT12 signal pin, the CSI0_ DAT13 signal pin, the CSI0_ DAT16 signal pin, and the CSI0_ DAT17 signal pin of the FPGA chip 20, so as to implement interrupt signal transmission.

When iMX6 writes Data to the FPGA, both chip select 0 and chip select 1 output logic low, enable output high, write enable output high, output 16 bits of Data onto the Data [15:0] pins and the corresponding address lines ADDR [15:0], looking through the WAIT WAIT signal continuously. If the signal is 1, the FPGA completes the data writing operation, and the writing operation can be performed on the next group of data. If the signal is 0, the FPGA does not finish the data writing operation, and the FPGA needs to wait for a plurality of clock cycles until the writing operation is finished, so that the next writing operation or reading operation can be carried out.

When iMX6 reads data from the FPGA, both chip select 0 and chip select 1 output logic low, enable output high, write enable output low, and output 16-bit address data onto ADDR [15:0] pins, continuously looking up WAIT WAIT signals. If the signal is 1, the FPGA finishes the data reading operation, and the data of the next group of addresses can be read. If the signal is 0, the FPGA does not finish the data reading operation, and the FPGA needs to wait for a plurality of clock cycles until the reading operation is finished, so that the next writing operation or reading operation can be carried out.

When iMX6 needs the FPGA to complete a certain operation quickly, a rising edge from a low level to a high level can be output on the interrupt 0-3 pins, and the FPGA can enter an interrupt processing program immediately after receiving the rising edge.

When the FPGA needs iMX6 to complete a certain operation quickly, a rising edge from a low level to a high level can be output on the interrupt 4-7 pins, and after the rising edge is received, iMX6 enters an interrupt handler immediately.

And the block operation clocks are 0-4 and are used for realizing rapid read-write exchange of a large amount of data between iMX6 and the FPGA. Upon entering a block operation, the FPGA or iMX6 will remember the address by simply writing the first address on the address bus ADDR [15:0] pins. With the change of the block operation clock, the FPGA or iMX6 will automatically increase the address without outputting on the ADDR [15:0] pin of the address bus, and only output 16-bit Data to the Data [15:0] pin, so as to complete the fast read-write transmission of a large amount of Data. According to the current design, the entire data area is divided into 16 data blocks, selected by block operations 0-3. Table 2 shows clock signals for block operations 0-3.

TABLE 2

Serial number	Block operation select 0	Block operation selection 1	Block operation selection 2	Block operation selection 3	Block selection
						1	Low level of electricity	Low level of electricity	Low level of electricity	Low level of electricity	0
2	High level	Low level of electricity	Low level of electricity	Low level of electricity	1
						3	Low level of electricity	High level	Low level of electricity	Low level of electricity	2
4	High level	High level	Low level of electricity	Low level of electricity	3
						5	Low level of electricity	Low level of electricity	High level	Low level of electricity	4
6	High level	Low level of electricity	High level	Low level of electricity	5
						7	Low level of electricity	High level	High level	Low level of electricity	6
8	High level	High level	High level	Low level of electricity	7
						9	Low level of electricity	Low level of electricity	Low level of electricity	High level	8
10	High level	Low level of electricity	Low level of electricity	High level	9
						11	Low level of electricity	High level	Low level of electricity	High level	10
12	High level	High level	Low level of electricity	High level	11
						13	Low level of electricity	Low level of electricity	High level	High level	12
14	High level	Low level of electricity	High level	High level	13
						15	Low level of electricity	High level	High level	High level	14
16	High level	High level	High level	High level	15

Fig. 2 is a schematic diagram of a frequency conversion controller in an embodiment of the present invention, and as shown in fig. 2, an embodiment of the present invention further provides a frequency conversion controller, including: the high-speed communication module of ARM chip and FPGA chip of above-mentioned any.

In an embodiment, the variable frequency controller provided in the embodiment of the present invention further includes: the FPGA chip 20 is used for transmitting the control signal output by the ARM chip 10 to a plurality of external frequency conversion devices in parallel.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: and the USB interface 301 is connected with the ARM chip 10 and is used for communicating with an external USB device.

According to the variable frequency controller provided by the embodiment of the utility model, the ARM chip is used as a main control chip of the frequency converter, the FPGA chip is used as a peripheral interface chip of the frequency converter, various complex algorithms can be realized by using the ARM chip, high-speed parallel data transmission can be realized by using the FPGA chip, quick response and high-precision variable frequency control can also be realized, and the variable frequency controller is strong in real-time performance and high in flexibility. The conversion between the USB signal and the TTL signal is realized through the RS422 conversion circuit 30, so that the ARM chip 10 communicates with an external USB device through a USB interface, thereby facilitating the USB debugging of the function of the ARM chip system (for example, a Linux system), facilitating the work of system debugging personnel, and supporting the hot plug function.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: a PCIe-to-PCI chip 101, an optical fiber Ethernet chip 102a, an optical fiber Ethernet interface 103a, an electrical port Ethernet chip 102b and an electrical port Ethernet interface 103 b;

the optical fiber ethernet interface 103a is connected to the optical fiber ethernet chip 102a, and is configured to transmit ethernet data through an optical fiber; an electrical port ethernet interface 103b connected to the electrical port ethernet chip 102b, for transmitting ethernet data via a network cable; the PCIe-to-PCI chip 101 is connected with the ARM chip 10, and is used for expanding the ARM chip 10 out of an optical fiber Ethernet bus and an electrical port Ethernet bus, so that the ARM chip 10 is connected with the optical fiber Ethernet chip 102a through the expanded optical fiber Ethernet bus; the extended electrical port ethernet bus is connected to the electrical port ethernet chip 102 b.

The variable frequency controller provided by the embodiment of the utility model integrates the hundred-megabyte standard Ethernet interface, supports the TCP/IP protocol, expands the optical fiber Ethernet interface through the PCIe-to-PCI chip 101 and realizes the receiving and sending of the high-speed Ethernet original message. Optionally, in the embodiment of the present invention, two ethernet buses are extended through the PCIe-to-PCI chip 101, where one ethernet bus is an electrical port ethernet and the other ethernet bus is a plastic optical fiber ethernet. Optionally, in the embodiment of the present invention, the PCIe-to-PCI chip may expand one PCIe bus interface into two PCI bus interfaces, and each PCI bus interface may be connected to one ethernet chip.

Alternatively, the PCIe to PCI chip may be an XIO2001 chip.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: and the RTC clock chip 104 is connected with the ARM chip 10 and used for providing a clock signal. Optionally, in the variable frequency controller provided in the embodiment of the present invention, the ARM chip 10 extends a Real-time clock (RTC) chip through an I2C bus to record and store the actual time, so that the entire system and the controller are more complete.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: DDR memory 106 and MMC memory 105; the DDR memory 106 is connected with the ARM chip 10 and used for storing memory data; and the MMC memory 105 is connected with the ARM chip 10 and used for storing data. Alternatively, the MMC memory may be an MMC card, through which onboard data storage is implemented, and both system check and encrypted data need to be stored in the MMC card. Because the read-write speed of the MMC card is higher than that of the CF card, the data which is held emergently can be stored in the MMC card. In the variable frequency controller provided by the embodiment of the utility model, the ARM chip expands the RAM in a DDR mode, so that the storage and operation of mass memory data are realized, and various current main DDR buses are supported.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: a USB interface 301 for communicating with an external USB device; and the USB-to-TTL module 302 is connected with the ARM chip 10 and is used for converting USB data into TTL data.

The frequency conversion controller provided by the embodiment of the utility model can be supplied with 24V direct current and is connected with an external power supply through a power interface 211 at the bottom. Alternatively, the power interface 211 may be a power terminal.

Optionally, in the variable frequency controller provided in the embodiment of the present invention, the ARM chip adopts a 4-core a9 series, and the main frequency can reach 1 GHz. Compared with the main frequency (hundred megameters) of the existing DSP chip, the variable frequency controller provided by the embodiment of the utility model is based on an ARM + FPGA system architecture, can realize quick real-time response and high-precision variable frequency control, and is more suitable for the requirements of high-end frequency converters and system application. In addition, in the variable frequency controller provided by the embodiment of the utility model, the FPGA chip is responsible for parallel high-speed data processing, optical fiber data communication and other work, and the function that one controller is provided with a plurality of motors is realized through coordination. Optionally, the ARM chip may perform high-speed data communication with the FPGA chip through the local bus.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: and the CF card interface 107 is connected with the ARM chip 10 and used for storing data into an external CF card or reading data in the external CF card. The ARM chip is expanded out of the storage function of the CF card, and system data or user data are stored in the CF card, so that system and program upgrading can be conveniently carried out through the CF card.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: a nixie tube driver chip 108 and a nixie tube 109; the nixie tube driving chip 108 is connected with the ARM chip 10 and is used for driving the nixie tube 109 to be turned on or off; the nixie tube 109 is used for displaying the state information of the variable frequency controller. Optionally, the nixie tube 109 is an 8-bit LED nixie tube for displaying the current controller status, so that the user can conveniently determine the current software condition inside the controller. Alternatively, the nixie driver chip 108 may be a 74HC595D serial-to-parallel chip, which converts the serial signal of the ARM chip into a parallel signal for driving the LED nixie tube.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: and the external expansion board 201 is connected with the FPGA chip 20 and is used for expanding various field buses or Ethernet buses. The FPGA chip expands the external expansion board through the internal bus, can realize the support of various field buses and real-time Ethernet buses, and enhances the expansibility of the system.

In one embodiment, the frequency conversion controller provided in the embodiment of the present invention further includes: and the interrupt signal transmission interface 212 is connected with the FPGA chip 20 and is used for transmitting interrupt signals.

In an embodiment, in the variable frequency controller provided in the embodiment of the present invention, the FPGA chip 20 may be further configured to extend any one of a CAN bus interface 202, an RS485 bus interface 203, an RS232 bus interface 204, an SSI encoder signal interface 205, an incremental encoder signal interface 206, a digital input signal interface 207, a digital output signal interface 208, an analog input signal interface 209, an analog output signal interface 210, and a power interface 211. By expanding the data transmission interfaces of various communication protocols, the coordinated and unified operation of multiple communication protocols is realized. The FPGA chip expands an interrupt signal transmission interface for receiving or sending a quick interrupt signal in a plastic optical fiber or glass optical fiber mode, and data synchronization and signal synchronization among a plurality of controllers are achieved. The ARM chip also supports an interrupt triggering function so as to realize the emergency processing of the fast signals.

In summary, the high-speed communication module and the variable-frequency controller of the ARM chip and the FPGA chip provided in the embodiments of the present invention connect the ARM chip and the FPGA chip through a 16-bit data bus or an address bus, and transmit data in a parallel manner, so that high-speed data transmission can be implemented between the ARM chip and the FPGA chip.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the utility model. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The utility model provides a high-speed communication module of ARM chip and FPGA chip which characterized in that includes: an ARM chip (10) and an FPGA chip (20);

the ARM chip (10) and the FPGA chip (20) are connected through a 16-bit data bus or an address bus, and data are transmitted in a parallel mode.

2. The high-speed communication module of an ARM chip and an FPGA chip of claim 1,

the ARM chip (10) adopts iMX6QD chips;

the FPGA chip (20) adopts an XC6SLX16-3FTG256C & W25Q80VSS chip.

3. The high-speed communication module of the ARM chip and the FPGA chip according to claim 2, wherein the signal pin D16, the signal pin D17, the signal pin D18, the signal pin D19, the signal pin D20, the signal pin D21, the signal pin D22, the signal pin D23, the signal pin D24, the signal pin D25, the signal pin EIM _ 25, the signal pin EIM _ D25, the EIM _ 25, the signal pin EIM _ D _ EIM _ 25, the signal pin EIM _ D25, the signal pin EIM _ 25, the signal 25, the signal pin EIM _ 25, the signal 25, the EIM _ D25, the signal 25, the EIM _ 25, the signal _ 25, the EIM _ D _ 25, the signal pin E _ EIM _ D _ 25, the signal _ EIM _ 25, the signal pin E _ D _ 25, the EIM _ 25, the signal of the FPGA chip (10) of the FPGA chip, the, And the EIM _ D30 signal pin and the EIM _ D31 signal pin are respectively connected and are used for realizing 16-bit data signal transmission.

4. The high-speed communication module of ARM chip and FPGA chip of claim 2, characterized in that, the EB0 signal pin, the EB1 signal pin, the EB2 signal pin, the EB3 signal pin of ARM chip (10) are respectively connected with the EIM _ EB0 signal pin, the EIM _ EB1 signal pin, the EIM _ EB2 signal pin, the EIM _ EB3 signal pin of FPGA chip (20) for realizing the block data transmission.

5. The high-speed communication module of ARM chip and FPGA chip of claim 2, characterized in that, the BCLK signal pin of ARM chip (10) is connected with EIM _ BCLK signal pin of FPGA chip (20) for realizing clock signal transmission.

6. The high-speed communication module of ARM chip and FPGA chip as claimed in claim 2, characterized in that, the CS0 signal pin, CS1 signal pin, WE _ B signal pin, WAIT signal pin, OE _ B signal pin of ARM chip (10) are connected with EIM _ CS0 signal pin, EIM _ CS1 signal pin, EIM _ WE _ B signal pin, EIM _ WAIT signal pin, EIM _ OE _ B signal pin of FPGA chip (20) respectively for enabling signal transmission.

7. The high-speed communication module of ARM chip and FPGA chip according to claim 2, wherein the DA0 signal pin, DA1 signal pin, DA2 signal pin, DA3 signal pin, DA4 signal pin, DA5 signal pin, DA6 signal pin, DA7 signal pin, DA8 signal pin, DA9 signal pin, EIM _ DA _ 9 signal pin, EIM _ 9 signal pin, EIM _ 9 signal 9, EIM _ 9 signal pin, EIM _ 9 signal 9, EIM _ 9 signal pin, EIM _ 9 signal 9, EIM _ 9 signal 9, EIM _ 9, EIM _ 9 signal pin, EIM _ 9 signal 9, EIM _ 9 signal pin, EIM _ 9 signal pin, EIM _ 9 signal 9, EIM _ 9, EIM _ 9 signal pin, EIM _ 9, EIM _ 9, EIM _ 9 signal pin, EIM _ 9 signal pin, EIM _ 9 signal pin, EIM _ 9 signal pin, EIM _ 9 signal 9, EIM _ 9, EIM _ 9, EIM _ 9 signal pin, EIM _ 9, EIM _, And the EIM _ DA14 signal pin and the EIM _ DA15 signal pin are respectively connected and used for realizing address signal transmission.

8. The module for high-speed communication between an ARM chip and an FPGA chip according to claim 2, wherein the CPU _ FPGA0 signal pin, the CPU _ FPGA1 signal pin, the CPU _ FPGA2 signal pin, the CPU _ FPGA3 signal pin, the CPU _ FPGA4 signal pin, the CPU _ FPGA5 signal pin, the CPU _ FPGA6 signal pin, the CPU _ FPGA7 signal pin of the ARM chip (10) are connected to the CSI0_ DAT4 signal pin, the CSI0_ DAT5 signal pin, the CSI0_ DAT6 signal pin, the CSI0_ DAT7 signal pin, the CSI0_ DAT12 signal pin, the CSI0_ DAT13 signal pin, the CSI0_ DAT16 signal pin, the CSI0 DAT17 signal pin of the FPGA chip (20), respectively, for realizing interrupt signal transmission.

9. A variable frequency controller, comprising: the high-speed communication module of the ARM chip and the FPGA chip of any one of claims 1 to 7.

10. The variable frequency controller of claim 9, wherein the FPGA chip (20) is configured to transmit the control signals output by the ARM chip (10) in parallel to a plurality of external variable frequency devices.

11. The variable frequency controller of claim 10, further comprising:

and the external expansion board (201) is connected with the FPGA chip (20) and is used for expanding various field buses or Ethernet buses.