CN205573840U - Watchdog circuit based on two CPU controllers - Google Patents
Watchdog circuit based on two CPU controllers Download PDFInfo
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- CN205573840U CN205573840U CN201620344944.5U CN201620344944U CN205573840U CN 205573840 U CN205573840 U CN 205573840U CN 201620344944 U CN201620344944 U CN 201620344944U CN 205573840 U CN205573840 U CN 205573840U
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- cpu controller
- cpu
- triode
- controller
- communication interface
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Abstract
The utility model discloses a watchdog circuit based on two CPU controllers. It includes main CPU, follows CPU and triode, main CPU's SPI communication interface and the SPI communication interface from CPU are connected, the base of triode is connected from CPU's IO output port, main CPU's RESET pin is connected to the collecting electrode of triode, the emitter electrode of the triode is grounded. The utility model discloses utilize the realization watchdog function of two CPU controller resources current on the vehicle, does not need NULL, simple structure, only use little use always, low -priced components and parts, the cost is reduced.
Description
Technical field
This utility model belongs to technical field of automotive electronics, is specifically related to a kind of based on dual processors control
The watchdog circuit of device processed.
Background technology
At present, automobile electronic controller realizes watchdog function, generally by integrated
Watchdog chip realizes or uses discrete component to build circuit realiration, uses integrated
Watchdog chip cost is higher, and uses discrete component to build circuit realiration watchdog merit
Can, components and parts are more, and circuit structure is more complicated.
Summary of the invention
The purpose of this utility model is contemplated to solve the deficiency that above-mentioned background technology exists, it is provided that
A kind of watchdog circuit based on double CPU controller.
The technical solution adopted in the utility model is: a kind of based on double CPU controller
Watchdog circuit, including host CPU controller, from cpu controller and audion, described
The SPI communication interface of host CPU controller is connected with the SPI communication interface from cpu controller,
The base stage of described audion connects the I/O output port from cpu controller, described audion
Colelctor electrode connects the RESET pin of host CPU controller, the grounded emitter of described audion.
This utility model utilizes the realization of existing double CPU controller resource on vehicle
Watchdog function, is not required to integrated chip, simple in construction, only uses little commonly using, inexpensively
Components and parts, reduce cost.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Fig. 2 is flow chart during this utility model operation.
Detailed description of the invention
With specific embodiment, this utility model is made the most below in conjunction with the accompanying drawings
Bright, it is simple to be well understood to this utility model, but they do not constitute restriction to this utility model.
As it is shown in figure 1, this utility model includes host CPU controller U1, from cpu controller
U2 and audion Q1, the SPI communication interface of described host CPU controller U1 with from CPU
The SPI communication interface of controller U2 connects, and the base stage of described audion Q1 passes through resistance R1
Connecting the I/O output port from cpu controller U2, the colelctor electrode of described audion Q1 is even
Connect the RESET pin of host CPU controller U1, the grounded emitter of described audion Q1.
Realize information by host CPU controller and the SPI communication interface from cpu controller to hand over
Mutually, utilize from an I/O output port of cpu controller by a NPN audion pair
The RESET pin of host CPU controller is controlled.The timing of host CPU controller is to from CPU
Controller sends particular data, if normally receiving data from cpu controller, then from CPU
Controller I/O output port output low level, protects the RESET pin of host CPU controller
Hold properly functioning control；If owing to host CPU controller failure causes from cpu controller not
Data can be normally received, export high level from cpu controller I/O output port, to host CPU
RESET pin once reset operation, it is achieved watchdog function.
Such as Fig. 2, in system operation, first host CPU controller, from CPU control
The mouth die initialization block of device opposite end.After initialization completes, host CPU controller is sent out by SPI interface
Send 0XC3 notice to enter application program from cpu controller, and watchdog function starts
Work.If being not received by 0XC3 from CPUCPU controller, keep watchdog function
Closing, host CPU controller is in diagnostic mode.
Initializing by rear, system is in normal operating condition.Host CPU controller can be with 10ms
Cycle sends 0XA5, and after cpu controller normally receives, I/O output port can be the most defeated
The RESET pin going out low level holding host CPU controller is high level, maintains system normal
Run.If host CPU controller breaks down, can not periodic receipt from cpu controller
To 0XA5, the high level of about 1ms, host CPU controller can be exported at I/O output port
RESET pin occur that 1ms low level, host CPU controller reset, the most immediately
Change.
Above content be combine that the present invention done by specific embodiment the most specifically
Bright, it is impossible to assert the present invention be embodied as be confined to these explanations.For belonging to the present invention
Technical field those of ordinary skill for, without departing from the inventive concept of the premise, also
Some simple deduction or replace can be made, all should be considered as belonging to protection scope of the present invention.
The content not being described in detail in this specification belongs to existing known to professional and technical personnel in the field
Technology.
Claims (1)
1. a watchdog circuit based on double CPU controller, it is characterised in that: include
Host CPU controller, from cpu controller and audion, the SPI of described host CPU controller
Communication interface is connected with the SPI communication interface from cpu controller, and the base stage of described audion is even
Connecing the I/O output port from cpu controller, the colelctor electrode of described audion connects host CPU
The RESET pin of controller, the grounded emitter of described audion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620344944.5U CN205573840U (en) | 2016-04-21 | 2016-04-21 | Watchdog circuit based on two CPU controllers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620344944.5U CN205573840U (en) | 2016-04-21 | 2016-04-21 | Watchdog circuit based on two CPU controllers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205573840U true CN205573840U (en) | 2016-09-14 |
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ID=56861019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620344944.5U Active CN205573840U (en) | 2016-04-21 | 2016-04-21 | Watchdog circuit based on two CPU controllers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205573840U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106874235A (en) * | 2017-02-09 | 2017-06-20 | 北京开疆智能自动化科技有限公司 | A kind of simulation DPRAM communication systems and method based on SPI serial links |
-
2016
- 2016-04-21 CN CN201620344944.5U patent/CN205573840U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106874235A (en) * | 2017-02-09 | 2017-06-20 | 北京开疆智能自动化科技有限公司 | A kind of simulation DPRAM communication systems and method based on SPI serial links |
| CN106874235B (en) * | 2017-02-09 | 2020-11-03 | 北京开疆智能自动化科技有限公司 | Analog DPRAM communication system and method based on SPI serial link |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |