CN2641934Y

CN2641934Y - Multiple serial interface data communicating transmitter

Info

Publication number: CN2641934Y
Application number: CN 03261023
Authority: CN
Inventors: 刘刚; 司永胜; 邢一春; 张丽梅
Original assignee: China Agricultural University
Current assignee: China Agricultural University
Priority date: 2003-08-07
Filing date: 2003-08-07
Publication date: 2004-09-15
Anticipated expiration: 2013-08-07

Abstract

The utility model discloses a multi-serial ports data communication transmitter, which includes a CPU, a serial port expended circuit, an interrupted discrimination circuit, a level switching circuit and a power supply circuit. Wherein the level switching circuit includes three level switching chips, the CPU is connected with the serial port expended circuit; the serial port expended circuit is connected with the interrupted discrimination circuit, one of the three level switching chips in the level switching circuit is connected between the CPU and a host computer, another two level switching chips are connected between the serial port expended circuit and an external serial port equipment, and the power supply provides power for each circuit. The utility model has simple structure design, convenient application, and can realize that the multi-serial ports data communication transmitter can communicate with the host computer, a plurality of digital sensors, and the GPS simultaneously through setting parameters at the host computer by the user.

Description

Many serial datas communication transport

Technical field

The utility model relates to a kind of many serial datas communication transport, particularly relate to a kind of many serial datas communication transport that host computer and several digital sensor or GPS, GSM etc. have the RS232 standard output device that is used for to connect simultaneously, belong to the data communications equipment field.

Background technology

In various fields such as Industry Control, data acquisition, instrument and meter and gps satellite location, usually need computer and equipment such as extraneous several sensors, instrument to carry out the while serial communication, for example, in modern precision agriculture, need gather moisture data, gps satellite locator data and GSM data simultaneously, and common desktop computer, notebook computer, palmtop PC itself only have one to two serial ports, and therefore, the data channel of many serial ports is all very necessary to above-mentioned every field.

In the prior art, existing CPU is expanded to the special chip of 3 serial ports, still, need the user to programme during use, and, when carrying out communication, need carry out level conversion with host computer such as palmtop PC, desktop computer, notebook computer and external equipment.Also having, is exactly that it can not realize that while such as palmtop PC, notebook computer and the equipment such as digital sensor more than three carry out communication.

The utility model content

The technical problems to be solved in the utility model is to propose a kind of many serial datas communication transport, the equipment that makes this transmitter can guarantee that whiles such as palmtop PC, notebook computer, desktop computer and a plurality of GPS, digital sensor, GSM etc. have RS232 output carries out communication, and does not need the user to programme.

The purpose of this utility model is achieved by the following technical solution: a kind of many serial datas communication transport, comprise CPU, serial expanded circuit, interrupt discriminator circuit, level shifting circuit and power circuit, wherein level shifting circuit is made up of three level transferring chip, CPU is connected with serial expanded circuit, serial expanded circuit is connected with the interruption discriminator circuit, a slice level transferring chip is connected between CPU and the host computer in the level shifting circuit, other two level transferring chip are connected between serial expanded circuit and the outside serial equipment, and power supply is each circuit supply.

The utility model structural design is simple, and is easy to use.Carry out the parameter setting by the user at host computer, can make this data transmission set can realize that while host computer and equipment such as a plurality of digital sensor, GPS carry out the while communication.

Description of drawings

Fig. 1 is many serial datas of the utility model communication transport structure connection diagram;

Fig. 2 is the circuit theory diagrams of many serial datas of the utility model communication transport.

Embodiment

As shown in Figure 1, the basic structure of many serial datas of the utility model communication transport comprises CPU, serial expanded circuit, interruption discriminator circuit, level shifting circuit and power circuit, among Fig. 1, the utility model has 5 external interfaces, be the RS232 interface, wherein 1 interface connects host computer, equipment such as all the other 4 connection digital sensors, GPS, and the user can use wherein 1 to 4 as required.

Fig. 2 is circuit theory diagrams of the present utility model.

The utility model has selected for use the 87C51 chip of MCS51 series as CPU, serial expanded circuit is made up of two PC16552D, interrupting discriminator circuit is the 74LS28 NAND gate, and level shifting circuit comprises three MAX232 chips of realizing Transistor-Transistor Logic level and EIA level conversion.

87C51 is the CPU that has EPROM in the sheet, adopt 40 pin DIP encapsulation modes, owing to carry EPROM in the sheet, need not expand the outer program storage of sheet, can make circuit simple, the main pin of 87C51 has power supply signal Vcc, Vss, reset signal RST, clock signal XTAL1, XTAL2, sheet to get location control signal PSEN, address latch control signal ALE, chip external memory selection signal EA and P0, P1, P2, P3 totally 48 I/O mouths outward.

The serial ports expansion chip adopts P16C552D, used main pin has: data/address bus D0～D7, register selection signal A0, A1, A2, channel selecting signal CHSL, signal RD, WR are selected in read-write, external interrupt signal INTR0, INTR1, chip selection signal CS, reset signal MR, serial input signals SIN1, SIN2, serial output signal SOUT1, SOUT2, external crystal-controlled oscillation signal XIN, XOUT.

This novel practical is as follows to the connection situation of each I/O mouth of 87C51:

P0: meet D0～D7 of serial ports expansion chip P162552D, be used to carry out transfer of data.

P1.0～P1.3: connect input 3,2,6,5 pins that interrupt differentiating chip 74LS28, and these 4 pins link to each other with the interrupt signal INTR of two serial ports expansion chip PC16552D simultaneously, just can judge the source of interruption according to everybody level of P1.0～P1.3.

P2.0～P2.2: meet A0, A1, the A2 of PC16552D, PC16552D is carried out register select.

P2.3: meet the CHSL of PC16552D, carry out channel selecting.

P2.4: meet the CS of a slice PC16552D, carry out the sheet choosing.

P2.5: meet the CS of another sheet PC16552D, carry out the sheet choosing.

The serial input terminal RXD of RXD, TXD:CPU and serial output terminal TXD connect pin 9 (R2OUT) and the pin one 0 (T2IN) of MAX232 respectively, carry out level conversion after, and host computer (notebook computer, palmtop PC etc.) carries out communication.

INT0, INT1: connect pin 4 and the pin one of 74LS28 respectively, with its signal as external interrupt signal.

WR: meet the WR of PC16552D, as writing control.

RD: meet the RD of PC16552D, as reading control.

In addition, serial expanded circuit is made up of two PC16552D, the SIN1 of PC16552D, SIN2, SOUT1 and SOUT2 as the expansion serial ports connect level shifting circuit, carry out level conversion after, with outside serial equipment communication.

Interrupting discriminator circuit is made up of the 74LS28 NAND gate, output 1 pin of 74LS28 and 4 pin meet external interrupt signal INT0 and the INT1 of CPU as external interrupt signal, interrupt signal INTR1 and INTR2 that input 2,3 pin of 74LS28 and 5,6 pin meet two PC16552D respectively connect I/O mouth P1.0～P1.3 of CPU simultaneously.

As serial input terminal RXD and the serial output terminal TXD of CPU, needs and host computer (notebook computer, palmtop PC etc.) carry out data communication respectively for RXD and TXD; The SIN1 of PC16552, SIN2, SOUT1 and SOUT2 need as the serial ports of expanding and data pick-up, GPS etc. carry out communication.The operation level of CPU, PC16552D is a Transistor-Transistor Logic level, its scope is 0～5V, and host computer, the serial line interface of digital sensor, GPS etc. is the RS-232C standard interface, operation level is the EIA level, be logical one be-15～-3V (usually with-12V), logical zero be+3～+ 15V (usefulness+12V) usually.For guaranteeing the correct transmission of data, realize under the RS-232C mode between the RS-232C standard interface and CPU I/O mouth and the coupling of input/output signal level between the I/O mouth of RS-232C standard interface and PC16552D, the utility model is between CPU87C51 and host computer, level transferring chip (MAX232) has been installed, to realize the mutual conversion between Transistor-Transistor Logic level and the EIA level between serial expanded circuit and outside serial equipment.

Level shifting circuit comprises three MAX232 chips that are used to realize Transistor-Transistor Logic level and EIA level conversion, between host computer and CPU, be connected a slice MAX232 U6, the serial input terminal RXD of CPU and serial output terminal TXD meet Transistor-Transistor Logic level output signal R2OUT and the Transistor-Transistor Logic level input signal T2IN of U6, the EIA level output signal T2OUT of U6 links to each other with host computer with EIA level input signal R2IN simultaneously, and the EIA level output signal T1OUT of U6 is connected an expansion mouth with EIA level input signal R1IN in addition;

Between serial expanded circuit and outside serial equipment, use two MAX232 U5 and U7 to carry out level conversion, the serial input signals SIN1 of serial expanded circuit meets the R2OUT of U7, serial output signal SOUT1 meets the T2IN of U7, and the R2IN of U7, T2OUT are connected two expansion mouths respectively with R1IN, TIOUT; The serial input signals SIN2 of serial expanded circuit meets the R1OUT of U7, and serial output signal SOUT1 meets the T1IN of U7, and the R1IN of U5, TIOUT connect an expansion mouth again.

Power pack as power supply, constitutes " power circuit " by 1 LM317 chip, to provide 5V power supply to the entire circuit plate by the 12V rechargeable battery of 2 series connection.

The utility model carries out simple baud rate by the program on the host computer and selects with after host computer, outside serial equipment etc. is connected, and just can carry out data communication.

Among Fig. 2,

expansion mouthful

1,2,3,4 connection digital sensors, GPS etc. have the equipment of RS232 standard interface.The interface that indicates " connecing host computer " is connected with host computer.

Operating procedure is as follows:

1, connects host computer and equipment such as digital sensor or GPS.

2, energized.

3, set the communication baud rate of each serial ports on host computer by selection, default value is 9600.

It should be noted last that: above embodiment is the unrestricted the technical solution of the utility model in order to explanation only, although the utility model is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the utility model, and not breaking away from any modification or partial replacement of spirit and scope of the present utility model, it all should be encompassed in the middle of the claim scope of the present utility model.

Claims

1, a kind of many serial datas communication transport is characterized in that: comprise CPU, serial expanded circuit, interruption discriminator circuit, level shifting circuit and power circuit, wherein, level shifting circuit comprises three level transferring chip; CPU is connected with serial expanded circuit, serial expanded circuit is connected with the interruption discriminator circuit, a slice level transferring chip in the level shifting circuit is connected between CPU and the host computer, other two level transferring chip are connected between serial expanded circuit and the outside serial equipment, and power supply is each circuit supply.

2, many serial datas communication transport according to claim 1 is characterized in that: CPU is the 87C51 chip of MCS51 series, and 8 I/O mouths of one of them of 87C51 P0 connects the data/address bus D0-D7 of serial expanded circuit; P1.0～P1.3 of its another I/O mouth P1 links to each other with the input pin that interrupts discriminator circuit; P2.0～P2.2 meets register selection signal A0, A1, the A2 of serial expanded circuit; P2.3 meets the channel selecting signal CHSL of serial expanded circuit; P2.4, P2.5 meet the chip selection signal CS of serial expanded circuit; Serial input terminal RXD and the serial output terminal TXD of CPU connect level shifting circuit, carry out level conversion after, and upper machine communication;

INT0, INT1 receive the output that interrupts discriminator circuit respectively as the receiving terminal of external interrupt signal; WR is as writing the write signal WR that control connects serial expanded circuit; RD is as reading to control the read signal RD that connects serial expanded circuit.

3, many serial datas communication transport according to claim 1, it is characterized in that: described serial expanded circuit is made up of two PC16552D chips, the SIN1 of every PC16552D, SIN2, SOUT1 and SOUT2 connect level shifting circuit as the serial ports of expansion, after carrying out level conversion, with outside serial equipment communication.

4, according to claim 1,2 or 3 described many serial datas communication transports, it is characterized in that: described interruption discriminator circuit is made up of the 74LS28 NAND gate, 1 pin of 74LS28 and 4 pin meet external interrupt signal INT0 and the INT1 of CPU as external interrupt signal, 2,3 pin of 74LS28 and 5,6 pin meet interrupt signal INTR1 and the INTR2 of two PC16552D respectively, connect I/O mouth P1.0～P1.3 of CPU simultaneously.

5, many serial datas communication transport according to claim 1, it is characterized in that: described level shifting circuit comprises three MAX232 chips that are used to realize Transistor-Transistor Logic level and EIA level conversion, between host computer and CPU, be connected a slice MAX232 U6, between serial expanded circuit and outside serial equipment, use two MAX232 U5 and U7 to carry out level conversion.

6, many serial datas communication transport according to claim 5, it is characterized in that: among the described MAX232 U6 that is connected between host computer and the CPU, the serial input terminal RXD of CPU and serial output terminal TXD meet Transistor-Transistor Logic level output signal R2OUT and the Transistor-Transistor Logic level input signal T2IN of U6, the EIA level output signal T2OUT of U6 links to each other with host computer with EIA level input signal R2IN simultaneously, in addition, the EIA level output signal T1OUT of U6 is connected an expansion mouth with EIA level input signal R1IN.

7, many serial datas communication transport according to claim 6 is characterized in that:

The serial input signals SIN1 of serial expanded circuit meets the R2OUT of U7, and serial output signal SOUT1 meets the T2IN of U7, and the R2IN of U7, T2OUT are connected two expansion mouths respectively with R1IN, TIOUT; The serial input signals SIN2 of serial expanded circuit meets the R1OUT of U7, and serial output signal SOUT1 meets the T1IN of U7, and the R1IN of U5, TIOUT connect an expansion mouth again.