CN2569346Y - Integrated module plate for mebedded with IC chip and passive element - Google Patents

Integrated module plate for mebedded with IC chip and passive element Download PDF

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Publication number
CN2569346Y
CN2569346Y CN02241480U CN02241480U CN2569346Y CN 2569346 Y CN2569346 Y CN 2569346Y CN 02241480 U CN02241480 U CN 02241480U CN 02241480 U CN02241480 U CN 02241480U CN 2569346 Y CN2569346 Y CN 2569346Y
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China
Prior art keywords
chip
substrate
passive component
integrated module
module board
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Expired - Lifetime
Application number
CN02241480U
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Chinese (zh)
Inventor
何昆耀
宫振越
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Via Technologies Inc
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Via Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model relates to an integrated module plate for embedded with IC chips and passive elements. The utility model comprises a basal plate comprising a plurality of large openings and small openings, wherein, passive elements are arranged in the small openings, a first sticky rubber film is used for sticking the bottom of the basal plate on a heat radiating basal plate in order to form the integrated module plate. The bottoms of IC chips are stuck in the large openings of the integrated module plate via a second sticky rubber film. A dielectric filling layer is covered on the entire surface of the integrated module plate and filled in all gaps on the surface of the integrated module plate.

Description

Be embedded with the integrated module board of IC chip and passive component
Technical field
The utility model relates to a kind of integrated module board (moduled board) and preparation method thereof, be particularly related to a kind of similar plastics welded ball array that Open Side Down (Cavity-Down Plastic Ball GridArray, CD-PBGA) or contain modularization (moduled) substrate of various openings and preparation method thereof, various IC chip and various passive component can be integrated in the modular substrate.
Background technology
Electronic packaging comprises that the bonding of integrated circuit (IC) chip is fixed, circuit connection, sealing structure, with all technologies between the engaging of circuit board, system in combination and product are finished; its purpose is finished IC chip and necessary circuit part for combination, to realize transmission electric energy and circuit signal, functions such as heat radiation approach, carrying and structural defence are provided.
Generally speaking, the assembling levels that the electronic packaging technology is can four different are distinguished: first level is meant the IC chip attach in a base plate for packaging, and finish wherein circuit connection and the technology of seal protection; Second level is meant packaging body and other electronic building bricks is incorporated on the circuit board; Tri-layer then refers to a plurality of circuit board group are loaded on becomes primary system on the mainboard; The 4th level is then for to be combined into a complete electronic product with a plurality of subsystems.
Improve and make the pin number increase of the output input of chip along with the integrated level of IC chip, therefore various highdensity IC base plate for packaging are continually developed out, the plastics welded ball array that wherein Open Side Down (Cavity Down-Plastic Ball Grid Array, CD-PBGA) base plate for packaging is exactly an example, it is with the IC chip attach so far in the opening of substrate, and utilize Wire Bonding Technology that the IC chip is electrically connected so far on the bonding joint of substrate surface (bonding finger), then this base plate for packaging can combine with circuit board in the mode that Open Side Down.In addition, the heat dissipation element device is above this base plate for packaging, and passive component needs to carry out assembly program in circuit board separately.
Existing technology can meet with following problem: first, the assembly program of IC chip package process, passive component and surface adhesion technology (surface mount technology, SMT) etc. step must be carried out respectively, therefore overall product is lower than length thereby acceptance rate because of flow process, and the cost of the cost of packaging technology is high.The second, under the situation of the assembling that can't integrate passive component and SMT technology, the thickness of entire product can't reduce, and can not meet the trend of " light, thin, short, little " of current techniques.The 3rd, in order to reach radiating effect, heat sink (heat sink)/fan (fan) element and an Electromagnetic Interference (Electro-Magnetic Interference must additionally be provided on mainboard, EMI) barricade is to improve the electrical characteristic performance, and this can further increase the overall craft cost.The 4th, because IC chip, passive component and heat dissipation element can't be integrated on the substrate simultaneously, so the layout circuit line of product is oversize and have influence on its electrical quality.
Therefore, how the technology of IC chip, passive component and heat dissipation element is integrated in simultaneously on the modular substrate, becomes the current important topic of needing discussion badly to solve the above problems.
The utility model content
Main purpose of the present utility model is to provide a kind of integrated module board, pasted by heat-radiating substrate and similar CD-PBGA or the substrate that contains various perforate and to be formed, and IC chip and passive component are embedded in integrated module board, so can directly on integrated module board, carry out the multiple layer inner connection Wiring technology, to solve the problem that prior art produces.
The integrated module board of the utility model preferred embodiment, include: a substrate that Open Side Down such as plastics welded ball array (CD-PBGA) substrate or contain the substrate of various openings, it includes a plurality of big openings that run through and little opening, wherein is provided with passive component in this little opening; One heat-radiating substrate is arranged at the bottom of this substrate; One first viscosity glued membrane is bonded to the bottom of this substrate on this heating panel; At least one active IC chip, the bottom of this IC chip is pasted in the big opening of the substrate on this fin by one second viscosity glued membrane; And a dielectric packed layer, cover the whole surface of this integrated module board, and fill up on the surface of this substrate and all spaces in the opening; And, can directly on this dielectric packed layer, carry out the multiple layer inner connection Wiring technology, IC chip, passive component and substrate are electrically connected mutually.
According to above-mentioned purpose, of the present utility model being characterised in that, heat-radiating substrate and perforate substrate directly pasted and become a kind of integrated module board, and IC chip and passive component are embedded in integrated module board, so can directly on integrated module board, carry out the multiple layer inner connection Wiring technology, with bonding, passive component assembling and the heat radiation wind that the replaces prior art steps such as assembling of loosing, and then reach making flow process, the acceptance rate that improves product of simplifying baseplate, reduce structure and adorn purposes such as technology cost.
Another feature of the present utility model is, by the viscosity glued membrane IC chip and passive component is pasted in the opening of integrated module board, can not use surface adhesion technology (SMT) and reflow (Reflow) etc. to make flow process, and reduces cost of manufacture.
Of the present utility modelly one be characterised in that again, integrate the thickness of controlling integrated module board, can effectively reduce the volume of product by the height of IC chip and passive component.
Another being characterised in that of the present utility model furthered the signal transmission distance between each IC chip, the passive component, can significantly improve the electrical performance of product.
Another being characterised in that of the present utility model furthered the signal transmission distance between each IC chip, the passive component, and according to the performance level of circuit design, may be a modular subsystem.
Another being characterised in that of the present utility model furthered the signal transmission distance between each IC chip, the passive component, and according to the performance level of circuit design, may be the modular systemic-function mainboard of a high degree of integration.
Description of drawings
Fig. 1 to Fig. 9 shows the generalized section of manufacture method of the integrated module board of the utility model embodiment.
Description of reference numerals in the accompanying drawing is as follows:
IC chip～12; Metal gasket～14; Alignment mark～17; Electric test metal coupling～16; Second viscosity glued membrane～18; Perforate substrate～22; Passive component～24; Passive component adhesion coating～25; Metal gasket～26; Alignment mark～27; First viscosity glued membrane～28; Integrated modular substrate～30; Heating panel～31; Space～34; Dielectric packed layer～36; Micropore～38,43; The first metal layer～40; First plain conductor～40A; Dielectric layer～42; Second metal level～44; Second plain conductor～44A; Shielding layer～46; Soldered ball～48.
Embodiment
For allowing above-mentioned and other purposes of the present utility model, feature and the advantage can be clearer understandable, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
Embodiment
The utility model provides a kind of similar plastics welded ball array (CD-PBGA) that Open Side Down or contains modular substrate of a plurality of perforates and preparation method thereof, be that passive component directly is made on this substrate, and this substrate and heating panel is bonding and constitute an integrated module board, again with the IC die bonding in the opening of integrated module board.Then can carry out the multiple layer inner connection Wiring technology, make IC chip and passive component can be electrically connected to integrated module board, be connected to surperficial welded ball array and directly use or design in addition on demand, this integrated module board is combined with other circuit boards in the mode that Open Side Down.Therefore, according to the quantity of IC chip and the application change of modularization technology, integrated module board of the present utility model can be considered a kind of modularizing member, a kind of multi-chip module (MCM) substrate or a kind of mainboard (mainboard), can be applicable in each different assembling level of electronic packaging technology.
See also the 1st to 9 figure, the generalized section of the manufacture method of the modular substrate of its demonstration the utility model embodiment.
As shown in Figure 1, integrated modular substrate 30 of the present utility model is made up of a substrate 22, one first viscosity glued membrane 28 and 31 of heat-radiating substrates.Substrate 22 includes a plurality of big openings 19 and little opening 21, the position of wherein big opening 19 is to be used for placing the IC chip, the position of little opening 21 is to be used for placing passive component (for example: resistance, electric capacity, inductor), can do suitably to change according to actual needs as for big opening 19 and the shape and the number of little opening 21, do not limited at this.In a preferred embodiment, include a plurality of metal gaskets 26, alignment mark 27 (alignment mark) and passive component 24 on substrate 22 surfaces, wherein passive component 24 is pasted in the little opening 21 by an adhesion coating 25; Passive component also can be used to embed (Embedded) mode because of different technologies and be formed in the board structure of variant layer.Conducting wire structure as for substrate 22 inside then can be designed to various patterns, is not write in this.The first viscosity glued membrane 28 is used for bonded substrate 22 and heat dissipation element 31, and its material can adopt conductive adhesive film, is filled with conducting resinl in its inside holes.Heating panel 31 can have the EMI shield effectiveness, and the material of heating panel 31 is mainly radiating copper sheet.
As shown in Figure 2, utilize the first viscosity glued membrane 28 that the bottom of substrate 22 is pasted on the heating panel 31, then can become an integrated modular substrate 30, still remain with the big opening 19 that is used for placing the IC chip on its surface.
As shown in Figure 3, provide at least one IC chip 12, its surface is provided with a plurality of metal gaskets 14, electric test metal coupling 16 and alignment mark 17 (alignment mark).Then, utilize one second viscosity glued membrane 18 that the bottom surface of IC chip 12 is pasted on the integrated modular substrate 30 in the big opening 19, and the space between IC chip 12 and the integrated modular substrate 30 can form a groove 34.In a preferred embodiment, the rough height with substrate 22 of the thickness of IC chip 12 is identical, helps follow-up modularization process integration.The second viscosity glued membrane 18 can adopt general adhesive tape, epoxy radicals glass cloth glue (epoxy-based prepreg), contain conductive particle glued membrane or metallic conduction cream or the like.
Then, IC chip 12 and passive component 24 are carried out seal protection.As shown in Figure 4, on the whole surface of integrated modular substrate 30, cover a dielectric packed layer 36, and make it fill up IC chip 12 space 34 and passive component 24 space on every side on every side.The manufacture method of dielectric packed layer 36 has dual mode available, first kind of mode is earlier resin (epoxy) material to be flowed in the space 34, on above-mentioned material, cover one deck dielectric (dielectric) material again, the second way then is that resin material and dielectric material are provided simultaneously, and this moment, resin material also can flow in the space 34.
Then, carry out the external connection lead technology of IC chip 12 and passive component 24.As shown in Figure 5, utilize methods such as laser drill (laser drilling), plasma etching or photoetching, in dielectric packed layer 36, form a plurality of micropores 38 (micro via), expose the surface of electric test metal coupling 16, metal gasket 26 and passive component 24 respectively.Then, as shown in Figure 6, utilize sputter (sputtering), vapour deposition (vapor deposition), electroplate (plating) or printing (printing) mode, deposition one the first metal layer 40 on the whole surface of integrated modular substrate 30, so that the first metal layer 40 covers dielectric packed layer 36, and make the first metal layer 40 fill up all micropores 38.Subsequently, as shown in Figure 7, utilize photoetching and etch process, the first metal layer 40 definition are formed a plurality of wire patterns, to finish the making of the first plain conductor 40A.
Next, proceed the external connection lead technology of the second layer.As shown in Figure 8,, make a dielectric layer 42, micropore 43, second metal level 44 or the like in regular turn, just can form a plurality of wire patterns, just finish the making of the second plain conductor 44A in the top of the first plain conductor 40A according to above-mentioned identical connection lead technology.Go up definition in the second plain conductor 44A and form a shielding layer, expose some second metal position to the open air, so just can directly use in order to external connection.
Or design in addition on demand, on the second plain conductor 44A, carry out array soldered ball (solder ball) technology.As shown in Figure 9, can utilize wire mark or deposition photolithographicallpatterned, go up definition prior to the second plain conductor 44A and form a shielding layer 46, the second plain conductor 44A with the precalculated position that exposes soldered ball 48, on the precalculated position, carry out the coating of tin cream then, again soldered ball 48 is positioned on each precalculated position, by scolding tin reflow (reflow) step soldered ball 48 is fixed on the surface of integrated modular substrate 30 at last.Then this integrated modular substrate 30 in the mode that Open Side Down with any circuit board can be combined thereafter.
As shown in the above description, integrated modular substrate 30 of the present utility model is pasted with the substrate 22 that contains perforate by heat-radiating substrate 31 to form, and IC chip 12 and passive component 24 are embedded in integrated modular substrate 30, therefore can directly on integrated modular substrate 30, carry out the multiple layer inner connection Wiring technology, with the steps such as bonding, injecting glue, passive component assembling and the diffusing assembling of heat radiation wind that replace prior art.Therefore, the utility model also can be considered a kind of system combination type encapsulation technology (SIP or title SOP), it is that chip with difference in functionality in the system is integrated in the modularization encapsulating products, can significantly dwindle the required area of follow-up pcb board, and reduce the assembly cost of passive component.
Compared to prior art, integrated modular substrate 30 of the present utility model and preparation method thereof has the following advantages: first, IC chip 12 and passive component 24 directly are pasted in the big opening 19 and little opening 21 of integrated modular substrate 30, so can simplify the modularization flow process, and reduce the modularization cost.The second, the electric test metal coupling 16 of finishing IC chip 12 through electric test when design alternative is connected to soldered ball 48, also is convenient to the testing electrical property of follow-up IC chip 12 directly by the first plain conductor 40A and the second plain conductor 44A and be electrically connected.The 3rd, simultaneously IC chip 12 and passive component 24 are embedded in integrated modular substrate 30, can therefore can effectively reduce the volume of modular product by the thickness of highly controlling integrated modular substrate 30 that is provided with of integrated element.The 4th, this kind modular mode can further the signal transmission distance between each IC chip 12 and the passive component 24, significantly to improve the electrical performance of product.The 5th, the utility model method can be omitted the assembling of bonding, passive component and the heat radiation wind steps such as assembling of loosing, so can reach the purposes such as acceptance rate, reduction modularization technology cost of raising modular product.Integrated module board of the present utility model can be modular encapsulating products (comprising single-chip or multicore sheet), subsystem circuit board or the mainboard with systemic-function.
Though the utility model with a preferred embodiment openly as above; but it is not in order to limit the utility model; in not breaking away from spirit and scope of the present utility model; those skilled in the art should do a little change and retouching, and therefore protection range of the present utility model should be as the criterion so that claims are defined.

Claims (6)

1. integrated module board that is embedded with IC chip and passive component is characterized in that including:
One substrate, it includes at least one big opening that runs through and at least one little opening, wherein is provided with a passive component in this little opening;
One heating panel is arranged at the bottom of this substrate;
One first viscosity glued membrane is bonded to the bottom of this substrate on this heating panel;
At least one IC chip, the bottom of this IC chip is pasted on the big opening that is positioned at this substrate on this heating panel by one second viscosity glued membrane;
One dielectric packed layer covers the whole surface of this substrate, and fills up on the surface of this substrate and all spaces in each opening, wherein has a plurality of micropores in this dielectric packed layer, to expose the part surface of this IC chip, this passive component and this substrate; And
At least one layer conductor structure is formed at this dielectric packed layer surface, and this IC chip, this passive component and this substrate are electrically connected.
2. the integrated module board that is embedded with IC chip and passive component as claimed in claim 1 is characterized in that this passive component is pasted in the little opening of this substrate by an adhesive linkage.
3. the integrated module board that is embedded with IC chip and passive component as claimed in claim 1, it is characterized in that including a plurality of metal gaskets and a plurality of electric test metal coupling on the surface of this IC chip, wherein this electric test metal coupling is made on this metal gasket surface.
4. the integrated module board that is embedded with IC chip and passive component as claimed in claim 1 is characterized in that including in addition a plurality of soldered balls, and matrix-like is formed on the surface of this conductor structure.
5. the integrated module board that is embedded with IC chip and passive component as claimed in claim 1 is characterized in that this first viscosity glued membrane is a conductive adhesive film.
6. the integrated module board that is embedded with IC chip and passive component as claimed in claim 1 is characterized in that this dielectric packed layer includes a resin material and a dielectric material.
CN02241480U 2002-07-26 2002-07-26 Integrated module plate for mebedded with IC chip and passive element Expired - Lifetime CN2569346Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN02241480U CN2569346Y (en) 2002-07-26 2002-07-26 Integrated module plate for mebedded with IC chip and passive element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN02241480U CN2569346Y (en) 2002-07-26 2002-07-26 Integrated module plate for mebedded with IC chip and passive element

Publications (1)

Publication Number Publication Date
CN2569346Y true CN2569346Y (en) 2003-08-27

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Country Status (1)

Country Link
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AV01 Patent right actively abandoned

Effective date of abandoning: 20050706

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