CN1215557C - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1215557C
CN1215557C CNB021219214A CN02121921A CN1215557C CN 1215557 C CN1215557 C CN 1215557C CN B021219214 A CNB021219214 A CN B021219214A CN 02121921 A CN02121921 A CN 02121921A CN 1215557 C CN1215557 C CN 1215557C
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CN
China
Prior art keywords
intermediate substrate
substrate
pad
semiconductor device
chip
Prior art date
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Expired - Fee Related
Application number
CNB021219214A
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Chinese (zh)
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CN1388584A (en
Inventor
木村直人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
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Publication of CN1388584A publication Critical patent/CN1388584A/en
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Publication of CN1215557C publication Critical patent/CN1215557C/en
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

The semiconductor device according to the present invention is equipped with a plurality of electronic circuits including at least one semiconductor integrated circuit chip, and a plurality of intermediate substrates interposed between the electronic components and a package and mounting the electronic components directly on its one major face, where each of the electronic component has on the one major face at least a plurality of first electrodes connected to the electronic components, a plurality of second electrodes for external connection, and internal connection electrodes for connecting between the electronic components including the connection between the first electrodes and the second electrodes that are mutually corresponding.

Description

Semiconductor device
Technical field
The present invention relates to semiconductor device, be particularly related to by multi-chip module (MCM hereinafter referred to as) semiconductor device that a plurality of electronic components form is installed in same encapsulation, described a plurality of electronic components comprise the semiconductor integrated circuit (IC chip hereinafter referred to as) with required function.
Background technology
For the various devices that adopt semiconductor device,, light weight small-sized, thin type and high-performance in order further to realize, after deliberation comprise the high-density packages of the various electronic components of IC chip.As a strong measure that realizes above-mentioned purpose, the various MCM semiconductor device of a plurality of IC chips have been proposed in same encapsulation, to have.
For example, in the flat 8-250652 of Japanese Patent Application Publication No., proposed to realize to have the thin MCM encapsulation of the multi-chip semiconductor device of excellent heat dispersion, a kind of MCM semiconductor device has been proposed in the flat 9-181256 of Japanese Patent Application Publication No., even purpose is variety classes or layout for various IC chips to be installed, encapsulation that can be general by employing realizes low-cost.
Fig. 7 A and 7B have shown the example cross-sectional schematic of the semiconductor device of the disclosed MCM of utilization encapsulation in the flat 8-250652 of Japanese Patent Application Publication No..
Fig. 7 A has shown the schematic diagram of the first routine MCM encapsulation 710.Printed wire (PW) plate 711 has a large amount of level course parts that are made of underclad portion 712, intermediate layer part 713 and top section 714.In this example, underclad portion 712 is continuous, and intermediate layer and top section have opening respectively, have formed step-like opening 715 by above-mentioned opening, and step-like opening forms cavity part 716 with underclad portion 712.
The MCM sheet is a silicon MCM sheet 717 on the silicon that is made of silicon substrate 718 and silicon 719,720, and is arranged in cavity.Silicon substrate has the shape in the underclad portion surface upper plenum that puts it to the PW plate.Each lead connects and refers to that 721 are interconnected on the contact pad 723 on the intermediate layer part of PW plate by lead 722.
Each pad equally also is interconnected on another level course part partly of PW plate, for example pass through the contact 725 of through hole 724, thereby on the solder protuberance 726 of each interconnected to the underclad portion basal surface, and when needs, with its be interconnected to other chip or electronic device for example on the top section surface of PW plate by label 727 or 728 represented chip or devices.Here, be placed on the lip-deep MCM sheet of underclad portion and be arranged in cavity part 716 fully, the height of the top surface of the top section of the aspect ratio PW plate of the top surface of chip is low.
The potting material 729 that will have a height applicability for example silica gel is filled in the cavity part 716, and potting material 729 has sealed that interconnecting parts between chip and the silicon substrate, the lead on the silicon substrate connect and refer to, interconnecting parts and interconnecting lead on the PW plate between the contact pad connect the lead that refers to contact pad.
In addition, in device 710, be provided with as structure member 730 heat sink and the sealed cavity part.The end 731 of structure member (heat sink) is positioned on the top section of PW plate.Although the chip of heat sink position and MCM sheet has certain distance, its near MCM sheet make its can be fully in the device course of work by the heat of the composed component generation of MCM sheet.As selection, can provide be suitable for heat conduction parts 732 for example heat-conducting cream or hot grease so that contact with heat sink physics with chip.
Fig. 7 B has shown the second routine MCM encapsulation 770.This is an example with MCM sheet of following structure, and wherein the MCM sheet is interconnected to PW plate 771 by the solder reflow connection.This MCM encapsulation has the PW plate 771 that is formed by single-layer portions, and single-layer portions has logical opening 772.Position relation between PW plate 771 and the MCM sheet 717 is that the chip 719 and 720 of MCM sheet is arranged in opening 772, locate the end of the silicon substrate 718 of MCM sheet like this, make it overlapping, make the silicon substrate 718 of MCM sheet be positioned at the outside of opening with the bottom surface of the PW plate 771 of adjacent openings.
Each connection on the silicon substrate refers to that 773 all 774 are electrically connected by contacting on solder reflow interconnection and the PW plate.Cup-shaped cover 775 contacts with the basal surface of silicon substrate 718, and the flange 776 of cover is attached to the bottom of PW plate 771 by means of the adhesive (not shown).In order to use cup-shaped cover heat sink as the MCM sheet, for example copper or plastics with high-termal conductivity form the cup-shaped cover by metal.When using metal cap, it is that it can be as the shield of electromagnetic radiation that a benefit is arranged.
Cavity part 777 becomes by the wall part of opening 772 and cup-shaped are hood-shaped, the local potting material silica gel for example with applicability, the interconnecting parts between encapsulant 729 sealings and protection MCM sheet and connection refer to, and contact of filling.
As mentioned above, traditional MCM semiconductor device has following array structure, wherein a plurality of IC chips are installed on the silicon substrate as intermediate substrate, silicon substrate are installed on the PW plate, for example disclosed semiconductor device in the flat 8-250652 of Japanese Patent Application Publication No..The size of silicon substrate is compared with the size of IC chip and is become greatly in view of the above, but does not consider their size at that time.Yet, be attached in the whole lip-deep structure of PW plate at silicon substrate, as in the example shown in Fig. 7 A, a problem has appearred, and be exactly when the size of silicon substrate increases, because thermal stress causes silicon substrate to trend towards producing the crack.In addition, the wiring that interconnects the IC chip is formed on silicon substrate with being used for the outside wiring that connects.For surpassing for example silicon substrate size of 20mm * 20mm, owing to can not in single exposure is handled, form wiring figure, therefore at present restriction occurring aspect the improvement of connecting wiring figure, also having produced a problem is the realization that has limited more highdensity connecting wiring.
Now, by forming opening at the PW plate that is used for installing intermediate substrate, so that in opening, hold the IC chip that is installed on the intermediate substrate, only utilize the electrode part that is located at the intermediate substrate peripheral part that intermediate substrate is connected to the PW plate, as example at Fig. 7 B, in the disclosed semiconductor device of the flat 9-181256 of Japanese Patent Application Publication No., can alleviate because the cracking problem that thermal stress occurs in intermediate substrate.Yet, owing to be provided with big opening at the middle body of PW plate, therefore still the another one problem can appear, limited the quantity of the external connecting electrode of semiconductor device exactly, perhaps must strengthen the size of PW plate in order to ensure the electrode of specified quantity.
Summary of the invention
The purpose of this invention is to provide a kind of MCM semiconductor device that uses intermediate substrate, it has improved the connecting wiring on the intermediate substrate, even strengthen the size of IC chip and the quantity of the increase IC chip to semiconductor device to be installed, also alleviated the cracking problem that in intermediate substrate, occurs to a great extent.
Semiconductor device according to the invention comprises: substrate; First and second intermediate substrate, it is installed on the substrate and is separated from each other out; With a plurality of electronic components that are directly installed on the intermediate substrate, these a plurality of electronic components comprise one first semiconductor chip at least, be formed with a plurality of first pads on the first surface of this first semiconductor chip, its second surface is relative with first surface, first semiconductor chip is installed on first and second intermediate substrate as follows: the part of the second surface of first semiconductor chip is towards first intermediate substrate, another part of the second surface of first semiconductor chip is towards second intermediate substrate, wherein first intermediate substrate has a plurality of first pads, second intermediate substrate has a plurality of second pads, each first pad of first intermediate substrate links to each other with one the first relevant pad of first semiconductor chip by first wire, each second pad of second intermediate substrate links to each other with one the first relevant pad of first semiconductor chip by second wire, and wherein first intermediate substrate further comprises a plurality of the 3rd pads, each the 3rd pad and one first corresponding pad electrical connection, second intermediate substrate further comprises a plurality of the 4th pads, each the 4th pad and one second corresponding pad electrical connection, each third and fourth pad is outwards drawn by lead.
Description of drawings
By with reference to below in conjunction with accompanying drawing to the detailed description that the present invention did, above and other objects of the present invention, feature and advantage will become more clear, wherein:
Figure 1A-1B has shown that being used to describe first of semiconductor device according to the invention implements illustration, and wherein Figure 1A is a floor map, and Figure 1B is the cross-sectional schematic that the line X-X ' along Figure 1A obtains;
Fig. 2 A-2C is the master operation cross-sectional schematic of manufacture method that is used to describe the semiconductor device of first embodiment;
Fig. 3 A-3C has shown the figure that is used to describe second embodiment of the invention, and wherein Fig. 3 A is a floor map, and Fig. 3 B and Fig. 3 C are the cross-sectional schematic that obtains along the line Y-Y ' among Fig. 3 A;
Fig. 4 shows that the substrate of second embodiment connects the cross-sectional schematic of the object lesson of projection;
Fig. 5 A-5D has shown the figure of the 3rd embodiment that is used to describe semiconductor device of the present invention, wherein Fig. 5 A is a floor map, Fig. 5 B and 5C are the cross-sectional schematic that the line Z-Z ' along Fig. 5 A obtains, and Fig. 5 D has shown the cutaway view of structure example of the PWB of this embodiment;
Fig. 6 A and 6B are the floor map that is used to describe to the modification that each embodiment did of semiconductor device according to the invention;
Fig. 7 A and 7B are the cross-sectional schematic of the example of the expression semiconductor device that uses traditional MCM encapsulation;
Fig. 8 is the floor map that is used to describe the manufacture method of intermediate substrate.
Embodiment
The present invention is described below with reference to the accompanying drawings.
With reference to figure 1A-1B, for example, the semiconductor device of this embodiment comprises two intermediate substrate 10 and 20 at least, as 3 chips 40,50,52 and the printed substrate (hereinafter being also referred to as PWB) of electronic component.
The primary structure of each element is described at first, successively.IC chip 40 has and is used for the pad electrode (not shown) that is connected with the outside of the element that forms thereon in its face side, and for example, solder protuberance is formed on the electrode.IC chip 50 and 62 has the connection pads (not shown) of conduct at the external connecting electrode of the face side that is formed with element. Intermediate substrate 10 and 20 is all formed by the silicon substrate with square almost or rectangular profile, its size for example is the 20mm length of side or littler square, allows to carry out the batch exposure by common reduced projection aligner (reduction projectionaligner) (so-called stepping projection exposure machine).Intermediate substrate 10 has connection pads 11 and 13 and unshowned inner connecting wiring on a first type surface, intermediate substrate 20 has same connection pads 21 and 23 and unshowned inner connecting wiring.Here, connection pads 11 and 21 is appointed as first electrode, connection pads 13 and 23 is appointed as second electrode.PWB 60 has the internal connecting electrodes 61 that will be appointed as third electrode on external connecting electrode 63 on the first surface 60a and the second surface 60b, second surface 60b has formed with respect to the opposing face as positive first surface 60a, and corresponding mutually external connecting electrode 63 is connected by the wiring in the PWB (not shown) with internal connecting electrodes 61.In addition, for example solder ball 65 is formed on the external connecting electrode 63.
Below, with the connection of describing in these elements.For example by projection 45 pad electrode on the face side that is formed on chip 40 is connected on the corresponding projection connection pads 12 on the first type surface that is formed on substrate 10 by welding, IC chip 40 is faced down is connected to intermediate substrate 10. IC chip 50 and 52 is installed in the precalculated position, and they face up on intermediate substrate 10 and 20, and for example spun gold or aluminium wire are connected with the corresponding connection pads 11 that is pre-formed on substrate 10 and 20 each connection pads (not shown) with 21 with wire 71.To be installed in the intermediate substrate 10 and 20 that its back side has an adhesive on the particular location of second 60b of PWB 60, and utilize wire that each connection pads 13 and 23 is connected to corresponding internal connecting electrodes 61.Sealing resin 5 grades with epoxy type are sealed in last all electronic components installed of second surface 60b of PWB 60 and the electrode that forms on second surface 60b.
Then, will the manufacture method of the semiconductor device 1 of this embodiment be described briefly.Fig. 2 has shown the cross-sectional schematic of the master operation that is used to describe manufacture method.IC chip 40,50 and 52 can be made by known method, therefore will omit description of them.
With reference to figure 2A-2C, at first, on the whole surface of wafer 6, form the dielectric film (not shown), at its top, formed and comprised connection pads 11 and 13 and corresponding to the desirable connecting wiring 15 of the projection connection pads 12 of intermediate substrate 10 and comprise corresponding to the connection pads 21 of intermediate substrate 20 and 23 desirable connecting wiring, except the back will become the coupling part that is connected with other parts, be connection pads 11,13,21 and 23 and projection connection pads etc. whole surface cover (Fig. 2 A) with the dielectric film (not shown).Here, connecting wiring 15 and 25 comprise with connection pads 11 and 21 and projection connection pads 12 be connected to wiring on connection pads 13 and 23 and the connecting wiring between IC chip 40,50 and 52.In fact, connecting wiring 15 and 25 can utilize conductive metallic material for example aluminium (Al), copper (Cu) etc. accurately form in the mode the same with the wiring of general semiconductor chip.In addition, can make intermediate substrate 10 and 20 by for example on wafer shown in Figure 86, substrate 10 and 20 being combined as cell block 30 with the form of matrix.Then, wafer 6 is cut into the sheet of piece 30, is cut into intermediate substrate sheet 10 and 20 respectively every.Then, be connected to precalculated position on the face 60b, intermediate substrate 10 and 20 be installed on the second surface 60b of previously prepared PWB 60 by the back side with intermediate substrate 10 and 20.Then, IC chip 40 is installed in the precalculated position of intermediate substrate 10.More particularly, by projection 45, make at set pad electrode on IC chip 40 surfaces to be connected on the projection connection pads 12 corresponding on the first type surface that is pre-formed in intermediate substrate 10, be installed on the intermediate substrate 10 thereby IC chip 40 faced down with pad electrode.By this way, IC chip 40 is connected on the intermediate substrate 10, finishes simultaneously to be electrically connected and mechanical connection.Then, IC chip 50 and 52 faced up is installed in the precalculated position, makes it on intermediate substrate 10 and 20.Utilize soft adhesive 8 realize IC chips 50 and 52 with intermediate substrate 10 and 20 between be connected.Then, by wire 71 with unshowned IC chip 50 and 52 connection pads with in advance on intermediate substrate 10 and 20 the corresponding connection pads 11 of preparation be connected with 21.Then, utilize wire 73 with intermediate substrate 10 and 20 connection pads 13 with 23 with after the corresponding internal connecting electrodes 61 of PWB 60 is connected, for example epoxy resin 5 sealings of resin of the element one of whole second surface 60b and installation being reinstated regulation.Then, utilize for example solder ball 65 connection external connecting electrodes 63, finished semiconductor device 1.
In the superincumbent description, it is flat that the wafer 6 that is used to make intermediate substrate 10 and 20 only needs.For example, this wafer can be that its electrical property departs from the wafer that standard consequently can not be used for making the product that element is housed.Therefore, it is not too large to make the expense of these substrates.In addition, in the present embodiment, provided intermediate substrate 10 and 20 examples of making by a wafer simultaneously, but their also wafer manufacturings from separating respectively.
As mentioned above, the semiconductor device 1 of this embodiment uses a plurality of intermediate substrate that formed by silicon substrate, make the square of the size of an intermediate substrate less than length of side 20mm, the foursquare size of this length of side 20mm is normally to use the reduced projection aligner to carry out the size of exposure in batches.Therefore can easily form the wiring of the fine linewidth of little about 0.2 μ m of arriving.In view of the above, can obtain making the high effect of connecting wiring density of intermediate substrate, and make this installation realize high density as flip-over type IC chip.In addition, by the predetermined electronic component installed on different intermediate substrate, can so that signal between a plurality of intermediate substrate, transmit.In addition, the size by making intermediate substrate is less than the square of length of side 20mm, the cracking problem that can occur owing to thermal coefficient of expansion is different with the thermal coefficient of expansion of PWB hardly in intermediate substrate.In addition, by using silicon substrate as intermediate substrate, make the thermal coefficient of expansion of intermediate substrate equal the thermal coefficient of expansion of IC chip, even make in the installation of flip-over type, injecting between intermediate substrate and the IC chip under the discontented situation, it also can obtain sufficient resisting temperature cyclicity, reduces manufacturing expense.In addition, PWB only needs to connect the internal connecting electrodes and the external connecting electrode of mutual correspondence, therefore the effect of bringing the PWB manufacturing expense to reduce.
Below, the semiconductor device 2 of the second embodiment of the present invention will be described with reference to figure 3A-3C.With reference to figure 3A and 3B, the semiconductor device 2 of this embodiment comprises intermediate substrate 80, three IC chips 40,50 and 52 and PWB 60 at least.Below, the composed component identical with first embodiment provided identical reference number, and the descriptions thereof are omitted.
The intermediate substrate 80 that is included in the semiconductor device 2 is formed by silicon substrate, has the profile of square almost or rectangle.On an interarea of intermediate substrate 80, dispose connection pads 81, projection connection pads 82, middle connection pads 84 and unshowned inner connecting wiring.In this embodiment, connection pads 81 and projection connection pads 82 are appointed as first electrode, the middle connection pads 84 that is located in the fringe region is appointed as second electrode.For example pass through projection 45 by welding, make on the first type surface that is located at IC chip 40 lip-deep pad electrodes and intermediate substrate 80 to be connected, be connected on the intermediate substrate 80 thereby IC chip 40 faced down corresponding to the formed projection connection electrode 82 of these pad electrodes.In addition, IC chip 50 and 52 is installed on the particular location of intermediate substrate 80, their each connection pads (not shown) connects with corresponding connection pads 81 on being located at intermediate substrate 80 by means of wire 71.
In this embodiment, first type surface of intermediate substrate 80 that all three electronic components 40,50 and 52 are installed and the second surface 60b of PWB 60 are faced with each other, utilize substrate to connect projection 90 and corresponding mutually a middle connection pads 84 and an internal connecting electrodes 61 are coupled together by connecting.In this case, set the distance h 1 between second 60b of first type surface of intermediate substrate 80 and PWB 60, make the IC chip 40,50 that is installed on the intermediate substrate 80 not contact second 60b of PWB 60 with wire 71 with 52.More particularly, for example, set t1 and t2, it is satisfied concern h1＞(t1+t2).As shown in Figure 4, on each internal connecting electrodes 61 of PWB, formed projection, this projection has as the small cylindrical metal 91 of the high t1 of core and lip-deep solder coat 67, forming projection on the connection pads 84 in the middle of each, this projection has as the minute metallic post 93 of the high t2 of core and lip-deep solder coat 87.Then, by also heating on the assigned position that intermediate substrate 80 is placed on PWB 60, scolder 67 and 87 fusions become the scolder 97 around cylindrical metal 91 and 93, form the substrate of guaranteeing predetermined altitude and connect projection 90, and intermediate substrate 80 is installed on the PWB 60.After intermediate substrate 80 is installed on the PWB 60, resin 5 is injected into gap between intermediate substrate 80 and the PWB 60.
In the semiconductor device 2 of this embodiment, because intermediate substrate 80 is connected projection 90 with 60 of PWB by means of substrate and connects, even when the size of middle substrate 80 increases, also can alleviate in intermediate substrate 80 owing to the different crackings that cause of the thermal coefficient of expansion between intermediate substrate 80 and the PWB 60.In addition, when the size of middle substrate 80 surpasses the 20mm length of side square, the connecting wiring density of this intermediate substrate 80 is lower than the connecting wiring density of substrate of the centre of first embodiment slightly, but it benefit is arranged is to simplify being connected of intermediate substrate and PWB.
In addition, in this embodiment, the middle body at PWB 60 is not provided with external connecting electrode if can guarantee external connecting electrode 63 required quantity, by middle body the opening 68 of appropriate size is set at the PWB shown in Fig. 3 C, can so that resin 5 be injected in the gap between intermediate substrate 80 and the PWB 60.
The 3rd embodiment of semiconductor device according to the invention will be described below.Fig. 5 A-5D has described the semiconductor device 3 of this embodiment, and with reference to figure 5A and 5B, this device for example comprises intermediate substrate 80, three IC chips 40,50 and 52 and PWB 62 at least.Below, the composed component identical with first embodiment provided identical reference number, and the descriptions thereof are omitted.
In the semiconductor device 3 of this embodiment, similar with second embodiment, first type surface of intermediate substrate 80 and second 62b of PWB 62 face, and corresponding a middle connection pads 84 and an inner connection pads 61 are coupled together by welding by means of projection 95 grades of solder ball.Yet the remarkable difference that is included in the PWB 60 of the PWB 62 in the semiconductor device 3 of this embodiment and second embodiment is: be provided with recess 100 on second 62b side.Recess 100 does not comprise the zone that has formed internal connecting electrodes, comprises at least in the face of being installed in IC chip 40,50 on the intermediate substrate 80 and 52 zone, and the recess of formation makes and the part of IC chip 40,50 and 52 can be pushed in the recess 100.As a result, it is low to make the substrate of aspect ratio second embodiment of projection 95 connect the height of projection 90, therefore can make under the situation of semiconductor device than second embodiment thin.In addition, recess 100 does not penetrate PWB 62, owing to can on first 62a side of recess 100 external connecting electrode 63 be set, need not reduce the quantity of external connecting electrode or the size of increase PWB 62 in order to ensure the number of electrodes of hope.The situation of all the other structures and second embodiment is similar, has therefore omitted description of them.In addition, the same as the modification of this embodiment with second embodiment, by middle body through hole 68 is set at PWB 62, be convenient to the injection of resin 5, shown in Fig. 5 C.In addition, by in conjunction with PWB621 and PWB 622,, can easily form the recess 100 of PWB 62, shown in Fig. 5 D with the part of recess corresponding to opening.
As mentioned above, in the first embodiment of the present invention, in constituting the MCM semiconductor device, use size less than foursquare a plurality of silicon substrates of the 20mm length of side as intermediate substrate, be used for directly installing a plurality of electronic components that comprise the IC chip.As a result, can easily form the forming fine wiring of about 0.2 μ m live width on each intermediate substrate, in view of the above, the high-density installation of the high-density wiring between the electronic component and a large amount of electronic components becomes possibility.In addition, even when utilizing adhesive that its back side is connected on the PWB, thereby intermediate substrate is installed on the PWB, similar with the normal assembling of IC chip, owing to make the size of intermediate substrate littler, will can not occur owing to the different problems of crack that cause of thermal coefficient of expansion between PWB and the intermediate substrate than the foursquare size of the 20mm length of side.
In addition, in the of the present invention second and the 3rd embodiment, first type surface of intermediate substrate of all a plurality of electronic components and second face of PWB have been installed on it have been faced with each other, by coupling together, and further resin has been injected in the gap between intermediate substrate and the PWB with solder protuberance etc.In view of the above, even the size of intermediate substrate surpasses the square of the 22mm length of side, also can alleviate between intermediate substrate and the PWB owing to the different problems of crack that cause of thermal coefficient of expansion.In addition, in the 3rd embodiment, be provided with recess, and can under the situation of the external dimensions that does not influence the external connecting electrode quantity that is formed on first or PWB, make the semiconductor device attenuate at second face of PWB.
In addition, the present invention is not limited to given in conjunction with the embodiments description, can be used as various modifications in its theory scope.For example, the present invention has been described with reference to the drawings, wherein the internal connecting electrodes of PWB is a third electrode, connection pads of intermediate substrate (first embodiment) or middle connection pads (the second and the 3rd embodiment) are second electrode, above-mentioned arrangement of electrodes are become a line on each side zones of two opposite sides.Then, if desired, also they can be arranged on all four sides, as shown in Figure 6A, perhaps they be arranged to many lines rather than a line, although formally do not illustrate.In addition, utilize example to describe the present invention, the electronic component that wherein is included in the semiconductor device only has the IC chip.Yet semiconductor can comprise other element, for example resistor, capacitor and connector.In addition, resistor and capacitor can be combined on the intermediate substrate with connecting wiring.In addition, in a second embodiment, not only can substrate be set and connect projection, and can connect inner projection 98, shown in Fig. 6 B in interior zone setting such as substrate in edge area.In this way, the third electrode of the connection PWB among all right partial simplified PWB and the wiring of external connecting electrode.
As mentioned above, according to the present invention, can obtain following effect: realize the MCM semiconductor device easily and cheaply, this MCM semiconductor device can need not be considered the difference of thermal coefficient of expansion in the employed parts with a large amount of electronic component that comprises the IC chip of high-density installation.In addition, can obtain making the thin effect of MCM semiconductor device.
Although described the present invention with reference to specific embodiment, this description does not also mean that restriction the present invention.With reference to description of the invention, those skilled in the art are conspicuous to the various modifications of disclosed embodiment.Therefore, claims should cover any modification or the embodiment that falls in the essential scope of the present invention.

Claims (12)

1. semiconductor device comprises:
Substrate;
First and second intermediate substrate, it is installed on the described substrate and is separated from each other out; With
Be directly installed on a plurality of electronic components on the described intermediate substrate; Described a plurality of electronic component comprises one first semiconductor chip at least; Be formed with a plurality of first pads on the first surface of described first semiconductor chip; Its second surface is relative with described first surface; Described first semiconductor chip is installed on described first and second intermediate substrate as follows: the part of the described second surface of described first semiconductor chip is towards described first intermediate substrate; Another part of the described second surface of described first semiconductor chip is towards described second intermediate substrate
Wherein said first intermediate substrate has a plurality of first pads, described second intermediate substrate has a plurality of second pads, described first pad of each of described first intermediate substrate links to each other with relevant described first pad of described first semiconductor chip by first wire, described second pad of each of described second intermediate substrate links to each other with relevant described first pad of described first semiconductor chip by second wire, and
Wherein said first intermediate substrate further comprises a plurality of the 3rd pads, each described the 3rd pad and corresponding described first pad electrical connection, described second intermediate substrate further comprises a plurality of the 4th pads, each described the 4th pad and corresponding described second pad electrical connection, each described third and fourth pad is outwards drawn by lead.
2. semiconductor device as claimed in claim 1, wherein said lead are connected with described substrate and form electric channel between described substrate and each described third and fourth pad.
3. semiconductor device as claimed in claim 1, wherein each described first and second intermediate substrate forms rectangular shape, and the length on arbitrary limit of this rectangular shape is all less than 20mm.
4. semiconductor device as claimed in claim 1, wherein said first and second intermediate substrate are made by silicon substrate.
5. semiconductor device as claimed in claim 4, wherein said silicon substrate comprises the electronic component that is formed at wherein.
6. semiconductor device as claimed in claim 5, wherein said electronic component comprise one of capacitor and resistor at least.
7. semiconductor device as claimed in claim 1, wherein said a plurality of electronic component also comprises one second semiconductor chip, described second semiconductor chip have the 3rd surface that is formed with a plurality of second pads on it with relative the 4th surface, described the 3rd surface, described second semiconductor chip is installed on described first and second intermediate substrate as follows: the part on described the 4th surface is towards described first intermediate substrate, and the another part on described the 4th surface is towards described second intermediate substrate.
8. semiconductor device as claimed in claim 7, wherein said first intermediate substrate also comprises a plurality of the 5th pads, described second intermediate substrate also comprises a plurality of the 6th pads, described the 5th pad of each of described first intermediate substrate links to each other with relevant described second pad of described second semiconductor chip by the 3rd wire, and described the 6th pad of each of described second intermediate substrate links to each other with relevant described second pad of described second semiconductor chip by the 4th wire.
9. semiconductor device as claimed in claim 8, described the 3rd pad of each of wherein said first intermediate substrate also is electrically connected with one of corresponding described the 5th pad, and described the 4th pad of each of described second intermediate substrate also is electrically connected with one of corresponding described the 6th pad.
10. semiconductor device as claimed in claim 9, wherein said lead are connected with described substrate and form electric channel between described substrate and each described first and second intermediate substrate.
11. semiconductor device as claimed in claim 7, wherein each described first and second intermediate substrate forms rectangular shape, and the length on arbitrary limit of described rectangular shape is all less than 20mm.
12. semiconductor device as claimed in claim 7, wherein each described first and second intermediate substrate is made by the silicon substrate that wherein is formed with electronic component, and described electronic component comprises one of capacitor and resistor at least.
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US6984889B2 (en) 2006-01-10

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