CN221447179U - Shielded gate trench VDMOS device - Google Patents
Shielded gate trench VDMOS device Download PDFInfo
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- CN221447179U CN221447179U CN202322399138.0U CN202322399138U CN221447179U CN 221447179 U CN221447179 U CN 221447179U CN 202322399138 U CN202322399138 U CN 202322399138U CN 221447179 U CN221447179 U CN 221447179U
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- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 description 20
- 230000015556 catabolic process Effects 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000002902 bimodal effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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Abstract
The utility model provides a shielded gate trench VDMOS device, comprising: a substrate, an intermediate layer, a semi-insulating layer and a gate layer; the intermediate layer is arranged on the upper side of the substrate and comprises a drift layer and a source electrode layer; the drift layer is arranged on the substrate, and a source layer is arranged on the upper side of the drift layer; wherein at least one trench is formed in the intermediate layer; the semi-insulating layer is arranged in the groove, is in contact with the drift layer and has resistivity; and the grid electrode layer is arranged in the groove, is close to the source electrode layer and is contacted with the upper surface of the semi-insulating layer. The utility model improves the pressure endurance capacity of the device by improving the structure in the groove.
Description
Technical Field
The utility model relates to the technical field of Semiconductor devices, in particular to a Vertical Double-diffused metal Oxide Semiconductor field effect transistor (VDMOS) device with a shielded gate trench.
Background
In the modern electronics field, with the increasing demand for energy and the diversified application of electronic devices, the development of power semiconductor devices has become more critical. These devices play an important role in the fields of energy conversion, motor driving, power management, and the like. However, high voltage, high power applications place more stringent demands on semiconductor devices, and conventional design and fabrication techniques increasingly exhibit their limitations. Under the background, the design of novel power devices such as a shielded gate trench VDMOS (Vertical Double-DiffusedMetal-Oxide-Semiconductor) and the like is continuously emerging, so that the limitations of the traditional devices are overcome, and a more efficient and reliable solution is provided.
The shielded gate trench VDMOS is a novel power mosfet (Metal-Oxide-Semiconductor Field-effect transistor), and compared with the conventional VDMOS structure, the split gate VDMOS is improved in gate design, and a split structure is adopted on the gate, and the split structure is respectively connected with the shielded gate and the control gate of the source, wherein the shielded gate divides the control gate from the drain, and the split structure can reduce the coupling between the gate-source capacitance and the gate-drain capacitance, so that the power consumption and noise in the switching process are reduced. The shielded gate trench VDMOS meets the requirements of high voltage and high power, and brings new development opportunities for the power electronics field through an innovative structure and a manufacturing method, and the wide application prospect in the fields of energy conversion, electric driving and the like is worthy of expectations.
However, the shielded gate trench VDMOS has a lower on-resistance than the conventional trench VDMOS due to its longitudinal electric field modulation effect. When the common trench VDMOS breaks down reversely, the longitudinal electric field is maximum at the PN junction; when the shielded gate trench VDMOS device breaks down, the longitudinal electric field has two peaks, one is at the PN junction and the other is at the bottom of the trench, and the electric field distribution can greatly improve the withstand voltage of the device, thereby reducing the on-resistance of the device.
The bimodal electric field phenomenon causes breakdown voltage creep when the shielded gate trench VDMOS breaks down reversely, namely the breakdown voltage of the device gradually decreases with the increase of time when the device breaks down reversely. The reason is that the electric field at the bottom of the groove is overlarge, because of the strong electric field at the bottom of the groove, hot holes acquire enough energy, the hot holes enter the oxide layer beyond the potential barrier, trap charges in the oxide layer are relatively large, the hot holes are fixed, similar to positive fixed charges exist on the surface of the oxide layer, the electric field of bulk silicon in the groove is changed, the shielding effect of the groove is weakened, the bulk silicon cannot be completely consumed, the maximum electric field value is transferred to the PN junction, and the breakdown voltage of the device is reduced.
Disclosure of utility model
The utility model aims at solving the technical problems, and improves the pressure endurance capacity of the device; in view of this, the present utility model provides a shielded gate trench VDMOS device.
The technical scheme adopted by the utility model is that the shielded gate trench VDMOS device comprises:
A substrate;
An intermediate layer disposed on an upper side of the substrate, including a drift layer and a source layer; the drift layer is arranged on the substrate, and a source layer is arranged on the upper side of the drift layer; wherein at least one trench is formed in the intermediate layer;
a semi-insulating layer which is arranged in the groove, is contacted with the drift layer and has resistivity;
and the grid electrode layer is arranged in the groove, is close to the source electrode layer and is contacted with the upper surface of the semi-insulating layer.
In one embodiment, the semi-insulating layer is a polysilicon layer and has a resistivity of 10 12-1017 Ω·cm using an LPCVD (lpcvd— Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) process.
In one embodiment, the semi-insulating layer is between 0.1 and 0.5um thick.
In one embodiment, the semi-insulating layer is disposed at the bottom of the trench; or at the bottom and on both sides of the trench.
In one embodiment, the source layer includes:
a first source layer and a second source layer forming a source of the device, wherein a side close to the drift layer is the first source layer; surfaces of the first source layer and the second source layer are connected to each other.
In one embodiment, the device further comprises:
and the filling isolation layer is arranged on the inner side of the semi-insulating layer.
In one embodiment, the material of the filling isolation layer comprises silicon dioxide and silicon nitride.
In one embodiment, a thin gate oxide layer is further disposed between the source layer and the gate layer.
In one embodiment, the substrate, the drift layer, the second source layer are N-type, and the first source layer is P-type; or the substrate, the drift layer and the second source electrode layer are of a P type, and the first source electrode layer is of an N type.
Compared with the prior art, the utility model has at least the following advantages:
The shielded gate trench VDMOS device provided by the utility model can achieve the purpose of improving the withstand voltage of the device, and particularly, when the device is in a reverse blocking state: the drain electrode has high potential, the grid electrode and the source electrode have zero potential, the upper part of the semi-insulating layer is connected with the grid electrode, the bottom of the semi-insulating layer is connected with the drift region, the longitudinal potential of the resistor is uniformly distributed, meanwhile, as the side surface of the high-resistance semi-insulating layer is connected with the drift region, the uniformly distributed longitudinal resistor potential has a certain modulation effect on the electric field of the drift region in the groove, compared with the traditional shielded grid groove modulation, the shielded grid groove modulation device has more uniform modulation and higher withstand voltage, and the purpose of likewise improving the withstand voltage of the device can be achieved.
In addition, due to the existence of the semi-insulating layer, when the device is in reverse breakdown, hot holes generated by the bottom peak electric field enter the semi-insulating layer, and the hot holes are not bound in a fixed area like a traditional structure, but move from a high-voltage area to a low-voltage area in the resistor, and are finally neutralized by electrons in the resistor, so that the effect of influencing the electric field of a drift area in a groove is lost, and the breakdown voltage creep phenomenon can be effectively avoided.
Drawings
Fig. 1 is a schematic diagram of a conventional shielded gate trench VDMOS device;
fig. 2 is a schematic diagram of a principle of breakdown hot holes entering an oxide layer of a conventional shielded gate trench VDMOS device;
fig. 3 is a schematic structural diagram of a shielded gate trench VDMOS device according to an embodiment of the present utility model;
Fig. 4 is a schematic diagram of a circuit model of a proposed novel shielded gate trench VDMOS device according to an embodiment of the present utility model;
Fig. 5 is a schematic structural diagram of a shielded gate trench VDMOS device according to another embodiment of the present utility model.
Reference numerals
101-A substrate, 102-a drift layer, 103-a first source layer, 104-a second source layer, 201-a thick field oxide layer, 202-an isolation oxide layer, 203-a thin gate oxide layer, 204-a filling isolation layer; 301-polysilicon shield gate, 302-gate layer, 401-semi-insulating layer.
Detailed Description
In order to further describe the technical means and effects adopted by the present utility model for achieving the intended purpose, the following detailed description of the present utility model is given with reference to the accompanying drawings and preferred embodiments.
In the drawings, the thickness, size and shape of the object have been slightly exaggerated for convenience of explanation. The figures are merely examples and are not drawn to scale.
It will be further understood that the terms "comprises," "comprising," "includes," "including," "having," "containing," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features that are listed, the entire listed feature is modified instead of modifying a separate element in the list. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
As used herein, the terms "substantially," "about," and the like are used as terms of a table approximation, not as terms of a table level, and are intended to illustrate inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
For ease of understanding, the prior art is briefly described below.
As shown in fig. 1, a conventional shielded gate trench VDMOS is shown in a cellular structure, where a substrate 101 is specifically a highly doped N-type substrate layer, a bottom portion is used as a drain electrode of a device, a drift layer 102 is specifically a low doped epitaxial layer, this portion is used to bear a reverse withstand voltage of the device, a first source layer 103 is specifically a P-type doped region, and a second source layer 104 is specifically an n+ source heavily doped layer, where the first source layer 103 is connected to a surface of the second source layer 104, so as to form a source electrode of the device. The trench is filled with a thick field oxide layer 201, an isolation oxide layer 202 is arranged between the trench gate and the shielding gate, and a thin gate oxide layer 203 is arranged between the source electrode layer and the gate electrode layer 302. The polysilicon shielding gate 301 is connected to the source electrode, and the gate electrode layer 302 is specifically a device polysilicon gate electrode, and controls the on and off of the device.
When the conventional shielded gate device is in a reverse breakdown state, the longitudinal electric field has two peaks, one is the junction between the P-type region of the first source layer 103 and the N-type region of the drift layer 102, and the other is the junction between the bottom of the thick field oxide layer 201 and the drift layer 102, and both the two positions have higher impact ionization rate due to the action of the strong electric field. Hole electrons generated by collision ionization at the PN junction are rapidly extracted by the P region of the first source layer 103 and the N-type region of the drift layer 102 respectively, and finally the electrode positions are combined; and holes generated by collision at the bottom of the trench enter the thick field oxide layer 201 under the action of a strong electric field.
As shown in fig. 2, these free hot holes are easily fixed and bound by the trapped charges in the oxide layer, and are difficult to move again, and these positive charges cause the electric field distribution in the trench to change, so that the shielding effect of the device is weakened, the surface electric field is enhanced, and the voltage of the device is reduced, which is a breakdown creep phenomenon, that is, the breakdown voltage of the device gradually decreases with the increase of the breakdown time.
To address the above phenomena, an embodiment of the present utility model provides a shielded gate trench VDMOS device, as shown in fig. 3, including:
A substrate 101;
an intermediate layer disposed on the upper side of the substrate 101, including a drift layer 102 and a source layer; the drift layer 102 is arranged on the substrate 101, and a source layer is arranged on the upper side of the drift layer 102; wherein at least one trench is formed in the intermediate layer;
A semi-insulating layer 401 provided inside the trench, in contact with the drift layer 102, and having a resistivity;
The gate layer 302 is disposed in the trench, adjacent to the source layer, and in contact with the upper surface of the semi-insulating layer 401.
The device provided by the present utility model will be described in detail below with reference to fig. 3.
In this embodiment, the bottom of the substrate 101 serves as the device drain.
In this embodiment, the semi-insulating layer 401 is a polysilicon layer, and has a resistivity of 10 12-1017 Ω·cm by an LPCVD (lpcvd— LowPressure Chemical Vapor Deposition, low pressure chemical vapor deposition) process.
In this embodiment, the semi-insulating layer 401 has a thickness of between 0.1 um and 0.5 um.
In this embodiment, the source layer specifically includes: a first source layer 103 and a second source layer 104 which constitute a device source, wherein the first source layer 103 is located on a side close to the drift layer 102; the surfaces of the first source layer 103 and the second source layer 104 are connected to each other.
In this embodiment, the device further includes: the filling isolation layer 204 is provided inside the semi-insulating layer 401.
In this embodiment, the material of the filling isolation layer 204 includes silicon dioxide and silicon nitride.
In this embodiment, a thin gate oxide layer 203 is further disposed between the source layer and the gate layer 302.
In this embodiment, the substrate 101, the drift layer 102, and the second source layer 104 are N-type, and the first source layer 103 is P-type; or the substrate 101, the drift layer 102, and the second source layer are P-type 104, and the first source layer 103 is N-type.
In this embodiment, referring again to fig. 3, compared with the conventional shielded gate structure, the trench is mainly filled with a changed material, specifically, the semi-insulating layer 401 is a SIPOS semi-insulating polysilicon layer, which has a higher resistivity, the resistivity is 10 12-1017 Ω·cm, and a filling isolation layer 204 is provided, wherein the semi-insulating layer 401 is in contact with the gate layer 302 of the device.
The schematic diagram of this embodiment is shown in fig. 4, which is equivalent to adding a large resistor R between the gate and the drain, as a discharging path of the hot carrier at the bottom of the trench, where the resistor R is determined by the resistivity of the semi-insulating layer 401, and the resistance is between 10 9-1012 Ω.
In one possible embodiment, as shown in fig. 5, a semi-insulating layer 401 may be disposed at the bottom of the trench; or may be U-shaped, disposed at the bottom and on both sides of the trench.
The shielded gate trench VDMOS device provided by the utility model can also achieve the purpose of improving the withstand voltage of the device, and when the device is in a reverse blocking state: the high potential of the drain electrode, zero potential of the grid electrode and the source electrode, the upper part of the semi-insulating layer 401 is connected with the grid electrode layer 302, the bottom is connected with the drift region 102, the longitudinal potential of the resistor is uniformly distributed, meanwhile, as the side surface of the high-resistance semi-insulating layer 401 is connected with the drift region 102, the uniformly distributed longitudinal resistor potential has a certain modulation effect on the electric field of the N-type drift region of the drift region 102 in the groove, compared with the traditional shielded grid groove modulation, the device is more uniform in modulation and higher in withstand voltage, and the purpose of improving the withstand voltage of the device can be achieved.
In addition, due to the semi-insulating layer 401, when the device is in reverse breakdown, hot holes generated by the bottom peak electric field enter the semi-insulating layer 401, and the hot holes are not bound in a fixed area like a traditional structure, but move from a high-voltage area to a low-voltage area in the resistor, and are finally neutralized by electrons in the resistor, so that the effect of influencing the electric field of the drift region 102 in the trench is lost, and the breakdown voltage creep phenomenon can be effectively avoided.
While the utility model has been described in connection with specific embodiments thereof, it is to be understood that these drawings are included in the spirit and scope of the utility model, it is not to be limited thereto.
Claims (8)
1. A shielded gate trench VDMOS device comprising:
A substrate;
An intermediate layer disposed on an upper side of the substrate, including a drift layer and a source layer; the drift layer is arranged on the substrate, and a source layer is arranged on the upper side of the drift layer; wherein at least one trench is formed in the intermediate layer;
a semi-insulating layer which is arranged in the groove, is contacted with the drift layer and has resistivity;
and the grid electrode layer is arranged in the groove, is close to the source electrode layer and is contacted with the upper surface of the semi-insulating layer.
2. The shielded gate trench VDMOS device of claim 1 wherein the semi-insulating layer is a polysilicon layer having a resistivity of 10 12-1017 Ω cm using an LPCVD process.
3. The shielded gate trench VDMOS device of claim 1 wherein the semi-insulating layer is between 0.1-0.5um thick.
4. The shielded gate trench VDMOS device of claim 1 wherein the semi-insulating layer is disposed at the bottom of the trench; or at the bottom and on both sides of the trench.
5. The shielded gate trench VDMOS device of claim 1, wherein the source layer comprises:
A first source layer and a second source layer forming a source of the device, wherein a side close to the drift layer is the first source layer; surfaces of the first source layer and the second source layer are connected to each other.
6. The shielded gate trench VDMOS device of claim 1, further comprising:
and the filling isolation layer is arranged on the inner side of the semi-insulating layer.
7. The shielded gate trench VDMOS device of claim 1 wherein a thin gate oxide layer is further provided between the source layer and the gate layer.
8. The shielded gate trench VDMOS device of claim 5 wherein the substrate, the drift layer, the second source layer are N-type, and the first source layer is P-type; or the substrate, the drift layer and the second source electrode layer are of a P type, and the first source electrode layer is of an N type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322399138.0U CN221447179U (en) | 2023-09-05 | 2023-09-05 | Shielded gate trench VDMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322399138.0U CN221447179U (en) | 2023-09-05 | 2023-09-05 | Shielded gate trench VDMOS device |
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| Publication Number | Publication Date |
|---|---|
| CN221447179U true CN221447179U (en) | 2024-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322399138.0U Active CN221447179U (en) | 2023-09-05 | 2023-09-05 | Shielded gate trench VDMOS device |
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| Country | Link |
|---|---|
| CN (1) | CN221447179U (en) |
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2023
- 2023-09-05 CN CN202322399138.0U patent/CN221447179U/en active Active
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