CN221379342U - High-voltage isolation packaging structure - Google Patents
High-voltage isolation packaging structure Download PDFInfo
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- CN221379342U CN221379342U CN202323036871.2U CN202323036871U CN221379342U CN 221379342 U CN221379342 U CN 221379342U CN 202323036871 U CN202323036871 U CN 202323036871U CN 221379342 U CN221379342 U CN 221379342U
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- 238000002955 isolation Methods 0.000 title claims abstract description 13
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000012212 insulator Substances 0.000 claims description 23
- 239000004033 plastic Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 239000003292 glue Substances 0.000 description 7
- 239000011230 binding agent Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000945 filler Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
技术领域Technical Field
本实用新型涉及领域,尤其涉及一种高压隔离封装结构。The utility model relates to a field, in particular to a high-voltage isolation packaging structure.
背景技术Background technique
电子元器件的小型化、集成化是大势所趋,因此应用中经常出现不同要求的芯片合封于同一封装体中,特别的,对于多芯片间电压差较大时,存在高压击穿等风险,产品存在重大安全隐患。The miniaturization and integration of electronic components is an irresistible trend. Therefore, chips with different requirements are often sealed in the same package in applications. In particular, when the voltage difference between multiple chips is large, there is a risk of high-voltage breakdown, which poses a major safety hazard to the product.
常规同一基岛上作业,同时存在高压芯片和低压芯片时,低压芯片使用绝缘胶固晶,高压芯片使用导电胶固晶,由于点胶方式的低成本高效率且切换方便的优势,装片固晶基本采用点胶方式作业,然而通过固晶方式作业的结合材厚度一般取决于结合材本身的特性,特别是绝缘结合材的厚度和其填充物相关,有填充物的厚度可以到10um~15um左右,无填充物的厚度一般在5~10um,绝缘特性和绝缘层厚度直接相关,这样的厚度无法满足耐高压的需求。Conventionally, when high-voltage chips and low-voltage chips exist on the same substrate at the same time, insulating glue is used to bond the low-voltage chips, and conductive glue is used to bond the high-voltage chips. Due to the advantages of low cost, high efficiency and convenient switching of the dispensing method, the chip bonding is basically carried out by dispensing. However, the thickness of the bonding material operated by the bonding method generally depends on the characteristics of the bonding material itself, especially the thickness of the insulating bonding material is related to its filler. The thickness with filler can be about 10um to 15um, and the thickness without filler is generally 5 to 10um. The insulation characteristics are directly related to the thickness of the insulation layer. Such a thickness cannot meet the requirements of high voltage resistance.
实用新型内容Utility Model Content
本实用新型的目的是为了解决现有技术中存在的缺点,而提出的一种高压隔离封装结构。The utility model aims to solve the shortcomings in the prior art and proposes a high-voltage isolation packaging structure.
为了实现上述目的,本实用新型采用了如下技术方案:一种高压隔离封装结构,包括第一基岛和第二基岛,所述第一基岛的上端固定连接有结合材二,所述结合材二上端设置有隔离物一,所述隔离物一上端设置有结合材三,所述结合材三上端设置有隔离物二,所述隔离物二上端设置有低压芯片。In order to achieve the above-mentioned purpose, the utility model adopts the following technical scheme: a high-voltage isolation packaging structure, including a first base island and a second base island, the upper end of the first base island is fixedly connected with a binding material 2, the upper end of the binding material 2 is provided with an insulator 1, the upper end of the insulator 1 is provided with a binding material 3, the upper end of the binding material 3 is provided with an insulator 2, and the upper end of the insulator 2 is provided with a low-voltage chip.
作为上述技术方案的进一步描述:As a further description of the above technical solution:
所述第一基岛的上端固定连接有结合材一,所述结合材一的上端固定连接有高压芯片,且高压芯片、低压芯片第二基岛之间均设置有引线,所述第一基岛上设置有塑封体。The upper end of the first base island is fixedly connected with a bonding material 1, the upper end of the bonding material 1 is fixedly connected with a high-voltage chip, and leads are arranged between the high-voltage chip and the low-voltage chip and the second base island, and a plastic package is arranged on the first base island.
本实用新型具有如下有益效果:The utility model has the following beneficial effects:
此实施例列举方案主要为增加隔离物一和隔离物二同时采用结合材二和结合材三来直接增加绝缘层厚度,直接提升绝缘能力,满足高压隔离需求,其中隔离物一和隔离物二的选择可以选择线膨胀系数与芯片相近的绝缘材料,如二氧化硅等,其厚度可以通过研磨工艺实现,加工简单成本较低且易于实现,结合材二、结合材三均可以使用常见的点胶工艺实现,操作简便,结合材三可以在低压芯片晶圆划片前进行绝缘膜贴附或者绝缘胶涂覆工艺实现,作业简单易实现,结构简单,工艺上易于实现;耐压能力大幅提升,能满足高压隔离需求;由于多层结合材和隔离物的添加,对应相邻芯片的爬电距离也大幅增加;所有多芯片封装或叠层封装产品上均可以使用此结构原理来满足耐压需求。The scheme listed in this embodiment mainly increases the thickness of the insulating layer by adding insulator 1 and insulator 2 and simultaneously adopts binder 2 and binder 3 to directly increase the thickness of the insulating layer, directly improves the insulating capacity and meets the high-voltage isolation requirements. Among them, the choice of insulator 1 and insulator 2 can select insulating materials with a linear expansion coefficient similar to that of the chip, such as silicon dioxide, etc., and its thickness can be achieved through a grinding process. The processing is simple, the cost is low and it is easy to achieve. Both binder 2 and binder 3 can be achieved using a common dispensing process, which is easy to operate. Binding material 3 can be achieved by insulating film attachment or insulating glue coating process before low-voltage chip wafer dicing. The operation is simple and easy to achieve, the structure is simple, and the process is easy to achieve. The voltage resistance is greatly improved to meet the high-voltage isolation requirements. Due to the addition of multiple layers of binders and insulators, the creepage distance of the corresponding adjacent chips is also greatly increased. This structural principle can be used on all multi-chip packaging or stacked packaging products to meet the voltage resistance requirements.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本实用新型提出的一种高压隔离封装结构的侧视图;FIG1 is a side view of a high voltage isolation packaging structure proposed by the present invention;
图2为图1中A的放大图。FIG. 2 is an enlarged view of A in FIG. 1 .
图例说明:illustration:
1、塑封体;2、高压芯片;3、结合材一;4、第一基岛;5、结合材二;6、隔离物一;7、结合材三;8、隔离物二;9、低压芯片;10、第二基岛。1. Plastic package; 2. High-voltage chip; 3. Binding material 1; 4. First base island; 5. Binding material 2; 6. Isolator 1; 7. Binding material 3; 8. Isolator 2; 9. Low-voltage chip; 10. Second base island.
具体实施方式Detailed ways
参照图1-2,本实用新型提供的一种实施例:一种高压隔离封装结构,包括第一基岛4和第二基岛10,第一基岛4的上端固定连接有结合材二5,结合材二5上端设置有隔离物一6,隔离物一6上端设置有结合材三7,结合材三7上端设置有隔离物二8,隔离物二8上端设置有低压芯片9,结合材二5和结合材三7多使用绝缘材质,如绝缘胶等,隔离物一6在考虑低成本可以使用裸硅片,考虑绝缘效果可以考虑陶瓷片等,隔离物二8可以使用绝缘胶或绝缘膜。1-2, the utility model provides an embodiment: a high-voltage isolation packaging structure, including a first base island 4 and a second base island 10, the upper end of the first base island 4 is fixedly connected with a bonding material 2 5, the upper end of the bonding material 2 5 is provided with an insulator 1 6, the upper end of the insulator 1 6 is provided with a bonding material 3 7, the upper end of the bonding material 3 7 is provided with an insulator 2 8, and the upper end of the insulator 2 8 is provided with a low-voltage chip 9. The bonding material 2 5 and the bonding material 3 7 are mostly made of insulating materials, such as insulating glue, etc. The insulator 1 6 can use a bare silicon wafer in consideration of low cost, and a ceramic wafer can be considered in consideration of insulation effect, and the insulator 2 8 can use insulating glue or insulating film.
第一基岛4的上端固定连接有结合材一3,结合材一3多使用导电材料,如锡膏、铅锡丝、导电胶等,结合材一3的上端固定连接有高压芯片2,且高压芯片2、低压芯片9第二基岛10之间均设置有引线,第一基岛4上设置有塑封体1。The upper end of the first base island 4 is fixedly connected with a binding material 3, and the binding material 3 mostly uses a conductive material, such as solder paste, lead-tin wire, conductive glue, etc. The upper end of the binding material 3 is fixedly connected with a high-voltage chip 2, and leads are arranged between the high-voltage chip 2 and the low-voltage chip 9 and the second base island 10. A plastic package 1 is arranged on the first base island 4.
工作原理:隔离物一6和隔离物二8同时采用结合材二5和结合材三7来直接增加绝缘层厚度,直接提升绝缘能力,满足高压隔离需求,其中隔离物一6和隔离物二8的选择可以选择线膨胀系数与芯片相近的绝缘材料,如二氧化硅等,其厚度可以通过研磨工艺实现,加工简单成本较低且易于实现,结合材二5、结合材三7均可以使用常见的点胶工艺实现,操作简便,结合材三7可以在低压芯片9晶圆划片前进行绝缘膜贴附或者绝缘胶涂覆工艺实现,作业简单易实现。Working principle: Insulator 1 6 and insulator 2 8 use binding material 2 5 and binding material 3 7 to directly increase the thickness of the insulation layer, directly improve the insulation capacity, and meet the high-voltage isolation requirements. Insulator 1 6 and insulator 2 8 can be selected from insulating materials with a linear expansion coefficient similar to that of the chip, such as silicon dioxide, and their thickness can be achieved through a grinding process. The processing is simple, low-cost and easy to achieve. Binding material 2 5 and binding material 3 7 can both be achieved using a common dispensing process, which is easy to operate. Binding material 3 7 can be achieved by insulating film attachment or insulating glue coating process before the low-voltage chip 9 wafer is diced. The operation is simple and easy to achieve.
最后应说明的是:以上所述仅为本实用新型的优选实施例而已,并不用于限制本实用新型,尽管参照前述实施例对本实用新型进行了详细的说明,对于本领域的技术人员来说,其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换,凡在本实用新型的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本实用新型的保护范围之内。Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
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