CN221327371U

CN221327371U - EFUSE memory cell, programming and reading circuit and electronic equipment

Info

Publication number: CN221327371U
Application number: CN202323330807.5U
Authority: CN
Inventors: 周健; 王帅旗; 张代中
Original assignee: Jiefang Semiconductor Shanghai Co ltd
Current assignee: Jiefang Semiconductor Shanghai Co ltd
Priority date: 2023-12-07
Filing date: 2023-12-07
Publication date: 2024-07-12
Anticipated expiration: 2033-12-07

Abstract

The utility model discloses an EFUSE storage unit, a programming reading circuit and electronic equipment, which belong to the technical field of integrated circuits, wherein the EFUSE storage unit comprises a constant current source module, a programming control signal port and a bias voltage signal port, wherein the constant current source module is used for connecting the programming control signal port and the bias voltage signal port, providing a first current larger than a preset value before programming and providing a second current smaller than the preset value after programming; a Latch circuit module; the numerical control current mirror module comprises an inverter, a transmission gate and a current mirror. The logic state of the first node is latched by the Latch circuit module and is output to the Latch data output port, and if the Latch data output port is 1, the EFUSE memory cell is not burnt, and if the Latch data output port is 0, the EFUSE memory cell is burnt, so that the problem of the conventional EFUSE memory cell can be solved.

Description

EFUSE memory cell, programming and reading circuit and electronic equipment

Technical Field

The present utility model relates to the field of integrated circuits, and in particular, to an EFUSE memory cell, a programming and reading circuit, and an electronic device.

Background

EFUSE, collectively known as an "electronic fuse," is a programmable electronic fuse, a non-volatile memory device used to store information and protect a chip. Compared with other memories such as fuse and laser fuse, which are One Time Program (OTP), the efuse has the advantages of no need of additional equipment to assist in fusing, good process compatibility, small occupied area and the like, so the efuse is widely applied.

As shown in FIG. 1, R _fuse is an electronic fuse, typically composed of a thin section of polysilicon, which has a small resistance, e.g., several tens of ohms, prior to programming. The first NMOS transistor N1 is a NMOS transistor with a relatively large width and length, the gate of which is controlled by the programming signal Din, when din=1, N1 is turned on, and a relatively large current flows to Gnd (ground) through R _fuse and N1, and the heat generated by this large current on the fuse will cause the fuse to be blown completely under ideal conditions, so that the open circuit appears, and the equivalent resistance of R _fuse approaches infinity.

The grid electrode of the second NMOS tube N2 is connected to a bias voltage VBIAS, the second NMOS tube N2 is equivalent to a constant current source, and the current value is set as I; the third NMOS transistor N3, the first PMOS transistor P1, and the inverter INV3 form a transmission gate, and the input end of the inverter INV3 and the gate of the third NMOS transistor N3 are connected to the Read control signal Read. When read=1, this transmission gate is turned on. For the efuse memory cell that has not been burned, the R _fuse resistance is very small, and the voltage of the NetA node is equal to VDD-I R _fuse, which is a value very close to VDD, so the NetA node appears as a logic 1; whereas for eufse memory cells that underwent programming, ideally R _fuse was completely blown and presented as an open circuit, the voltage at the NetA node would be equal to Gnd, i.e., appear as a logic 0.

Latch in fig. 1 is a Latch, whose circuit is shown in fig. 2, whose sampling clock signal CP is coupled to the Read control signal Read, and which samples the logic state of the NetA node when read=1, and latches the logic state of the NetA node when read=0, and outputs it from its Dout port.

However, due to some non-idealities, R _fuse may not be completely fused after burning, but may appear as a larger resistance, such as several kiloohms to several tens of kiloohms, at which time even if burning is performed again, the current flowing through R _fuse is too small due to the larger resistance at this time, and the generated heat is insufficient to completely fuse it. In this case, when the Read control signal read=1, the transmission gate composed of the third NMOS transistor N3, the first PMOS transistor P1 and the inverter INV3 is turned on, since R _fuse is not completely blown, but equivalent to a resistor having a resistance value of several kiloohms to several tens of kiloohms, if the current I of the constant current source is relatively small, the voltage of the NetA node will be equal to VDD-i×r _fuse, which is a voltage between VDD and GND, and in the extreme case may even be in the vicinity of the intermediate value of VDD and GND, which will cause the subsequent Latch circuit to fail to determine whether the logic state of the NetA node is 0 or 1, resulting in a Read error.

In general, the current I of the constant current source is increased to make the value of i×r _fuse larger than VDD, so that the voltage of the NetA node is equal to Gnd (i.e., it appears as logic 0), so that in order to read the correct value, a larger current I of the constant current source must be set, which results in larger power consumption during reading.

It should be noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of utility model

The utility model aims to provide an EFUSE memory cell, a programming and reading circuit and electronic equipment, which are used for solving the problem that a Latch cannot accurately judge the state of a NetA node, namely the circuit condition or the condition of R _fuse cannot be judged due to incomplete fusing of R _fuse.

In order to solve the above technical problems, the present utility model provides an EFUSE memory unit, including:

The constant current source module is used for connecting the burning control signal port and the bias voltage signal port, providing a first current larger than a preset value before burning and providing a second current smaller than the preset value after burning, and comprises an electronic fuse;

The Latch data input port of the Latch circuit module is connected with the first node, and the sampling clock port is connected with the readout control signal;

The digital control current mirror module comprises an inverter, a transmission gate and a current mirror, wherein the input end of the inverter is connected with the readout control signal, the input end and the output end of the inverter are respectively connected with a first control input end and a second control input end of the transmission gate, the signal input end of the transmission gate is connected with a bias current input port, the bias current input port is used for providing a bias current signal with a preset value, the signal output end of the transmission gate is connected with a reference current input end of the current mirror, the copy current input end of the current mirror is connected with a first node, the first node is also connected with a second end of the electronic fuse, a grid interconnection node in the current mirror is also connected with a drain electrode of a fourth switching transistor, a grid electrode of the fourth switching transistor is connected with the output end of the inverter, and a source electrode of the fourth switching transistor is commonly connected with the reference current output end and the copy current output end of the current mirror to the ground.

Preferably, the constant current source module further includes a second control transistor, a first end of the electronic fuse is connected to a power supply voltage, a second end of the electronic fuse is connected to a source electrode of the second control transistor, a drain electrode of the second control transistor is connected to the first node, a gate electrode of the second control transistor is connected to the bias voltage signal port, the burning control signal port is connected to a gate electrode of the first switching transistor, a drain electrode of the first switching transistor is connected to a second end of the electronic fuse, and a source electrode of the first switching transistor is grounded.

Preferably, the transmission gate includes a fifth switching transistor and a first control transistor, drain electrodes of the fifth switching transistor and the first control transistor are interconnected as the signal input terminal to be connected to the bias current input port, and a gate electrode of the fifth switching transistor is used as the first control input terminal to be connected to an input terminal of the inverter; the sources of the fifth switching transistor and the first control transistor are interconnected as the signal output terminal to be connected to the reference current input terminal of the current mirror, and the gate of the first control transistor is interconnected as the second control input terminal to be connected to the output terminal of the inverter.

Preferably, the current mirror includes a third switching transistor and a second switching transistor, gates of the third switching transistor and the second switching transistor are interconnected and serve as the gate interconnection node, a drain electrode and a gate interconnection of the third switching transistor serve as the reference current input terminal, a drain electrode of the second switching transistor serves as the replica current input terminal to be connected to the first node, and sources of the second switching transistor and the third switching transistor are a replica current output terminal and a reference current output terminal, respectively.

The application also provides an EFUSE programming and reading circuit, which comprises:

A common bias unit for providing a bias current signal to the bias current input port and a bias voltage signal to the bias voltage signal port;

At least one EFUSE memory unit, the EFUSE memory unit comprising:

Preferably, the common bias unit includes a first resistor, a second resistor, a third control transistor and a fourth control transistor, wherein a first end of the first resistor and a first end of the second resistor are commonly connected and connected to a power supply voltage, a source electrode of the third control transistor is connected with a second end of the first resistor, a gate electrode of the third control transistor is commonly connected with a drain electrode for accessing an external bias current signal, a source electrode of the fourth control transistor is connected with a second end of the second resistor, gates of the third control transistor and the fourth control transistor are commonly connected and connected with the bias voltage signal port to provide a bias voltage signal, and a drain electrode of the fourth control transistor is used for outputting the bias current signal to the bias current input port.

The disclosure further provides an electronic device, which uses the EFUSE programming and reading circuit to program and read the EFUSE memory unit.

The disclosure also provides a programming and reading method of the EFUSE programming and reading circuit, which uses the EFUSE programming and reading circuit to program and read the EFUSE memory cell, and further comprises the following steps:

When the burning is performed: providing a read control signal for the EFUSE storage unit, and when the read control signal is at a first level, burning the EFUSE storage unit in sequence, and judging the burning state of the EFUSE storage unit through a level signal of a Latch data output port of the Latch circuit module;

When reading: and providing a read control signal for the EFUSE storage unit, and sequentially reading the EFUSE storage unit when the read control signal is at a second level.

In the EFUSE memory cell provided by the utility model, when the Read control signal Read jumps from 1 to 0, the logic state of the first node NetA is latched by the Latch circuit module and is output to the Latch data output port Dout thereof, if the Latch data output port Dout is logic 1, the EFUSE memory cell is not programmed, and if the Latch data output port Dout is logic 0, the EFUSE memory cell is programmed, thereby avoiding the problem of Read error caused by incomplete programming of the electronic fuse R _fuse. Further, the output result of the first node NetA is not affected by the preset value, so that the bias current signal I can be set to a smaller value, and the power consumption in the reading process can be greatly reduced.

The EFUSE programming and reading circuit and the electronic device provided by the utility model belong to the same conception as the EFUSE storage unit provided by the utility model, so that the EFUSE programming and reading circuit and the electronic device provided by the utility model have at least all advantages of the EFUSE storage unit provided by the utility model and are not repeated herein. The common bias unit is used for providing a bias current signal to the bias current input port and providing a bias voltage signal to the bias voltage signal port; at least one EFUSE memory unit, the EFUSE memory unit comprising: the constant current source module is used for connecting the burning control signal port and the bias voltage signal port, providing a first current larger than a preset value before burning and providing a second current smaller than the preset value after burning, and comprises an electronic fuse; the Latch data input port of the Latch circuit module is connected with the first node, and the sampling clock port is connected with the readout control signal; the digital control current mirror module comprises an inverter, a transmission gate and a current mirror, wherein the input end of the inverter is connected with the readout control signal, the input end and the output end of the inverter are respectively connected with a first control input end and a second control input end of the transmission gate, the signal input end of the transmission gate is connected with a bias current input port, the bias current input port is used for providing a bias current signal with a preset value, the signal output end of the transmission gate is connected with a reference current input end of the current mirror, the copy current input end of the current mirror is connected with a first node, the first node is also connected with a second end of the electronic fuse, a grid interconnection node in the current mirror is also connected with a drain electrode of a fourth switching transistor, a grid electrode of the fourth switching transistor is connected with the output end of the inverter, and a source electrode of the fourth switching transistor is commonly connected with the reference current output end and the copy current output end of the current mirror to the ground.

Drawings

FIG. 1 is a circuit diagram of a conventional EFUSE memory cell;

FIG. 2 is a circuit diagram of a conventional Latch module;

FIG. 3 is a circuit diagram of an EFUSE memory cell according to one embodiment of the present utility model;

FIG. 4 is a circuit diagram of a common bias unit according to an embodiment of the present utility model;

FIG. 5 is a schematic diagram illustrating a connection relationship between an EFUSE memory cell and a common bias cell in a 4-bit EFUSE memory according to an embodiment of the present utility model;

FIG. 6 is a timing diagram of a burn operation for the 4bit EFUSE memory shown in FIG. 5;

FIG. 7 is a timing diagram of a read operation to the 4bit EFUSE memory shown in FIG. 5.

In the figure: 100. a common bias unit; 200. EFUSE memory cell; 201. a constant current source module; 202. and the numerical control current mirror module.

Detailed Description

The EFUSE memory cell, the programming and reading circuit and the electronic device provided by the utility model are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present utility model will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model. It should be understood that the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the utility model. Specific design features of the utility model disclosed herein, including for example, specific dimensions, orientations, positions, and configurations, will be determined in part by the specific intended application and use environment. In the embodiments described below, the same reference numerals are used in common between the drawings to denote the same parts or parts having the same functions, and the repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

The inventor researches and discovers that when the conventional EFUSE memory cell is used, the conventional EFUSE memory cell is not completely fused, so that the Latch module Latch connected with the conventional EFUSE memory cell cannot read the state of the electronic fuse, and the method of increasing the current of the constant current source part has the defect of needing a large amount of power consumption.

Based on this, the core idea of the present utility model is that by providing an EFUSE memory cell, the logic state of the first node can be latched by the Latch circuit module and output to the Latch data output port Dout thereof, and a Dout port of 1 indicates that the EFUSE memory cell is not programmed, and a Dout port of 0 indicates that the EFUSE memory cell is programmed, so that the problem of the conventional EFUSE memory cell can be solved.

Specifically, please refer to fig. 3-7, which are schematic diagrams of an embodiment of the present utility model. As shown in fig. 3, an EFUSE memory cell includes:

The constant current source module 201 is configured to connect the programming control signal port Din and the bias voltage signal port VBP, provide a first current I ₁ greater than a preset value before programming, and provide a second current I ₂ less than the preset value after programming, where the constant current source module 201 includes an electronic fuse R _fuse;

A Latch circuit module (not labeled), wherein a Latch data input port D of the Latch circuit module is connected with a first node NetA, and a sampling clock port CP is connected with a Read control signal Read;

The digitally controlled current mirror module 202 includes an inverter INV3, a transmission gate and a current mirror, where an input end of the inverter INV3 is connected to the readout control signal Read, an input end and an output end of the inverter INV3 are respectively connected to a first control input end and a second control input end of the transmission gate, a signal input end of the transmission gate is connected to a bias current input port IBIAS, the bias current input port IBIAS is used for providing a bias current signal I with the preset value, a signal output end of the transmission gate is connected to a reference current input end of the current mirror, a copy current input end of the current mirror is connected to the first node NetA, the first node NetA is also connected to a second end of the electronic fuse R _fuse, a gate interconnection node in the current mirror is also connected to a drain electrode of a fourth switching transistor N4, a gate of the fourth switching transistor N4 is connected to an output end of the inverter 3, and a copy current input end of the fourth switching transistor N4 is connected to the reference current output end of the current mirror and the reference current d is connected to the common ground.

When the Read control signal read=0, or the Read control signal Read is at a low level, the transmission gate in fig. 3 is turned off, the bias current input port IBIAS is in a high-resistance state, and at the same time, the fourth switching transistor N4 is turned on, the current mirror is turned off, and no current flows through the current mirror.

In contrast, when the Read control signal read=1, or the Read control signal Read is at a high level, the transmission gate is turned on, the gate voltage of the fourth switching transistor N4 is 0, the fourth switching transistor N4 is turned off, and the reference current input terminal of the current mirror and the current flowing in the replica current input terminal are the same, that is, equal to the bias current signal I input by the bias current input port IBIAS.

As can be seen from the above analysis, for the unfired EFUSE memory cell 200, the first current I ₁ provided by the constant current source module 201 is greater than the preset value, i.e. the first current I ₁ is greater than the bias current signal I, so the node voltage of the first node NetA is at a high level, i.e. it is expressed as logic 1; for the burned EFUSE memory cell 200, the second current I ₂ provided by the constant current source module 201 is smaller than the preset value, so the node voltage of the first node NetA is low, i.e. it is expressed as logic 0. Therefore, when the Read control signal Read jumps from 1 to 0, the logic state of the first node NetA is latched by the Latch circuit module and is output to the Latch data output port Dout, if the Latch data output port Dout is logic 1, it indicates that the EFUSE memory cell 200 is not programmed, and if the Latch data output port Dout is logic 0, it indicates that the EFUSE memory cell 200 is programmed, so as to avoid the problem of a Read error caused by incomplete programming of the electronic fuse R _fuse.

It will be appreciated that the magnitude of the predetermined value does not affect the output of the first node NetA, so that the bias current signal I can be set to a smaller value, for example 10uA, which can greatly reduce the power consumption during reading.

Specifically, the constant current source module 201 further includes a second control transistor P2, a first end of the electronic fuse R _fuse is connected to the power supply voltage VDD, a second end is connected to the source of the second control transistor P2, the drain of the second control transistor P2 is connected to the first node NetA, the gate is connected to the bias voltage signal port VBP, the burning control signal port Din is connected to the gate of the first switching transistor N1, the drain of the first switching transistor N1 is connected to the second end of the electronic fuse R _fuse, and the source of the first switching transistor N1 is grounded.

As shown in fig. 3, the constant current source module 201 is composed of a second control transistor P2 and an electronic fuse R _fuse, the gate voltage of the second control transistor P2 is connected to the bias voltage signal port VBP, the electronic fuse R _fuse is a polysilicon fuse, and the constant current source module 201 is further externally connected with the bias voltage signal port VBP and the burning control signal port Din.

If the electronic fuse is not burned, the resistance of the electronic fuse R _fuse is relatively small, so that a larger current can be generated based on an external signal, namely a first current I ₁ larger than a bias current signal I; if the resistor is burned, the resistance of the resistor fuse R _fuse increases, so as to generate a second current I ₂ smaller than the bias current signal I.

Specifically, the transmission gate includes a fifth switching transistor N5 and a first control transistor P1, drains of the fifth switching transistor N5 and the first control transistor P1 are interconnected as the signal input terminal to be connected to the bias current input port, and a gate of the fifth switching transistor N5 is used as the first control input terminal to be connected to an input terminal of the inverter INV 3; the sources of the fifth switching transistor N5 and the first control transistor P1 are interconnected as the signal output terminal to be connected to the reference current input terminal of the current mirror, and the gate of the first control transistor P1 is interconnected as the second control input terminal to be connected to the output terminal of the inverter INV 3.

The transmission gate is used for transmitting the input current of the bias current input port IBIAS to the current mirror, and is controlled by the Read control signal Read, when the Read control signal read=0, the transmission gate formed by the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 is disconnected, the bias current input port IBIAS is in a high-resistance state, meanwhile, the gate voltage of the fourth switching transistor N4 is a high voltage, the fourth switching transistor N4 is turned on, and the current mirror is turned off. If read=1, the transmission gate composed of the fifth switching transistor N5, the first control transistor P1, and the inverter INV3 is turned on.

Specifically, the current mirror includes a third switching transistor N3 and a second switching transistor N2, gates of the third switching transistor N3 and the second switching transistor N2 are interconnected and serve as the gate interconnection node, a drain electrode and a gate interconnection of the third switching transistor N3 serve as the reference current input end, a drain electrode of the second switching transistor N2 serves as the copy current input end to be connected with the first node NetA, and sources of the second switching transistor N2 and the third switching transistor N3 are respectively a copy current output end and a reference current output end.

In one example, the second switching transistor N2 and the third switching transistor N3 are the same size, and form a mirror with a mirror ratio of 1:1, and the current flowing through both are the same and equal to the current I flowing into the bias current input port IBIAS.

The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices of the same characteristics, and according to the role in the circuit, the transistors used in the embodiments of the present application are mainly CMOS transistors (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors). The switch transistor is an NMOS transistor, and the control transistor is a PMOS transistor.

Based on the same inventive concept, the utility model also provides an EFUSE programming and reading circuit, which comprises:

A common bias unit 100 for providing a bias current signal I to the bias current input port IBIAS and a bias voltage signal to the bias voltage signal port VBP;

at least one EFUSE memory unit 200, the EFUSE memory unit comprising:

The constant current source module 201 includes an electronic fuse R _fuse, which is configured to connect the burning control signal port Din and the bias voltage signal port VBP, and provide currents with different magnitudes before and after burning: providing a first current I ₁ which is larger than a preset value before burning, and providing a second current I ₂ which is smaller than the preset value after burning;

The Latch data input port D of the Latch circuit module is connected with the NetA of the first node, and the sampling clock port CP is connected with the Read control signal Read;

the digitally controlled current mirror module 202 includes an inverter INV3, a transmission gate and a current mirror, where an input end of the inverter INV3 is connected to the readout control signal Read, an input end and an output end of the inverter INV3 are respectively connected to a first control input end and a second control input end of the transmission gate, a signal input end of the transmission gate is connected to the bias current input port IBIAS, the bias current input port IBIAS is used for providing a bias current signal I with the preset value, a signal output end of the transmission gate is connected to a reference current input end of the current mirror, a copy current input end of the current mirror is connected to the first node, the first node NETA is also connected to a second end of the electronic fuse R _fuse, a gate interconnection node in the current mirror is also connected to a drain electrode of a fourth switching transistor, a gate of the fourth switching transistor N4 is connected to an output end of the inverter, and a source electrode of the fourth switching transistor N4 is connected to the output end of the current mirror and the copy current input end of the current mirror is connected to the reference current d.

The EFUSE programming and reading circuit provided by the disclosure has no difference from a conventional EFUSE memory cell in the programming process, when the programming signal din=1, the programming tube N1 is turned on, a large current flows through the electronic fuse R _fuse, and the R _fuse is completely fused or the resistance value is increased to several kiloohms to several tens kiloohms due to heat generation.

Specifically, the common bias unit 100 includes a first resistor R1, a second resistor R2, a third control transistor P3, and a fourth control transistor P4, where a first end of the first resistor R1 and a first end of the second resistor R2 are commonly connected and connected to a power supply voltage VDD, a source of the third control transistor P3 is connected to the second end of the first resistor R1, a gate and a drain of the third control transistor P3 are commonly connected for accessing an external bias current signal IBIN, a source of the fourth control transistor P4 is connected to the second end of the second resistor R2, gates of the third control transistor P3 and the fourth control transistor P4 are commonly connected and connected to the bias voltage signal port VBP to provide a bias voltage signal, and a drain of the fourth control transistor P4 is used for outputting the bias current signal I to the bias current input port ibs.

As shown in fig. 4, which is a circuit diagram of the common bias unit 100, IBIN is a bias current input port of the common bias unit 100, IBOUT is a bias current output port of the common bias unit 100, and VBP is a bias voltage output port of the common bias unit 100.

In one embodiment, the resistances of the first resistor R1 and the second resistor R2 are the same, and the resistances are slightly larger than the resistance of the non-burned resistor fuse R _fuse in the EFUSE memory cell 200 (for example, the resistance of the non-burned resistor fuse R _fuse is 50 ohms, and then the resistances of the first resistor R1 and the second resistor R2 are set to 200 ohms). The third control transistor P3 and the fourth control transistor P4 are PMOS transistors of identical dimensions, thus forming a current mirror, the current flowing through the fourth control transistor P4 and the second resistor R2 will be equal to the current flowing through the third control transistor P3 and the first resistor R1, the bias current input port IBIN of the common bias unit 100 is set to have a predetermined value of current I, the current flowing through the third control transistor P3 and the first resistor R1 is equal to I, the current flowing through the fourth control transistor P4 and the second resistor R2 is also equal to I, the bias current output port IBOUT of the common bias unit 100 is equal to I, i.e. in the EFUSE memory cell 200, the bias current input port ias is connected to the bias current output port IBOUT of the common bias unit 100

In one embodiment, the constant current source module 201 is composed of a second control transistor P2 and an electronic fuse R _fuse, the gate voltage of the second control transistor P2 is connected to the bias voltage signal port VBP, that is, connected to the bias voltage signal port VBP of the common bias unit 100, the electronic fuse R _fuse is a polysilicon fuse, the second control transistor P2 is the same size as the third control transistor P3 and the fourth control transistor P4 in the common bias unit 100, the gates of the second control transistor P2 are connected to the bias voltage signal port VBP, and the bias current output port IBOUT of the common bias unit 100 is connected to the bias current input ports IBIAS of all the EFUSE memory cells 200.

It will be appreciated that in the unfired EFUSE memory cell 200, the resistance of the electronic fuse R _fuse is smaller than the resistances of the first resistor R1 and the second resistor R2 in FIG. 4, and thus the first current I _1, provided by the constant current source module 201 will be larger than the currents flowing through the first resistor R1 and the second resistor R2, i.e. larger than the bias current signal I, and the resistance of the electronic fuse R _fuse will be larger than the resistances of the first resistor R1 and the second resistor R2 in FIG. 4 after the burning, and the second current I _2, provided by the constant current source module 201 will be smaller than the currents flowing through the first resistor R1 and the second resistor R2, i.e. smaller than the bias current signal I.

In one example, the second switching transistor N2 and the third switching transistor N3 are the same size, form a mirror with a mirror ratio of 1:1, and have the same current flowing through them, which is equal to the current I flowing into the bias current input port IBIAS, which is connected to the IBOUT port of the common bias cell 100, and is equal to I.

Based on the same technical conception, the application also provides electronic equipment, which adopts the EFUSE programming and reading circuit to program and read the EFUSE storage unit.

Based on the same technical conception, the application also provides a programming and reading method of the EFUSE programming and reading circuit, which is used for programming and reading the EFUSE storage unit and comprises the following steps:

When the burning is performed: providing a Read control signal to the EFUSE memory cell 200, and when the Read control signal Read is at a first level, sequentially burning the EFUSE memory cell 200, and judging the burning state of the EFUSE memory cell through a level signal of a Latch data output port Dout of the Latch circuit module;

when reading: the read control signal is provided to the EFUSE memory cell 200 and when the read control signal is at a second level, the EFUSE memory cell 200 is sequentially read.

The first level is, for example, a low level, and the second level is, for example, a high level.

As shown in fig. 5, the whole memory is composed of a common bias circuit and a plurality of EFUSE memory cells 200, and the IBIN ports are bias current input ports, and an external reference current source is required. The common bias cell 100 generates a bias voltage signal (VBP) coupled to the bias voltage signal ports VBP of all EFUSE memory cells 200 and a bias current signal (IBOUT) coupled to the IBIAS ports of all EFUSE memory cells 200. The VBP port of EFUSE memory cell 200 is a bias voltage input port, IBIAS is a bias current input port, read is a Read control signal, din is a burn control signal port, dout is a latched store data output port.

Fig. 5 is only an example of a 4bit effuse memory, and if a larger capacity EFUSE memory is required, EFUSE memory unit 200 is simply extended according to the connection.

When performing the writing, for example, the EFUSE memory cell 200 to be written is shown in fig. 5 with the first, third and fourth from top to bottom, and the timing sequence is shown in fig. 6. The Read control signal Read of all EFUSE memory cells 200 is equal to 0 or low level, then let the write control signal Din <3> of the first EFUSE memory cell 200 equal to 1, write the first EFUSE memory cell 200, restore Din <3> to 0 after the write is completed, since the second EFUSE memory cell 200 is not written, let the write control signal Din <2> of the second EFUSE memory cell 200 constantly remain to 0, then let the write control signal Din <1> of the third EFUSE memory cell 200 equal to 1, write the third memory cell, let Din <1> restore to 0 after the write is completed, finally let the write signal Din <0> of the fourth memory cell equal to 1, and let Din <0> restore to 0 after the write is completed.

As shown in FIG. 7, the timing of the Read operation is shown in FIG. 7, all the programming control signals Din are equal to 0, the first EFUSE memory cell 200 is first Read, the Read <3> is equal to 1, the Read control signals Read of the other EFUSE memory cells 200 are equal to 0, the IBIAS ports of the other EFUSE memory cells 200 except the first EFUSE memory cell 200 are all in the high impedance state, the bias current signal output by the common bias unit 100 only flows into the bias current input port IBIAS of the first EFUSE memory cell 200, the Read <3> jumps from 1 to 0 after a period of time, and the Read operation of the first EFUSE memory cell 200 is completed, and the data stored in the first EFUSE memory cell 200 is latched to the Dout <3> port. The reading of other memory cells is then completed one by one in the same manner as the above.

Where fig. 4 is a circuit diagram of the common bias unit 100, IBIN is a bias current input port of the common bias unit 100, IBOUT is a bias current output port of the common bias unit 100, and VBP is a bias voltage output port of the common bias unit 100. The resistance of the first resistor R1 and the second resistor R2 are the same, and the resistance is slightly larger than the resistance of the electronic fuse R _fuse that is not burned in the EFUSE memory cell 200 (for example, the resistance of the electronic fuse R _fuse that is not burned is 50 ohms, and the resistance of the first resistor R1 and the second resistor R2 is set to 200 ohms). The third control transistor P3 and the fourth control transistor P4 are PMOS transistors with identical dimensions, thus forming a current mirror, the current flowing through the fourth control transistor P4 and the second resistor R2 will be equal to the current flowing through the third control transistor P3 and the first resistor R1, the bias current input at the IBIN port is set to be I, the current flowing through the third control transistor P3 and the first resistor R1 is equal to I, the current flowing through the fourth control transistor P4 and the second resistor R2 is also equal to I, and the current output at the IBOUT port is equal to I.

The constant current source module 202 is composed of a second control transistor P2 and an electronic fuse R _fuse, wherein the gate voltage of the second control transistor P2 is connected to the VBP port of the common bias unit 100, R _fuse is a polysilicon fuse, the second control transistor P2 in fig. 3 is the same size as the third control transistor P3 and the fourth control transistor P4 in fig. 4, and their gate electrodes are connected to the bias current input port VBP of the common bias unit 100. If the electronic fuse R _fuse is not burned, the resistance of the electronic fuse R _fuse is smaller than the resistances of the first resistor R1 and the second resistor R2 in fig. 4, so the current provided by the constant current source module 202 in fig. 3 will be greater than the first current I ₁ flowing through the third control transistor P3 and the first resistor R1 in fig. 4, i.e. greater than I; after the burning, the resistance of the electronic fuse R _fuse will be greater than the resistances of the first resistor R1 and the second resistor R2 in fig. 4, and the second current I ₂ of the constant current source module 201 in fig. 3 will be smaller than the current flowing through the third control transistor P3 and the first resistor R1 in fig. 4, that is, smaller than I.

If the Read control signal read=0, the transmission gate formed by the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 in fig. 3 is turned off, the IBIAS port is in a high-resistance state, the gate voltage of the fourth switching transistor N4 is high, the fourth switching transistor N4 is turned on, the gate voltages of the second switching transistor N2 and the third switching transistor N3 are pulled to ground Gnd, the second switching transistor N2 and the third switching transistor N3 are turned off, and no current flows through the second switching transistor N2 and the third switching transistor N3.

If the Read control signal read=1, the transmission gate formed by the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 in fig. 3 is turned on, the gate voltage of the fourth switching transistor N4 is 0, the fourth switching transistor N4 is turned off, the second switching transistor N2 and the third switching transistor N3 form a mirror with a mirror ratio of 1:1 because the second switching transistor N2 and the third switching transistor N3 have the same size, the currents flowing through the two transistors are the same and equal to the current flowing into the IBIAS port, and the current flowing into the IBIAS port is equal to I because the IBIAS port is connected to the IBOUT port of the common bias unit 100, and the currents flowing through the second switching transistor N2 and the third switching transistor N3 are both equal to I.

Based on the above analysis, for the unfired EFUSE memory cell 200, the constant current source current in FIG. 3 is greater than I, so the first node NetA node voltage will be high, i.e. appear as logic 1; for the burned EFUSE memory cell 200, the current output by the constant current source module 201 in FIG. 3 is less than I, and the voltage of the first node NetA node will be low, i.e. appear as logic 0. The size of I does not affect the output result of the first node NetA node, so that I can be set to a smaller value, such as 10uA, and the power consumption in the reading process is greatly reduced. When the Read control signal Read changes from 1 to 0, the logic state of the NetA node of the first node is latched by the Latch circuit module and is output to the Dout port, which indicates that the EFUSE memory cell 200 is not programmed if the Dout port is 1, and indicates that the EFUSE memory cell 200 is programmed if the Dout port is 0.

In summary, in the EFUSE memory cell, the programming and reading circuit and the electronic device provided in the embodiments of the present utility model, when the Read control signal Read jumps from 1 to 0, the logic state of the first node NetA is latched by the Latch circuit module and is output to the Latch data output port Dout thereof, if the Latch data output port Dout is logic 1, it indicates that the EFUSE memory cell is not programmed, and if the Latch data output port Dout is logic 0, it indicates that the EFUSE memory cell is programmed, thereby avoiding the problem of a Read error caused by incomplete programming of the electronic fuse R _fuse. Further, the output result of the first node NetA is not affected by the preset value, so that the bias current signal I can be set to a smaller value, and the power consumption in the reading process can be greatly reduced.

The above description is only illustrative of the preferred embodiments of the present utility model and is not intended to limit the scope of the present utility model, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. An EFUSE memory cell comprising:

2. The EFUSE memory cell of claim 1 wherein the constant current source module further comprises a second control transistor, the first terminal of the electronic fuse being connected to a supply voltage, the second terminal being connected to a source of the second control transistor, a drain of the second control transistor being connected to the first node, a gate being connected to the bias voltage signal port, the programming control signal port being connected to a gate of a first switching transistor, a drain of the first switching transistor being connected to a second terminal of the electronic fuse, a source of the first switching transistor being grounded.

3. The EFUSE memory cell of claim 1 wherein the transfer gate includes a fifth switching transistor and a first control transistor, the drains of the fifth switching transistor and the first control transistor being interconnected as the signal input to connect to the bias current input port, the gate of the fifth switching transistor being the first control input to connect to the input of the inverter; the sources of the fifth switching transistor and the first control transistor are interconnected as the signal output terminal to be connected to the reference current input terminal of the current mirror, and the gate of the first control transistor is interconnected as the second control input terminal to be connected to the output terminal of the inverter.

4. The EFUSE memory cell of claim 2 wherein the current mirror includes a third switching transistor and a second switching transistor, gates of the third switching transistor and the second switching transistor being interconnected and acting as the gate interconnect node, drains of the third switching transistor and gate interconnect acting as the reference current input, drains of the second switching transistor acting as the replica current input to connect to the first node, sources of the second switching transistor and the third switching transistor being the replica current output and the reference current output, respectively.

5. An EFUSE programming read circuit comprising:

At least one EFUSE memory unit, the EFUSE memory unit comprising:

6. The EFUSE programming and reading circuit as set forth in claim 5, wherein the common bias unit comprises a first resistor, a second resistor, a third control transistor and a fourth control transistor, wherein the first end of the first resistor and the first end of the second resistor are commonly connected and connected to a power supply voltage, the source electrode of the third control transistor is commonly connected to the second end of the first resistor, the gate electrode of the third control transistor is commonly connected to the drain electrode for accessing an external bias current signal, the source electrode of the fourth control transistor is commonly connected to the second end of the second resistor, the gate electrodes of the third control transistor and the fourth control transistor are commonly connected and connected to the bias voltage signal port for providing the bias voltage signal, and the drain electrode of the fourth control transistor is used for outputting the bias current signal to the bias current input port.

7. The EFUSE programming and reading circuit as set forth in claim 5, wherein the constant current source module further comprises a second control transistor, a first terminal of the electronic fuse is connected to a power supply voltage, a second terminal of the electronic fuse is connected to a source of the second control transistor, a drain of the second control transistor is connected to the first node, a gate of the second control transistor is connected to the bias voltage signal port, the programming control signal port is connected to a gate of a first switching transistor, a drain of the first switching transistor is connected to a second terminal of the electronic fuse, and a source of the first switching transistor is grounded.

8. The EFUSE programming read circuit as set forth in claim 5, wherein the pass gate comprises a fifth switching transistor and a first control transistor, drain interconnections of the fifth switching transistor and the first control transistor being the signal input for connection to the bias current input port, a gate of the fifth switching transistor being the first control input for connection to an input of the inverter; the sources of the fifth switching transistor and the first control transistor are interconnected as the signal output terminal to be connected to the reference current input terminal of the current mirror, and the gate of the first control transistor is interconnected as the second control input terminal to be connected to the output terminal of the inverter.

9. The EFUSE programming read circuit as recited in claim 5, wherein the current mirror comprises a third switching transistor and a second switching transistor, gates of the third switching transistor and the second switching transistor being interconnected and acting as the gate interconnection node, drains and gates of the third switching transistor being interconnected as the reference current input, drains of the second switching transistor being acting as the replica current input to connect with the first node, sources of the second switching transistor and the third switching transistor being the replica current output and the reference current output, respectively.

10. An electronic device, wherein the EFUSE memory cell is programmed and read using the EFUSE programming read circuit as claimed in any one of claims 5-9.