CN210271793U - Anti-fuse memory cell circuit and array circuit - Google Patents
Anti-fuse memory cell circuit and array circuit Download PDFInfo
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- CN210271793U CN210271793U CN201921654359.5U CN201921654359U CN210271793U CN 210271793 U CN210271793 U CN 210271793U CN 201921654359 U CN201921654359 U CN 201921654359U CN 210271793 U CN210271793 U CN 210271793U
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Abstract
The utility model provides an antifuse memory cell circuit and array circuit, the utility model has the advantages of: 1. the anti-fuse memory cell circuit of the utility model is a pure combinational circuit, compared with a sequential circuit, after delaying a plurality of times, all the channels are closed, and the whole circuit has no logic action, the static power consumption is lower, and the power consumption is approximately 0; 2. the utility model discloses antifuse memory cell circuit has constituted two positive feedback loops by the design of switch and logical operation module in essence for read-out circuit can more reliable read out "0" or "1"; 3. the utility model discloses antifuse memory cell circuit can save complicated sequential control part, and the output OUTA OUTB of reading circuit even can be without latching, directly as antifuse's code output. 4. The utility model discloses antifuse memory cell circuit layout wiring is nimble.
Description
Technical Field
The utility model relates to an integrated circuit field especially relates to an antifuse memory cell circuit and array circuit.
Background
One Time Programmable (OTP) memory may store data in a plurality of OTP cells having both an unprogrammed state and a programmed state. The OTP cells may include fuses or antifuses, and once the fuses or antifuses are programmed, the stored data is permanent. Due to this characteristic, OTP memories are used in various applications to store data. In the DRAM, the OTP is used to control the turn-on or turn-off of a redundant (redundancy) memory cell, for example, when there is a defect in a memory cell corresponding to a word line, the corresponding OTP cell is programmed (the output state of the OTP cell is from "0" to "1"), the control circuit of the DRAM will turn off the read/write of the memory cell and turn on the read/write of a memory cell in the redundant area, at this time, the memory cell corresponding to the redundant area completely replaces the defective memory cell, and the defect of the DRAM is repaired.
The current one-time programmable memory has the following problems: 1. the problem of large static power consumption of the one-time programmable memory; 2. the problem of poor reliability of a read-out circuit of the one-time programmable memory; 3. the problem of complex control circuit of the one-time programmable memory; 4. the layout and wiring of the one-time programmable memory are not flexible.
Therefore, how to overcome the above problems is a technical problem which needs to be solved at present.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that an antifuse memory cell circuit and array circuit are provided, its static consumption is lower, and the reliability of reading out the circuit is high, and simple structure, and the wiring is nimble.
In order to solve the above problem, the present invention provides an antifuse memory cell circuit, which includes: an anti-fuse device; a switch module coupled to the antifuse device; a selection module coupled to the switch module; a control module coupled to the antifuse device and the switch module, respectively; the control module is used for switching the on-off mode of the switch module according to the breakdown state of the anti-fuse device.
Further, the antifuse device has a first end and a second end, the switch module includes a first switch unit and a second switch unit, the first switch unit and the second switch unit each have a first end, a second end and a control end, the control ends are both coupled to the control module, the second ends are both coupled to the selection module, the first end of the first switch unit is coupled to the first end of the antifuse device, and the first end of the second switch unit is coupled to the second end of the antifuse device.
Further, the switch module further includes a third switch unit having a first end, a second end and a control end, wherein the first end of the third switch unit is coupled to the first end of the antifuse device, the second end of the third switch unit is coupled to a ground signal, and the control end of the third switch unit is coupled to the control module.
Further, the selection module includes a bit line selection unit and a word line selection unit, each of the bit line selection unit and the word line selection unit has a first terminal, a second terminal, and a control terminal, the control terminal of the bit line selection unit is coupled to a bit line, the first terminal of the bit line selection unit is coupled to the second terminal of the second switch unit, the second terminal of the bit line selection unit is coupled to a ground signal, the control terminal of the word line selection unit is coupled to a word line, the first terminal of the word line selection unit is coupled to the second terminal of the first switch unit, and the second terminal of the word line selection unit is coupled to a power signal.
Further, the antifuse memory cell circuit further includes a current providing block having a first terminal coupled to a power signal and a second terminal coupled to the second terminal of the word line selection unit.
Further, the control module includes a control unit having an input terminal coupled to the first terminal of the antifuse device, a write enable signal, a read enable signal, and a read enable delay signal, and an output terminal coupled to the switch module.
Further, the control module further includes an amplifying unit having an input terminal coupled to the first terminal of the antifuse device and an output terminal coupled to the input terminal of the control unit, wherein the amplifying unit is configured to amplify a signal at the first terminal of the antifuse device.
Further, the control module further comprises a delay unit, the delay unit has an input end and an output end, the read enable signal is further coupled to the input end of the delay unit, the output end of the delay unit is coupled to the control unit, and the delay unit is used for delaying the read enable signal.
The present invention also provides an antifuse memory array circuit comprising a plurality of antifuse memory cell circuits as described above.
Further, the control modules of the antifuse memory unit are integrated into a total control module.
Further, the input terminal of the master control module is coupled to a write enable signal, a read enable delay signal and the first terminal of each of the antifuse devices.
Further, the output end of the master control module outputs a control signal, and the control signal is coupled to the third switching unit of the antifuse memory unit.
Further, at least a portion of the antifuse memory cell circuits share a current providing block.
Further, at least a portion of the antifuse memory cell circuits share a word line select unit.
The utility model has the advantages that:
1. the anti-fuse memory cell circuit of the utility model is a pure combinational circuit, compared with a sequential circuit, after delaying a plurality of times, namely completing the read-write operation, all the channels are closed, and the whole circuit has no logic action, the static power consumption is lower, and the power consumption is approximately 0;
2. the utility model discloses antifuse memory cell circuit has constituted two positive feedback loops through the design of switch and logical operation module in essence for read-out circuit can read out "0" or "1" more reliably;
3. the utility model discloses antifuse memory cell circuit can save complicated sequential control part, and the output OUTA OUTB of reading circuit even can be without latching, directly as antifuse's code output.
4. The utility model discloses antifuse memory cell circuit layout wiring is nimble.
Drawings
FIG. 1 is a circuit diagram of one embodiment of an antifuse memory cell circuit of the present invention;
FIG. 2 is a circuit diagram of a first embodiment of an antifuse memory array circuit;
FIG. 3 is a circuit diagram of a second embodiment of an antifuse memory array circuit;
FIG. 4 is a circuit diagram of a third embodiment of an antifuse memory array circuit.
Detailed Description
The following describes in detail embodiments of an antifuse memory cell circuit and an array circuit according to the present invention with reference to the accompanying drawings.
The antifuse memory cell circuit includes an antifuse device; a switch module coupled to the antifuse device; a selection module coupled to the switch module; a control module coupled to the antifuse device and the switch module, respectively; the control module is used for switching the on-off mode of the switch module according to the breakdown state of the anti-fuse device. The utility model discloses antifuse memory cell circuit can be based on the output of antifuse device (i.e., antifuse memory cell's memory state) controls opening and closing of switch module to the purpose of saving the consumption is realized. Fig. 1 is a circuit diagram of an embodiment of an antifuse memory cell circuit according to the present invention. Referring to fig. 1, the antifuse memory cell circuit of the present invention includes an antifuse device C00, a switch module, a selection module, and a control module 12.
The antifuse device C00 has a first terminal and a second terminal. During programming, if the antifuse device C00 breaks down, the on-resistance is approximately 0 ohms; if the antifuse device C00 is not broken down, the on-resistance is approximately infinite ohms. That is, the antifuse device C00 is non-conductive when inactive and becomes conductive when activated (broken down), forming an electrical connection that selectively allows two devices or chips that would otherwise be electrically isolated to be electrically connected and can provide different resistance values for logic operations.
The switch module is coupled to the antifuse device C00. The switch module includes a first switch unit MP2 and a second switch unit MN1, the first switch unit MP2 and the second switch unit MN1 each having a first terminal, a second terminal and a control terminal. In this embodiment, the first switch unit MP2 is a P-type transistor, and the second switch unit MN1 is an N-type transistor.
The control terminals of the first and second switch units MP2 and MN1 are coupled to the control module 12. Specifically, a control terminal of the first switch unit MP2 is coupled to a first control signal CTRL _ a of the control module 12, and a control terminal of the second switch unit MN1 is coupled to a second control signal CTRL _ B of the control module 12.
The second terminals of the first and second switch units MP2 and MN1 are coupled to a selection module. Specifically, a second terminal of the first switch unit MP2 is coupled to the word line select unit MP1 of the select block, and a second terminal of the second switch unit MN1 is coupled to the bit line select unit MN2 of the select block.
A first terminal of the first switch unit MP2 is coupled to a first terminal of the antifuse device C00, and a first terminal of the second switch unit MN1 is coupled to a second terminal of the antifuse device C00.
After the antifuse memory cell sensing circuit senses the programming result, the pull-up of the antifuse memory cell is turned off if the antifuse device C00 breaks down, and is maintained if the antifuse device C00 does not break down. After the antifuse memory cell sensing circuit senses the programming result, if the antifuse device C00 breaks down, the pull-down of the antifuse memory cell is maintained, and if the antifuse device C00 does not break down, the pull-down of the antifuse memory cell is turned off.
Further, the switching module also includes a third switching unit MN0, the third switching unit MN0 having a first terminal, a second terminal, and a control terminal. A first terminal of the third switching unit MN0 is coupled to the first terminal of the antifuse device C00, a second terminal of the third switching unit MN0 is coupled to a ground signal, and a control terminal of the third switching unit MN0 is coupled to the third control signal CTRL _ a of the control module 12. In this embodiment, the third switching unit MN0 is an N-type transistor. The third switching unit MN0 is used to pull the one-stage output node OUTA of the antifuse memory cell to ground when the one-time programmable memory is not in operation, and also to define an initial operating state of the one-stage output node OUTA when the one-time programmable memory is in operation.
The select module includes a bit line select cell MN2 and a word line select cell MP1, the bit line select cell MN2 and the word line select cell MP1 each having a first terminal, a second terminal, and a control terminal. The bit line selection unit MN2 can be an N-type transistor, and the word line selection unit MP1 can be a P-type transistor.
The control terminal of the bit line selection unit MN2 is coupled to a bit line BL00, the first terminal of the bit line selection unit MN2 is coupled to the second terminal of the second switch unit MN1, and the second terminal of the bit line selection unit MN2 is coupled to a ground signal. The control terminal of the word line select unit MP1 is coupled to the word line WL00, the first terminal of the word line select unit MP1 is coupled to the second terminal of the first switch unit MP2, and the second terminal of the word line select unit MP1 is coupled to a power signal.
During programming, the bit line selection unit MN2 can control the on/off of the antifuse memory cell, and plays a role in protecting the antifuse device C00.
Further, the antifuse memory cell circuit further includes a current providing module MP0 having a first terminal coupled to a power signal and a second terminal coupled to a second terminal of the word line selecting unit MP 1. That is, the second terminal of the word line select unit MP1 is coupled to a power signal through the current providing module MP 0. The current supply module MP0 acts as a mirror current source, and the current supply module MP0 can control the amount of current flowing through the antifuse device C00 during programming, and the current supply module MP0 can control the pull-up capability of the antifuse memory cell during normal operation. The current supply module MP0 may be a P-type transistor.
The control module 12 includes a control unit 121, an amplifying unit 122, and a delay unit 123.
The control unit 121 is configured to receive a signal and output a control signal. Specifically, the control unit 121 has an input terminal coupled to the first terminal of the antifuse device C00 through the amplifying unit 122, a write enable signal En _ W, a read enable signal En _ R, and a read enable delay signal En _ R _ DLY, and an output terminal coupled to the switch module, and outputs a first control signal CTRL _ a, a second control signal CTRL _ B, and a third control signal CTRL _ C. The first control signal CTRL _ a is coupled to a control terminal of the first switching unit MP2, the second control signal CTRL _ B is coupled to a control terminal of the second switching unit MN1, and the third control signal CTRL _ C is coupled to a control terminal of the third switching unit MN 0.
The amplifying unit 122 has an input terminal coupled to the primary output node OUTA of the antifuse device C00, and an output terminal for amplifying the state of the primary output node OUTA of the antifuse device C00 to the state of the secondary output node OUTB, so that a logic error in a subsequent digital circuit can be avoided, and reliability of the readout circuit can be improved. The output terminal is coupled to the input terminal of the control unit 121, so as to input the secondary output OUTB of the antifuse device C00 to the input terminal of the control unit 121. In this embodiment, the amplifying unit 122 is composed of two inverters.
The delay unit 123 is used for generating the read enable delay signal En _ R _ DLY. Specifically, the read enable signal En _ R is coupled to the delay unit 123 in addition to the control unit 121, and the delay unit 123 delays the read enable signal En _ R and outputs the delayed read enable signal En _ R _ DLY. The delay unit 123 may be formed by connecting an even number of inverters in series, or the delay unit 123 is an RC delay circuit. The delay time Td is a minimum of 4 inverter delays during which the amplification unit 122 can complete the amplification of OUTA.
The utility model also provides a concrete implementation mode of the reading and writing method of above-mentioned antifuse memory cell circuit. Please refer to table 1:
| EN_W | EN_R | EN_R_DLY | OUTA | OUTB | | CTRL_B | CTRL_C | |
| 1 | 0 | 0 | X | X | 0 | 1 | 0 | |
| 0 | 0 | 0 | | X | 1 | 0 | 1 | |
| 0 | 1 | 0 | X | X | 0 | 1 | 0 | |
| 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
TABLE 1
The programming method is that the control module controls the switch module to be opened so as to write the anti-fuse device. Examples are as follows:
when the write enable signal EN _ W is equal to 1 and the read enable signal EN _ R is equal to 0, the first control signal CTRL _ a is equal to 0 (the first switching tube MP2 is turned on), the second control signal CTRL _ B is equal to 1 (the second switching tube MN1 is turned on), the third control signal CTRL _ C is equal to 0 (the third switching tube MN0 is turned off), and VDD is a high voltage; if the word line WL00 is "0" and the bit line BL00 is "1", the antifuse device C00 is broken down with an on-resistance of approximately 0 ohms; otherwise, antifuse device C00 is not broken down and has an on-resistance of approximately infinite ohms.
The standby method is that the control module controls the switch module to be closed so as to reduce the power consumption of the anti-fuse device. Examples are as follows:
when the write enable signal EN _ W is equal to 0 and the read enable signal EN _ R is equal to 0, the first control signal CTRL _ a is equal to 1 (the first switching tube MP2 is turned off), the second control signal CTRL _ B is equal to 0 (the second switching tube MN1 is turned off), the third control signal CTRL _ C is equal to 1 (the third switching tube MN0 is turned on), VDD is a normal voltage, the static power consumption of the antifuse memory cell is approximately 0 at this time, and OUTB outputs "0" by default.
The method during normal operation is that the control module controls the switch module to be opened so as to read the anti-fuse device. Examples are as follows:
1. when the word line WL00 is equal to 0, the bit line BL00 is equal to I, VDD is a normal voltage, the write enable signal EN _ W is equal to 0, the read enable signal EN _ R is equal to 0, and the read enable delay signal EN _ R _ DLY is equal to 0, the first control signal CTRL _ a is equal to 1 (the first switching tube MP2 is turned off), the second control signal CTRL _ B is equal to 0 (the second switching tube MN1 is turned off), and the third control signal CTRL _ C is equal to 1 (the third switching tube MN0 is turned on). 2. When the word line WL00 is equal to 0, the bit line BL00 is equal to 1, VDD is a normal voltage, the write enable signal EN _ W is equal to 0, the read enable signal EN _ R is equal to 1, and the read enable delay signal EN _ R _ DLY is equal to 0, then the first control signal CTRL _ a is equal to 0 (the first switching tube MP2 is open), the second control signal CTRL _ B is equal to 1 (the second switching tube MN1 is open), and the third control signal CTRL _ C is equal to 0 (the third switching tube MN0 is closed); if the antifuse device C00 is not broken down, the on-resistance of the antifuse device C00 is approximately infinite ohm, and the OUTA is pulled up to "1" by the first P-type transistor MP0, the first selection transistor MP1 and the first switch transistor MP 2; if the antifuse device C00 breaks down, the on-resistance of the antifuse device C00 is approximately 0 ohm, and the OUTA is maintained at "0" by the second switching transistor MN1 and the second selection transistor MN 2. 3. When the word line WL00 is equal to 0, the bit line BL00 is equal to 1, VDD is a normal voltage, the write enable signal EN _ W is equal to 0, the read enable signal EN _ R is equal to 1, the read enable delay signal EN _ R _ DLY is equal to 1, if OUTB is equal to OUTA, the first control signal CTRL _ a is equal to 0 (the first switching tube MP2 is open), the second control signal CTRL _ B is equal to 0 (the second switching tube MN1 is closed), and the third control signal CTRL _ C is equal to 0 (the third switching tube MN0 is closed); if OUTB equals 0, the first control signal CTRL _ a equals 1 (the first switching tube MP2 is closed), the second control signal CTRL _ B equals 1 (the second switching tube MN1 is open), and the third control signal CTRL _ C equals 0 (the third switching tube MN0 is closed).
The anti-fuse memory cell circuit of the utility model is a pure combinational circuit, compared with a time sequence circuit, after Td delay, all the channels are closed, and the whole circuit has no logic action, the static power consumption is lower, and the power consumption is approximately 0; and the utility model discloses antifuse memory cell circuit has constituted two positive feedback loops through the design of switch and logical operation module in essence for read-out circuit can more reliable read out "0" or "1"; and simultaneously, the utility model discloses antifuse memory cell circuit can save complicated sequential control part, and the output OUTA OUTB of reading out the circuit even can need not latch, directly as the code output of antifuse.
Further, in order to realize the utility model discloses anti-fuse memory cell circuit's control, LOGIC operation unit LOGIC circuit inner structure as follows:
CTRL_A＝(！EN_W)&&((！EN_R)&&(！EN_R_DLY)||EN_R&&EN_R_DLY&&(！OUTB))
CTRL_B＝EN_W&&(！EN_R)&&(！EN_R_DLY)||(！EN_W)&&EN_R&&((！EN_R_DLY)||EN_R_DLY&&(！OUTB))
CTRL_C＝(！EN_W)&&(！EN_R)
the utility model also provides a first embodiment of antifuse memory array circuit. FIG. 2 is a circuit diagram of a first embodiment of an antifuse memory array circuit. Referring to fig. 2, the antifuse memory array circuit includes a plurality of antifuse memory cell circuits. The structure of the anti-fuse memory cell circuit is the same as that of the anti-fuse memory cell circuit. In this embodiment, the control modules of the antifuse memory unit are integrated into an overall control module. The input terminal of the general control module is coupled to the write enable signal EN _ W, the read enable signal EN _ R, the read enable delay signal EN _ R _ DLY, and the first terminal of each antifuse device C00. That is, the antifuse memory cell circuit shares the write enable signal EN _ W, the read enable signal EN _ R, and the read enable delay signal EN _ R _ DLY to reduce the number of input lines, thereby reducing the area. Further, the output terminal of the general control module outputs a control signal, and the control signal is coupled to the third switching unit MN0 of the antifuse memory cell, that is, the antifuse memory cell circuits share the third control signal CTRL _ C of the control unit, so as to reduce the number of control lines and thus reduce the area. For logic operation circuits, the internal pure combinational logic can continue to be optimized to reduce the number of logic gates, thereby reducing area.
The utility model discloses still provide a second embodiment of antifuse memory array circuit. FIG. 3 is a circuit diagram of a second embodiment of an antifuse memory array circuit. Referring to fig. 3, the second embodiment is different from the first embodiment in that at least a portion of the antifuse memory cell circuits share a current supply block MP 0. For example, all of the antifuse memory cell circuits share one current supply block MP 0. The current supply block MP0 functions as a current mirror to supply and limit current, and the anti-fuse memory cell circuit shares the current supply block MP0 to reduce the number of transistors and thus area. Further, in the present embodiment, at least a portion of the antifuse memory cell circuits share the word line selection unit MP1, for example, all of the antifuse memory cell circuits share the word line selection unit MP 1. The word line selection unit MP1 is a word line controlled selection transistor, the antifuse memory cell circuit sharing the word line selection unit MP1 can reduce the number of transistors, thereby reducing the area.
The present invention also provides a third embodiment of an antifuse memory array circuit. FIG. 4 is a circuit diagram of a third embodiment of an antifuse memory array circuit. Referring to fig. 4, the third embodiment is different from the second embodiment in that the amplifying unit 122 is composed of two inverters, and the amplifying unit 122 can be combined with the circuit of the control unit 121 to reduce the number of logic gates, thereby reducing the area. That is, the function of the amplifying unit 122 is realized by the control unit 121.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (14)
1. An antifuse memory cell circuit, comprising:
an anti-fuse device;
a switch module coupled to the antifuse device;
a selection module coupled to the switch module;
a control module coupled to the antifuse device and the switch module, respectively;
the control module is used for switching the on-off mode of the switch module according to the breakdown state of the anti-fuse device.
2. The antifuse memory cell circuit of claim 1, wherein the antifuse device has a first terminal and a second terminal,
the switch module comprises a first switch unit and a second switch unit, wherein the first switch unit and the second switch unit are respectively provided with a first end, a second end and a control end, the control ends are respectively coupled to the control module, the second ends are respectively coupled to the selection module, the first end of the first switch unit is coupled to the first end of the anti-fuse device, and the first end of the second switch unit is coupled to the second end of the anti-fuse device.
3. The antifuse memory cell circuit of claim 2, wherein the switch block further comprises a third switch unit having a first terminal coupled to the first terminal of the antifuse device, a second terminal coupled to a ground signal, and a control terminal coupled to the control block.
4. The antifuse memory cell circuit of claim 2, wherein the selection block comprises a bit line selection cell and a word line selection cell, the bit line selection cell and the word line selection cell each having a first terminal, a second terminal, and a control terminal, the control terminal of the bit line selection cell being coupled to a bit line, the first terminal of the bit line selection cell being coupled to the second terminal of the second switch cell, the second terminal of the bit line selection cell being coupled to a ground signal, the control terminal of the word line selection cell being coupled to a word line, the first terminal of the word line selection cell being coupled to the second terminal of the first switch cell, the second terminal of the word line selection cell being coupled to a power signal.
5. The antifuse memory cell circuit of claim 4, further comprising a current supply block having a first terminal coupled to a power signal and a second terminal coupled to the second terminal of the word line select unit.
6. The antifuse memory cell circuit of claim 1, wherein the control block comprises a control unit having an input coupled to the first terminal of the antifuse device, a write enable signal, a read enable delay signal, and an output coupled to the switch block.
7. The antifuse memory cell circuit of claim 6, wherein the control block further comprises an amplification unit having an input coupled to the first terminal of the antifuse device and an output coupled to the input of the control unit, the amplification unit to amplify the signal at the first terminal of the antifuse device.
8. The antifuse memory cell circuit of claim 6, wherein the control block further comprises a delay unit having an input and an output, the read enable signal further coupled to the input of the delay unit, the output of the delay unit coupled to the control unit, the delay unit to delay the read enable signal.
9. An antifuse memory array circuit comprising a plurality of antifuse memory cell circuits according to any one of claims 1 to 8.
10. The antifuse memory array circuit of claim 9, wherein the control blocks of the antifuse memory cells are integrated as a global control block.
11. The antifuse memory array circuit of claim 10, wherein an input of the global control block is coupled to a write enable signal, a read enable delay signal, and a first terminal of each of the antifuse devices.
12. The antifuse memory array circuit of claim 10, wherein an output of the global control block outputs a control signal coupled to the third switching unit of the antifuse memory cell.
13. The antifuse memory array circuit of claim 9, wherein at least a portion of the antifuse memory cell circuits share a current supply block.
14. The antifuse memory array circuit of claim 9, wherein at least a portion of the antifuse memory cell circuits share a word line select unit.
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| CN201921654359.5U CN210271793U (en) | 2019-09-29 | 2019-09-29 | Anti-fuse memory cell circuit and array circuit |
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| CN201921654359.5U CN210271793U (en) | 2019-09-29 | 2019-09-29 | Anti-fuse memory cell circuit and array circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021056958A1 (en) * | 2019-09-29 | 2021-04-01 | 长鑫存储技术有限公司 | Anti-fuse storage unit circuit and array circuit, and read/write method therefor |
| CN113948142A (en) * | 2020-07-16 | 2022-01-18 | 长鑫存储技术有限公司 | Anti-fuse memory cell state detection circuit and memory |
| WO2023133967A1 (en) * | 2022-01-17 | 2023-07-20 | 长鑫存储技术有限公司 | Antifuse memory |
-
2019
- 2019-09-29 CN CN201921654359.5U patent/CN210271793U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021056958A1 (en) * | 2019-09-29 | 2021-04-01 | 长鑫存储技术有限公司 | Anti-fuse storage unit circuit and array circuit, and read/write method therefor |
| US11887682B2 (en) | 2019-09-29 | 2024-01-30 | Changxin Memory Technologies, Inc. | Anti-fuse memory cell circuit, array circuit and reading and writing method thereof |
| CN113948142A (en) * | 2020-07-16 | 2022-01-18 | 长鑫存储技术有限公司 | Anti-fuse memory cell state detection circuit and memory |
| CN113948142B (en) * | 2020-07-16 | 2023-09-12 | 长鑫存储技术有限公司 | Antifuse memory cell state detection circuit and memory |
| WO2023133967A1 (en) * | 2022-01-17 | 2023-07-20 | 长鑫存储技术有限公司 | Antifuse memory |
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