CN115938436B - Memory circuit and memory array - Google Patents
Memory circuit and memory array Download PDFInfo
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- CN115938436B CN115938436B CN202210225369.7A CN202210225369A CN115938436B CN 115938436 B CN115938436 B CN 115938436B CN 202210225369 A CN202210225369 A CN 202210225369A CN 115938436 B CN115938436 B CN 115938436B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a memory circuit and a memory array, which relate to the technical field of semiconductors and are used for avoiding the condition of erroneous writing to a certain extent when a user writes data into the memory circuit, so that the reliability of the memory circuit is improved. The memory circuit includes an access unit circuit and a first control circuit. The input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, and the power end of the first control circuit is electrically connected with the fuse signal end. The first control circuit is used for supplying power to the access unit circuit when the m bit signals meet a first preset condition and the fuse signals meet a second preset condition. Wherein m is a positive integer. The data storage end of the access unit circuit is electrically connected with the fuse signal end, and when the fuse signal meets a second preset condition, the access unit circuit is used for storing the data written by the write data end. The memory array comprises the memory circuit provided by the technical scheme.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a memory circuit and a memory array.
Background
An electrically programmable Fuse (Electrically programmable Fuse, abbreviated as eFuse) is a one-time programmable memory developed by electromigration, fuse programming is performed based on the electromigration principle, and the programmed information can be permanently stored.
At present, eFuse memory circuits are widely applied to the fields of aviation, mobile equipment, routers and the like, and higher requirements are also put on the reliability of the eFuse memory circuits. In some conventional eFuse memory circuits, there is still a case where a user writes data by mistake, and the reliability of the eFuse memory circuit cannot be improved.
Disclosure of Invention
The invention aims to provide a memory circuit and a memory array, so that when a user writes data into the memory circuit, the situation of erroneous writing is avoided to a certain extent, and the reliability of the memory circuit is improved.
In a first aspect, the present invention provides a memory circuit comprising: an access unit circuit and a first control circuit. The input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, and the power end of the first control circuit is electrically connected with the fuse signal end. The first control circuit is used for supplying power to the access unit circuit when the m bit signals meet a first preset condition and the fuse signals meet a second preset condition. Wherein m is a positive integer. The data storage end of the access unit circuit is electrically connected with the fuse signal end, and when the fuse signal meets a second preset condition, the access unit circuit is used for storing the data written by the write data end.
Compared with the prior art, in the memory circuit provided by the invention, the input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, and the power end of the first control circuit is electrically connected with the fuse signal end. When m bit signals input by m bit signal ends meet a first preset condition, and a fuse signal input by a fuse signal end meets a second preset condition, the first control circuit can provide a required power supply voltage for the access unit circuit, and the access circuit can normally write data. Based on the above, the invention can control the m bit signals and the fuse signals so that the first control circuit can supply power to the access unit circuit, and the access unit circuit can write data normally, therefore, the invention can avoid the situation that a user writes data by mistake. Meanwhile, the data storage end of the access unit circuit is electrically connected with the fuse signal end, and when the fuse signal meets a second preset condition, the access unit circuit can store the data written by the write data end under the action of the fuse signal, so that the reliability of the storage circuit is further improved. Therefore, the storage circuit provided by the invention can store the data written by the write data terminal only when m bit signals meet the first preset condition and the fuse signals meet the second preset condition. Therefore, the memory circuit provided by the invention can avoid the situation that a user writes data by mistake to a certain extent, thereby improving the reliability of the memory circuit.
In a second aspect, the present invention further provides a memory array, including a plurality of memory circuits according to the first aspect, where the plurality of memory circuits are arranged in an array. The write data control end of each memory circuit is electrically connected with other write data control ends of the row, and the read data control end of each memory circuit is electrically connected with other read data control ends of the row. The write data end of each memory circuit is electrically connected with other write data ends of the column, and the read data end of each memory circuit is electrically connected with other read data ends of the column.
Compared with the prior art, the beneficial effects of the memory array provided by the invention are the same as those of the memory circuit described in the first aspect, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a schematic diagram of a memory circuit according to an embodiment of the present invention;
fig. 2 to fig. 4 are schematic structural diagrams of a first control sub-circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an access unit circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a sense amplifier according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a second control circuit according to an embodiment of the present invention;
fig. 8 to 10 are schematic structural diagrams of a second control sub-circuit according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a memory array according to an embodiment of the present invention.
Reference numerals:
1-a memory circuit, 11-a first control circuit,
12-access unit circuits, 111-first control sub-circuits,
112-first voltage generation subcircuit, 1111-multiple bit enable control module,
1111 a-first nor gate, 1111 b-and gate,
1112-first nand gate, 1113-not gate,
121-write sub-circuit, 1211-second nor gate,
122-fuses, 123-read sub-circuits,
13-second control circuit, 14-sense amplifier,
131-a second control sub-circuit, 132-a second voltage generation sub-circuit,
1311-second nand gate, 2-memory array.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
An electrically programmable Fuse (Electrically programmable Fuse, abbreviated as eFuse) is a one-time programmable memory developed by electromigration, fuse programming is performed based on the electromigration principle, and the programmed information can be permanently stored. eFuse circuits can not only be used as memory circuits to store important information in a chip, but also can be used as redundant circuits to improve the reliability of the chip.
At present, eFuse memory circuits are widely applied to the fields of aviation, mobile equipment, routers and the like, and higher requirements are also put on the reliability of the eFuse memory circuits. In some conventional eFuse memory circuits, there is still a case where a user writes data by mistake, and the reliability of the eFuse memory circuit cannot be improved.
In view of the above problems, an embodiment of the present invention provides a memory circuit 1. As shown in fig. 1, a memory circuit 1 provided in an embodiment of the present invention includes: the access unit circuit 12 and the first control circuit 11. The input terminal of the first control circuit 11 is electrically connected to the m bit signal input terminals, the output terminal is electrically connected to the power terminal of the access unit circuit 12, and the power terminal of the first control circuit 11 is electrically connected to the fuse signal terminal FS. The first control circuit 11 is configured to supply power to the access unit circuit 12 in a case where the m bit signals satisfy a first preset condition and the fuse signal satisfies a second preset condition. Wherein m is a positive integer. The data storage terminal of the access unit circuit 12 is electrically connected to the fuse signal terminal FS, and when the fuse signal meets a second preset condition, the access unit circuit 12 is configured to store the data written by the write data terminal.
As can be seen from the schematic structural diagram of the memory circuit 1 provided by the embodiment of the present invention, in the memory circuit 1 provided by the embodiment of the present invention, the input end of the first control circuit 11 is electrically connected to the m bit signal input ends correspondingly, the output end is electrically connected to the power supply end of the access unit circuit 12, and the power supply end of the first control circuit 11 is electrically connected to the fuse signal end FS. When the m bit signals input by the m bit signal terminals satisfy the first preset condition and the fuse signal input by the fuse signal terminal FS satisfies the second preset condition, the first control circuit 11 can provide the required power supply voltage vdd_cell to the access unit circuit 12, and the access circuit 1 can write data normally. Based on this, the embodiment of the present invention can control the m bit signals and the fuse signal so that the first control circuit 11 can supply power to the access unit circuit 12, and the access unit circuit 12 can write data normally, so that the embodiment of the present invention can avoid the situation that the user writes data by mistake. Meanwhile, the data storage end of the access unit circuit 12 is electrically connected with the fuse signal end FS, and when the fuse signal meets the second preset condition, the access unit circuit 12 can store the data written in the write data end under the action of the fuse signal, so that the reliability of the storage circuit 1 is further improved. Therefore, the memory circuit 1 provided in the embodiment of the present invention can only store the data written by the write data terminal when the m bit signals satisfy the first preset condition and the fuse signals satisfy the second preset condition. Therefore, the memory circuit 1 provided by the embodiment of the invention can avoid the situation that the user writes data by mistake to a certain extent, thereby improving the reliability of the memory circuit 1.
In practical applications. In order to reduce the probability of data wrongly written by a user to the greatest extent, preferably, m is more than or equal to 4. When m=4, the probability of being able to write data normally is only 1/16, and the probability of being unable to write data is 15/16, so that the situation of writing data by a user by mistake can be avoided to the greatest extent.
In one possible implementation, as shown in fig. 1, the first control circuit 11 includes a first control sub-circuit 111 and a first voltage generation sub-circuit 112. An input terminal of the first control sub-circuit 111 and m bit signal input terminals I 1 、I 2 、I 3 、I 4 The output end of the first control sub-circuit 111 is electrically connected to the control end of the first voltage generation sub-circuit 112, and is used for controlling the on-off of the first voltage generation sub-circuit 112 under the action of m bit signals. The power supply terminal of the first voltage generation sub-circuit 112 is electrically connected to the fuse signal terminal FS, and the output terminal of the first voltage generation sub-circuit 112 is electrically connected to the power supply terminal of the access unit circuit 12 for supplying power to the access unit circuit 12.
In a specific implementation process, by controlling the input of the m bit signals so as to meet the first preset condition, the output signal of the first control sub-circuit 111 controls the first voltage generation sub-circuit 112 to be turned on under the action of the m bit signals. In the case of conduction of the first voltage generation sub-circuit 112, the first voltage generation sub-circuit 112 supplies power to the access unit circuit 12 when the fuse signal satisfies the second preset condition. Based on this, when the m bit signals do not satisfy the first preset condition, the output signal of the first control sub-circuit 111 cannot turn on the first voltage generation sub-circuit 112, and at this time, the first voltage generation sub-circuit 112 cannot supply power to the access unit circuit 12, so as to avoid the user from writing data by mistake. In addition, even if the first voltage generating sub-circuit 112 is turned on under the action of the m bit signals, that is, if the m bit signals satisfy the first preset condition, but the fuse signal does not satisfy the second preset condition, the first voltage generating sub-circuit 112 cannot generate the power supply voltage vdd_cell required by the access unit circuit 12, and the access unit circuit 12 cannot write data without power supply, so that the situation that the user writes data by mistake is avoided.
Referring to fig. 1 to 4, in some embodiments, the first control sub-circuit 111 includes at least one multi-bit enable control module 1111, a first nand gate 1112, and a nor gate 1113. An input of the at least one multi-bit enable control module 1111 is electrically connected to the m bit signal inputs; an output of the at least one multi-bit enable control module 1111 is coupled to an input of a first nand gate 1112, and an output of the first nand gate 1112 is electrically coupled to an input of a nor gate 1113.
The first voltage generating sub-circuit 112 includes a first transistor T1, a second transistor T2, a first resistor R1, and a second resistor R2. The control end of the first transistor T1 is electrically connected to the output end of the nand gate 1113, the first electrode of the first transistor T1 is electrically connected to the fuse signal end FS through the first resistor R1, the first electrode of the first transistor T1 is also electrically connected to the control end of the second transistor T2, and the second electrode of the first transistor T1 is grounded. The first electrode of the second transistor T2 is electrically connected to the fuse signal terminal FS, the second electrode of the second transistor T2 is grounded through the second resistor R2, and the second electrode of the second transistor T2 is also electrically connected to the power supply terminal of the access unit circuit 12.
It is understood that the first transistor T1 is an N-type transistor, i.e. the control terminal is turned on when it is at a high level (logic "1"). The second transistor T2 is a P-type transistor, i.e. turned on when the control terminal is low (logic "0"). The second preset condition is that the fuse signal terminal FS is at a high level (logic "1").
In a specific implementation, when the first transistor T1 needs to be turned on, the level of the control terminal of the first transistor T1 must be made to be high (logic "1"). When the first transistor T1 is turned on, the first electrode is directly turned on with the second electrode, and the first electrode is also low level (logic "0") because the second electrode is directly grounded. Since the first resistor R1 is also present between the first electrode of the first transistor T1 and the fuse signal terminal FS, the fuse signal terminal FS can be prevented from being directly connected to the ground terminal and being set to a low level (logic "0"). At this time, the first electrode of the first transistor T1 outputs a low level (logic "0") signal to the control terminal of the second transistor T2, thereby turning on the second transistor T2. When the signal of the fuse signal terminal FS is at a low level (logic "0"), the second transistor T2 is turned on, and thus the voltage signal is not generated, i.e., the power supply voltage vdd_cell required by the access unit circuit 12 cannot be generated. Only when the fuse signal terminal FS is at a high level, the second electrode of the second transistor T2 generates the power supply voltage vdd_cell required for the access unit circuit 12. Similarly, the second resistor R2 is set to a low level (logic "0") in order to avoid the second electrode of the second transistor T2 being directly grounded.
Further, as shown in FIGS. 2-4, the multi-bit enable control module 1111 in the above embodiment includes at least one first NOR gate 1111a and at least one AND gate 1111b, and m is equal to or greater than 4. The input of each first nor gate 1111a is electrically connected to at least two bit signal inputs, respectively, and the output of each first nor gate 1111a is electrically connected to a first input of a first nand gate 1112. The input of each and gate 1111b is electrically connected to at least two bit signal inputs, respectively, and the output of each and gate 1111b is connected to the second input of the first nand gate 1112.
In practical applications, when the input terminal of the multi-bit enable control module 1111 is connected to the bit signal input terminal, the input terminals of the first nor gate 1111a and the and gate 1111b may be connected to the bit signal input terminal in a staggered manner, i.e. the bit signal input terminal ordered to be odd is connected to the input terminal of the first nor gate 1111a, and the bit signal input terminal ordered to be even is connected to the input terminal of the and gate 1111 b. In this way, the m bit signals can meet the first preset condition only in the case of the staggered arrangement of 0 and 1. That is, when m=4, the m bit signals are necessarily "0101", which avoids the situation that the m bit signals are "0011" due to noise interference or the like, and can further reduce the probability of erroneous writing and improve the reliability of the memory circuit 1. After the connection order is changed, the even-ordered bit signal input terminal is connected to the input terminal of the first nor gate 1111a, the odd-ordered bit signal input terminal is connected to the input terminal of the and gate 1111b, and the order of the m bit signals needs to be adjusted accordingly, and when m=4, the m bit signals are "1010". The embodiment of the present invention is not particularly limited in this regard.
It is understood that nand gate, nor gate, and not gate are all one basic logic circuit in digital circuits.
The NAND gate has at least two inputs and an output, and when all inputs are high (logic "1"), the output is low (logic "0"); when at least one of the inputs is low (logic "0"), the output is high (logic "1").
The nor gate has at least two input terminals and an output terminal, and when any one of the input terminals is high level (logic "1"), the output is low level (logic "0"); when all inputs are low (logic "0"), the output is high (logic "1").
The AND gate has at least two inputs and an output, the circuit output being high (logic "1") only when all inputs are high (logic "1"), and low (logic "0") otherwise.
The NOT gate has an input terminal and an output terminal, and when the input terminal is high level (logic '1'), the output terminal is low level (logic '0'); conversely, when the input is low (logic "0"), the output is high (logic "1").
For example, as shown in fig. 2, when m=4, i.e. there are 4 bit signal inputs, then the first control sub-circuit 111 should have 4 inputs accordingly. The first control sub-circuit 111 may include 1 multi-bit enable control module 1111, a first nand gate 1112, and an nor gate 1113. Specifically, the first control sub-circuit 111 includes 1 first nor gate 1111a, 1 and gate 1111b, 1 first nand gate 1112, and 1 not gate 1113. A first input terminal of the first NOR gate 1111a and a first bit signal input terminal I 1 A second input terminal of the first NOR gate 1111a is electrically connected to the third bit signal input terminal I 3 The output of the first nor gate 1111a is electrically connected to a first input of the first nand gate 1112. AND gate 1111b firstAn input terminal and a second bit signal input terminal I 2 A second input terminal of the AND gate 1111b is electrically connected to a fourth bit signal input terminal I 4 An output of the and gate 1111b is electrically connected to a second input of the first nand gate 1112, and an output of the first nand gate 1112 is electrically connected to an input of the not gate 1113. At this time, the first preset condition is: the m bit signals are "0101", i.e. the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the fourth bit signal is "1". The output of the first nor gate 1111a is "0", the output of the and gate 1111b is "1", the output of the first nand gate 1112 is "0", and the output of the nor gate 1113 is "1", so that the first transistor T1 may be turned on.
For example, as shown in fig. 3, when m=6, i.e. there are 6 bit signal inputs, then the first control sub-circuit 111 should have 6 inputs accordingly. The first control sub-circuit 111 may include 1 multi-bit enable control module 1111, a first nand gate 1112, and an nor gate 1113. Specifically, the first control sub-circuit 111 includes 1 first nor gate 1111a, 1 and gate 1111b, 1 first nand gate 1112, and 1 not gate 1113. The first nor gate 1111a has 3 inputs, and the and gate 1111b has 3 inputs. A first input terminal of the first NOR gate 1111a and a first bit signal input terminal I 1 A second input terminal of the first NOR gate 1111a is electrically connected to the third bit signal input terminal I 3 A third input terminal of the first NOR gate 1111a is electrically connected to the fifth bit signal input terminal I 5 The output of the first nor gate 1111a is electrically connected to a first input of the first nand gate 1112. A first input terminal and a second bit signal input terminal I of the AND gate 1111b 2 A second input terminal of the AND gate 1111b is electrically connected to a fourth bit signal input terminal I 4 A third input terminal of the AND gate 1111b is electrically connected to the sixth bit signal input terminal I 6 An output of the and gate 1111b is electrically connected to a second input of the first nand gate 1112, and an output of the first nand gate 1112 is electrically connected to an input of the not gate 1113. At this time, the first preset condition is that the m bit signals are "010101", i.e., the first bit signal is" 0", the second bit signal is" 1", the third bit signal is" 0", the fourth bit signal is" 1", the fifth bit signal is" 0", and the sixth bit signal is" 1". The output of the first nor gate 1111a is "0", the output of the and gate 1111b is "1", the output of the first nand gate 1112 is "0", and the output of the nor gate 1113 is "1", so that the first transistor T1 may be turned on. It should be understood that when m=6 in the above embodiment, there may also be 1 first nor gate 1111a with 4 inputs and 1 and gate 1111b with 2 inputs in the multi-bit enable control module 1111, which is not particularly limited in the embodiment of the present invention.
For example, as shown in fig. 4, when m=8, i.e. there are 8 bit signal inputs, the first control sub-circuit 111 should have 8 inputs accordingly. The first control sub-circuit 111 may include 2 multi-bit enable control modules 1111, a first nand gate 1112, and an nor gate 1113. Specifically, the first control sub-circuit 111 includes 2 first nor gates 1111a, 2 and gates 1111b, 1 first nand gate 1112, and 1 not gate 1113. The 2 first NOR gates 1111a have 4 inputs respectively connected to the first bit signal input I 1 Third bit signal input terminal I 3 Fifth bit signal input terminal I 5 Seventh bit signal input terminal I 7 The output terminals of the 2 first nor gates 1111a are electrically connected to the first input terminal and the third input terminal of the first nand gate 1112, respectively. The 2 AND gates 1111b have 4 inputs respectively connected to the second bit signal input I 2 Fourth bit signal input terminal I 4 A sixth bit signal input terminal I 6 An eighth bit signal input terminal I 8 The outputs of the 2 and gates 1111b are electrically connected to the second input and the fourth input of the first nand gate 1112, respectively, and the output of the first nand gate 1112 is electrically connected to the input of the nor gate 1113. At this time, the first preset condition is that the m bit signals are "01010101", i.e. the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the fourth bit signalThe fifth bit signal is "0", the sixth bit signal is "1", the seventh bit signal is "0", and the eighth bit signal is "1". The outputs of the 2 first nor gates 1111a are all "1", the outputs of the 2 and gates 1111b are also all "1", the output of the first nand gate 1112 is "0", and the output of the nor gate 1113 is "1", so that the first transistor T1 can be turned on. It is understood that when m=8, the first control sub-circuit 111 may further include only 1 multi-bit enable control module 1111, the first nand gate 1112, and the nor gate 1113, and the first nor gate 1111a and the and gate 1111b in the multi-bit enable control module 1111 may have 4 inputs respectively; alternatively, the first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs and the and gate 1111b has 5 inputs; alternatively, 1 first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs, 1 and gate 1111b has 2 inputs, and the other and gate 1111b has 3 inputs. The embodiments of the present invention are not limited to this, as the number of possible permutations is not exhaustive.
It will be appreciated that in the above embodiment, the arrangement order of the m bit signals is only related to the type of digital logic gate connected thereto, i.e. if the order of the first nor gate 1111a and the and gate 1111b in the multi-bit enable control module 1111 is adjusted in actual operation, the first preset condition should be adjusted accordingly, which is not particularly limited in the embodiment of the present invention.
In one possible implementation, as shown in FIG. 5, the access unit circuit 12 includes a write sub-circuit 121, a read sub-circuit 123, and a fuse 122. The first end of the writing sub-circuit 121 is electrically connected to the writing data end BS and the writing data control end WL, respectively, the second end of the writing sub-circuit 121 is electrically connected to the first end of the reading sub-circuit 123, and the power end of the writing sub-circuit 121 is electrically connected to the output end of the first control circuit 11. The first terminal of the fuse 122 is electrically connected to the fuse signal terminal FS, and the second terminal of the fuse 122 is electrically connected to both the second terminal of the write sub-circuit 121 and the first terminal of the read sub-circuit 123. The control terminal of the read sub-circuit 123 is electrically connected to the read data control terminal RL, and the second terminal of the read sub-circuit 123 is electrically connected to the read data terminal BL.
In some embodiments, the write sub-circuit 121 includes a second nor gate 1211 and a third transistor T3. The first input terminal of the second nor gate 1211 is electrically connected to the write data terminal BS, the second input terminal of the second nor gate 1211 is electrically connected to the write data control terminal WL, the output terminal of the second nor gate 1211 is electrically connected to the control terminal of the third transistor T3, and the power terminal of the second nor gate 1211 is electrically connected to the output terminal of the first control circuit 11. The first electrode of the third transistor T3 is electrically connected to the fuse signal terminal FS through the fuse 122, and the second electrode of the third transistor T3 is grounded. The read sub-circuit 123 includes a fourth transistor T4. The control terminal of the fourth transistor T4 is electrically connected to the read data control terminal RL, the first electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3, and the second electrode of the fourth transistor T4 is electrically connected to the read data terminal BL.
It is understood that the third transistor T3 and the fourth transistor T4 are both N-type transistors, i.e. the control terminal is turned on when the control terminal is at a high level (logic "1").
In the write data period, the write data control terminal WL is low (logic "0"), i.e., the input signal of the second input terminal of the second nor gate 1211 is low (logic "0"). In the case where the second nor gate 1211 can normally write, it may be determined that the fuse signal still satisfies the above-described second preset condition at this time, i.e., the fuse signal terminal is at a high level (logic "1"). At this time, since the first terminal of the fuse 122 is electrically connected to the fuse signal terminal FS, the second terminal of the fuse 122 is connected to the first electrode of the third transistor T3, if the third transistor T3 is turned on, the fuse 122 is blown, and if the third transistor T3 is not turned on, the fuse 122 is not blown. I.e., whether the fuse 122 is blown or not is determined by whether the third transistor T3 is turned on or not. Since the control terminal of the third transistor T3 is electrically connected to the output terminal of the second nor gate 1211, when the input signal of the second input terminal of the second nor gate 1211 is at a low level (logic "0"), the input signal of the first input terminal of the second nor gate 1211 directly determines the output signal of the second nor gate 1211. Illustratively, when the input signal at the first input terminal of the second nor gate 1211 is low (logic "0"), the second nor gate 1211 outputs high (logic "1"), the third transistor T3 is turned on, and the fuse 122 is blown, the stored data is encoded with "1"; when the input signal of the first input terminal of the second nor gate 1211 is high (logic "1"), the second nor gate 1211 outputs low (logic "0"), the third transistor T3 is not turned on, the fuse 122 is not blown, and the stored data is encoded with "0".
In the read data phase, the read data control terminal RL is high (logic "1") to control the fourth transistor T4 to be turned on. And thus the writing of data is completed, the fuse signal terminal FS needs to be set to a low level (logic "0") in order to avoid erroneous writing. The first electrode of the fourth transistor T4 is directly electrically connected to the second electrode, i.e., the state of the fuse 122 can be read from the read data terminal BL. If the fuse 122 is blown, the impedance is infinite, and if the fuse 122 is not blown, the impedance is approximately infinitesimal.
In a possible implementation, as shown in fig. 6 and 7, the memory circuit 1 further comprises a sense amplifier 14 and a second control circuit 13. The input end of the second control circuit 13 is correspondingly and electrically connected with the input ends of the m bit signals, the output end of the second control circuit 13 is electrically connected with the power end of the sense amplifier 14, and the second control circuit 13 is used for supplying power to the sense amplifier 14 when the m bit signals meet the first preset condition. The input of the sense amplifier 14 is electrically connected to the output of the access unit circuit 12 for reading the data stored in the access unit circuit 12.
As shown in fig. 6, the input terminal of the sense amplifier 14 is electrically connected to the read data terminal BL. The sense amplifier 14 is used for detecting the fusing state of the fuse 122, and converting the fusing state into a corresponding voltage signal for outputting, so that the reading of the data stored in the memory circuit 1 can be completed. In fig. 6, CK is a clock signal terminal, vdd_amp is a power terminal of the sense amplifier 14, AP is a first node, AN is a second node, and VOP is AN output terminal of the sense amplifier 14. Since the sense amplifier 14 has a mirror symmetrical structure, the comparison result can be outputted through the output terminal VOP by comparing the impedance of the fuse 122 with the resistance value of the fourth resistor R4. If the fuse 122 is in the blown state, the impedance is infinite, i.e. greater than the resistance of the fourth resistor R4, the output terminal VOP will output a high level (logic "1"), i.e. the data stored in the access unit circuit 12 is read as code "1"; if the fuse 122 is in the connected state, the impedance is approximately infinitely small, i.e. smaller than the resistance of the fourth resistor R4, and the output terminal VOP outputs a low level (logic "0"), i.e. the data stored in the access unit circuit 12 is read as a code "0".
In some embodiments, as shown in fig. 7, the second control circuit 13 includes a second control sub-circuit 131 and a second voltage generation sub-circuit 132. The input end of the second control sub-circuit 131 is correspondingly and electrically connected with the m bit signal input ends, and the output end of the second control sub-circuit 131 is electrically connected with the control end of the second voltage generation sub-circuit 132 and is used for controlling the on-off of the second voltage generation sub-circuit 132 under the action of the m bit signals. The power supply terminal of the second voltage generation sub-circuit 132 is electrically connected to the common power supply terminal VDD, and the output terminal of the second voltage generation sub-circuit 132 is electrically connected to the power supply terminal of the sense amplifier 14 for supplying power to the sense amplifier 14.
In a specific implementation process, by controlling the input of the m bit signals so as to meet the first preset condition, the output signal of the second control sub-circuit 131 controls the second voltage generating sub-circuit 132 to be turned on under the action of the m bit signals. In the case of conduction of the second voltage generation sub-circuit 132, the second voltage generation sub-circuit 132 supplies power to the sense amplifier 14. Based on this, when the m bit signals do not satisfy the first preset condition, the output signal of the second control sub-circuit 131 cannot turn on the second voltage generation sub-circuit 132, and at this time, the second voltage generation sub-circuit 132 cannot generate the power supply voltage vdd_amp required by the sense amplifier 14, that is, the second voltage generation sub-circuit 132 cannot supply power to the sense amplifier 14, and the sense amplifier 14 cannot read data normally without power supply, so that the data security is ensured, and the reliability of the memory circuit 1 is further improved.
In some embodiments, as shown in fig. 7-10, the second control sub-circuit 131 includes at least one multi-bit enable control module 1111 and a second nand gate 1311. The second voltage generation sub-circuit 132 includes a fifth transistor T5 and a third resistor R3. The input terminal of the at least one multi-bit enable control module 1111 is electrically connected to the m bit signal input terminals, the output terminal of the at least one multi-bit enable control module 1111 is electrically connected to the input terminal of the second nand gate 1311, and the output terminal of the second nand gate 1311 is electrically connected to the control terminal of the fifth transistor T5. The first electrode of the fifth transistor T5 is electrically connected to the common power supply terminal VDD, the second electrode of the fifth transistor T5 is grounded through the third resistor R3, and the second electrode of the fifth transistor T5 is also electrically connected to the power supply terminal of the sense amplifier 14.
It is understood that the fifth transistor T5 is a P-type transistor, i.e., is turned on at a low level (logic "0").
In practice, when the fifth transistor T5 needs to be turned on, the level of the control terminal of the fifth transistor T5 must be made low (logic "0"). When the fifth transistor T5 is turned on, the first electrode and the second electrode are directly turned on, and the first electrode and the second electrode are both at a high level (logic "1") under the action of the common power supply terminal VDD because the first electrode is electrically connected to the common power supply terminal VDD and a third resistor R3 is further provided between the second electrode and the ground terminal. The second electrode of the fifth transistor T5 is electrically connected to the power supply terminal of the sense amplifier 14, so that the power supply voltage vdd_amp required for the sense amplifier 14 is generated.
For example, as shown in fig. 8, when m=4, i.e., there are 4 bit signal inputs, the second control sub-circuit 131 should have 4 inputs accordingly. The second control sub-circuit 131 may include 1 multi-bit enable control module 1111 and a second nand gate 1311. Specifically, the second control sub-circuit 131 includes 1 first nor gate 1111a, 1 and gate 1111b, and 1 second nand gate 1311. A first input terminal of the first NOR gate 1111a and a first bit signal input terminal I 1 A second input terminal of the first NOR gate 1111a is electrically connected to the third bit signal input terminal I 3 Electrically connected, the output of the first NOR gate 1111a is connected to the second NAND gate 1311The first input terminal is electrically connected. A first input terminal and a second bit signal input terminal I of the AND gate 1111b 2 A second input terminal of the AND gate 1111b is electrically connected to a fourth bit signal input terminal I 4 An output terminal of the and gate 1111b is electrically connected to a second input terminal of the second nand gate 1311, and an output terminal of the second nand gate 1311 is electrically connected to a control terminal of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "0101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the fourth bit signal is "1". The output of the first nor gate 1111a is "0", the output of the and gate 1111b is "1", and the output of the second nand gate 1311 is "0", so that the fifth transistor T5 may be turned on.
For example, as shown in fig. 9, when m=6, i.e., there are 6 bit signal inputs, the second control sub-circuit 131 should have 6 inputs accordingly. The second control sub-circuit 131 may include 1 multi-bit enable control module 1111 and a second nand gate 1311. Specifically, the second control sub-circuit 131 includes 1 first nor gate 1111a, 1 and gate 1111b, and 1 second nand gate 1311. The first nor gate 1111a has 3 inputs, and the and gate 1111b has 3 inputs. A first input terminal of the first NOR gate 1111a and a first bit signal input terminal I 1 A second input terminal of the first NOR gate 1111a is electrically connected to the third bit signal input terminal I 3 A third input terminal of the first NOR gate 1111a is electrically connected to the fifth bit signal input terminal I 5 The output of the first nor gate 1111a is electrically connected to a first input of the second nand gate 1311. A first input terminal and a second bit signal input terminal I of the AND gate 1111b 2 A second input terminal of the AND gate 1111b is electrically connected to a fourth bit signal input terminal I 4 A third input terminal of the AND gate 1111b is electrically connected to the sixth bit signal input terminal I 6 An output terminal of the and gate 1111b is electrically connected to a second input terminal of the second nand gate 1311, and an output terminal of the second nand gate 1311 is electrically connected to a control terminal of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "010101", That is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", the fourth bit signal is "1", the fifth bit signal is "0", and the sixth bit signal is "1". The output of the first nor gate 1111a is "0", the output of the and gate 1111b is "1", and the output of the second nand gate 1311 is "0", so that the fifth transistor T5 may be turned on. It should be understood that when m=6 in the above embodiment, there may also be 1 first nor gate 1111a with 4 inputs and 1 and gate 1111b with 2 inputs in the multi-bit enable control module 1111, which is not particularly limited in the embodiment of the present invention.
For example, as shown in fig. 10, when m=8, i.e., there are 8 bit signal inputs, the second control sub-circuit 131 should have 8 inputs accordingly. The second control sub-circuit 131 may include 2 multi-bit enable control modules 1111 and a second nand gate 1311. Specifically, the second control sub-circuit 131 includes 2 first nor gates 1111a, 2 and gates 1111b, and 1 second nand gate 1311. The 2 first NOR gates 1111a have 4 inputs respectively connected to the first bit signal input I 1 Third bit signal input terminal I 3 Fifth bit signal input terminal I 5 Seventh bit signal input terminal I 7 The output terminals of the 2 first nor gates 1111a are electrically connected to the first input terminal and the third input terminal of the second nand gate 1311, respectively. The 2 AND gates 1111b have 4 inputs respectively connected to the second bit signal input I 2 Fourth bit signal input terminal I 4 A sixth bit signal input terminal I 6 An eighth bit signal input terminal I 8 The output terminals of the 2 and gates 1111b are electrically connected to the second input terminal and the fourth input terminal of the second nand gate 1311, respectively, and the output terminal of the second nand gate 1311 is electrically connected to the control terminal of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "01010101", i.e. the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", the fourth bit signal is "1", the fifth bit signal is "0", and the sixth bit signal is "1"1", the seventh bit signal is "0", and the eighth bit signal is "1". The outputs of the 2 first nor gates 1111a are all "1", the outputs of the 2 and gates 1111b are also all "1", and the output of the second nand gate 1311 is then "0", so that the fifth transistor T5 may be turned on. It is understood that when m=8, the second control sub-circuit 131 may further include only 1 multi-bit enable control module 1111 and the second nand gate 1311, and the first nor gate 1111a and the and gate 1111b in the multi-bit enable control module 1111 may have 4 inputs respectively; alternatively, the first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs and the and gate 1111b has 5 inputs; alternatively, 1 first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs, 1 and gate 1111b has 2 inputs, and the other and gate 1111b has 3 inputs. The embodiments of the present invention are not limited to this, as the number of possible permutations is not exhaustive.
Referring to fig. 2 to 4 and fig. 8 to 10, it can be seen that the circuit structure of the first control sub-circuit 111 is similar to that of the second control sub-circuit 131, so that in practical application, in order to save cost, the first control sub-circuit 111 and the second control sub-circuit 131 may be combined into one, i.e. the input terminal of the not gate 1113 in the first control sub-circuit 111 is directly electrically connected to the control terminal of the fifth transistor T5.
As shown in fig. 11, an embodiment of the present invention further provides a memory array 2, which includes a plurality of memory circuits 1 according to the first aspect, and the plurality of memory circuits 1 are arranged in an array. The write data control terminal WL of each memory circuit 1 is electrically connected to the other write data control terminals WL of the row, and the read data control terminal RL of each memory circuit 1 is electrically connected to the other read data control terminals RL of the row. The write data terminal BS of each memory circuit 1 is electrically connected to the other write data terminals BS of the column, and the read data terminal BL of each memory circuit 1 is electrically connected to the other read data terminals BL of the column.
As shown in fig. 11, the memory array 2 is an 8×8 array, that is, each row has 8 memory circuits per column. The write data control terminals WL of 8 memory circuits 1 per row are commonly connected together, and the read data control terminals RL of 8 memory circuits 1 per row are also commonly connected together. The write data terminals BS of 8 memory circuits 1 per column are commonly connected together, and the read data terminals BL of 8 memory circuits 1 per column are also commonly connected together. The fuse signal terminals FS of the 64 memory circuits 1 are commonly connected, and the power supply terminals vdd_cell of the 64 memory circuits 1 are also commonly connected.
Compared with the prior art, the beneficial effects of the memory array 2 provided by the embodiment of the invention are the same as those of the memory circuit 1, and are not described herein.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A memory circuit, comprising: an access unit circuit and a first control circuit; the input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, the power end of the first control circuit is electrically connected with the fuse signal end, and the first control circuit is used for supplying power to the access unit circuit when the m bit signals meet a first preset condition and the fuse signal meets a second preset condition; wherein m is a positive integer;
the data storage end of the access unit circuit is electrically connected with the fuse signal end through a fuse wire of the access unit circuit, and when the fuse wire signal meets the second preset condition, the access unit circuit is used for storing the data written by the write data end;
the second preset condition is that the level of the fuse signal end is high.
2. The memory circuit of claim 1, wherein the first control circuit comprises a first control sub-circuit and a first voltage generation sub-circuit;
the input end of the first control sub-circuit is correspondingly and electrically connected with the m bit signal input ends, and the output end of the first control sub-circuit is electrically connected with the control end of the first voltage generation sub-circuit and is used for controlling the on-off of the first voltage generation sub-circuit under the action of the m bit signals;
The power supply end of the first voltage generation sub-circuit is electrically connected with the fuse signal end, and the output end of the first voltage generation sub-circuit is electrically connected with the power supply end of the access unit circuit and is used for supplying power to the access unit circuit.
3. The memory circuit of claim 2, wherein the first control sub-circuit comprises at least one multi-bit enable control module, a first nand gate, and a nor gate;
the input end of the at least one multi-bit enabling control module is electrically connected with m bit signal input ends; the output end of the at least one multi-bit enabling control module is correspondingly connected with the input end of the first NAND gate, and the output end of the first NAND gate is electrically connected with the input end of the NAND gate;
the first voltage generation sub-circuit comprises a first transistor, a second transistor, a first resistor and a second resistor; the control end of the first transistor is electrically connected with the output end of the NOT gate, the first electrode of the first transistor is electrically connected with the fuse signal end through the first resistor, the first electrode of the first transistor is also electrically connected with the control end of the second transistor, and the second electrode of the first transistor is grounded; the first electrode of the second transistor is electrically connected with the fuse signal end, the second electrode of the second transistor is grounded through the second resistor, and the second electrode of the second transistor is also electrically connected with the power end of the access unit circuit.
4. The memory circuit of claim 3, wherein the multi-bit enable control module comprises at least one first nor gate and at least one and gate, and m is ≡4, wherein:
the input end of each first NOR gate is electrically connected with at least two bit signal input ends respectively, and the output end of each first NOR gate is electrically connected with the first input end of the first NAND gate; the input end of each AND gate is respectively and electrically connected with at least two bit signal input ends, and the output end of each AND gate is connected with the second input end of the first NAND gate.
5. The memory circuit according to any one of claims 1 to 4, wherein the access unit circuit includes a write sub-circuit, a read sub-circuit, and a fuse;
the first end of the writing sub-circuit is electrically connected with the writing data end and the writing data control end respectively, the second end of the writing sub-circuit is electrically connected with the first end of the reading sub-circuit, and the power end of the writing sub-circuit is electrically connected with the output end of the first control circuit;
the first end of the fuse is electrically connected with the fuse signal end, and the second end of the fuse is electrically connected with the second end of the writing sub-circuit and the first end of the reading sub-circuit at the same time;
The control end of the reading sub-circuit is electrically connected with the reading data control end, and the second end of the reading sub-circuit is electrically connected with the reading data end.
6. The memory circuit of claim 5, wherein the write sub-circuit comprises a second nor gate and a third transistor; the first input end of the second nor gate is electrically connected with the write-in data end, the second input end of the second nor gate is electrically connected with the write-in data control end, the output end of the second nor gate is electrically connected with the control end of the third transistor, and the power end of the second nor gate is electrically connected with the output end of the first control circuit; the first electrode of the third transistor is electrically connected with the fuse signal end through the fuse, and the second electrode of the third transistor is grounded;
the read sub-circuit includes a fourth transistor; the control end of the fourth transistor is electrically connected with the read data control end, the first electrode of the fourth transistor is electrically connected with the first electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected with the read data end.
7. The memory circuit of claim 4, further comprising a sense amplifier and a second control circuit; wherein:
The input end of the second control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the second control circuit is electrically connected with the power end of the sensitive amplifier, and the second control circuit is used for supplying power to the sensitive amplifier under the condition that the m bit signals meet the first preset condition;
the input end of the sense amplifier is electrically connected with the output end of the access unit circuit and is used for reading the data stored in the access unit circuit.
8. The memory circuit of claim 7, wherein the second control circuit comprises a second control sub-circuit and a second voltage generation sub-circuit;
the input end of the second control sub-circuit is correspondingly and electrically connected with the m bit signal input ends, and the output end of the second control sub-circuit is electrically connected with the control end of the second voltage generation sub-circuit and is used for controlling the on-off of the second voltage generation sub-circuit under the action of the m bit signals;
the power end of the second voltage generation sub-circuit is electrically connected with the public power end, and the output end of the second voltage generation sub-circuit is electrically connected with the power end of the sensitive amplifier and is used for supplying power to the sensitive amplifier.
9. The memory circuit of claim 8, wherein the second control sub-circuit comprises at least one of the multi-bit enable control module and a second nand gate; the second voltage generation sub-circuit comprises a fifth transistor and a third resistor;
the input end of the at least one multi-bit enabling control module is electrically connected with m bit signal input ends, the output end of the at least one multi-bit enabling control module is electrically connected with the input end of the second NAND gate, and the output end of the second NAND gate is electrically connected with the control end of the fifth transistor;
the first electrode of the fifth transistor is electrically connected with the public power end, the second electrode of the fifth transistor is grounded through the third resistor, and the second electrode of the fifth transistor is also electrically connected with the power end of the sense amplifier.
10. A memory array comprising a plurality of memory circuits of any one of claims 1-9, the plurality of memory circuits arranged in an array; wherein:
the writing data control end of each storage circuit is electrically connected with the other writing data control ends of the row, and the reading data control end of each storage circuit is electrically connected with the other reading data control ends of the row;
The writing data end of each storage circuit is electrically connected with the other writing data ends of the column, and the reading data end of each storage circuit is electrically connected with the other reading data ends of the column.
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| US5877988A (en) * | 1996-07-26 | 1999-03-02 | Lg Semicon Co., Ltd. | Read/write control circuit for semiconductor memory device |
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| CN102460586A (en) * | 2009-06-15 | 2012-05-16 | 索尼公司 | Semiconductor device |
| CN103730163A (en) * | 2013-12-27 | 2014-04-16 | 深圳市国微电子有限公司 | Programmable storage system |
| CN112003606A (en) * | 2020-07-27 | 2020-11-27 | 北京炎黄国芯科技有限公司 | E-fuse programming and reading circuit |
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| US5877988A (en) * | 1996-07-26 | 1999-03-02 | Lg Semicon Co., Ltd. | Read/write control circuit for semiconductor memory device |
| US6208549B1 (en) * | 2000-02-24 | 2001-03-27 | Xilinx, Inc. | One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS |
| CN102460586A (en) * | 2009-06-15 | 2012-05-16 | 索尼公司 | Semiconductor device |
| CN103730163A (en) * | 2013-12-27 | 2014-04-16 | 深圳市国微电子有限公司 | Programmable storage system |
| CN112003606A (en) * | 2020-07-27 | 2020-11-27 | 北京炎黄国芯科技有限公司 | E-fuse programming and reading circuit |
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