CN115938436A - A storage circuit and a storage array - Google Patents

Abstract

The invention discloses a storage circuit and a storage array, which relate to the technical field of semiconductors. When a user writes data into the storage circuit, the situation of wrong writing can be avoided to a certain extent, thereby improving the reliability of the storage circuit. The storage circuit includes an access unit circuit and a first control circuit. The input terminal of the first control circuit is electrically connected to the m bit signal input terminals, the output terminal is electrically connected to the power supply terminal of the access unit circuit, and the power supply terminal is electrically connected to the fuse signal terminal. The first control circuit is used for supplying power to the access unit circuit when the m bit signals satisfy the first preset condition and the fuse signal satisfies the second preset condition. Among them, m is a positive integer. The data storage terminal of the access unit circuit is electrically connected to the fuse signal terminal, and when the fuse signal satisfies the second preset condition, the access unit circuit is used to store the data written in the write data terminal. The storage array includes the storage circuit mentioned in the above technical solution.

Description

A storage circuit and a storage array

technical field

The invention relates to the technical field of semiconductors, in particular to a storage circuit and a storage array.

Background technique

Electrically programmable fuse (Electrically programmable fuse, abbreviated as eFuse) is a one-time programmable memory developed by electromigration. Fuse programming is performed based on the principle of electromigration, and the programmed information can be permanently stored.

At present, eFuse storage circuits are widely used in aviation, mobile devices, routers and other fields, and higher requirements are placed on the reliability of eFuse storage circuits. However, in some existing eFuse storage circuits, there are still cases where users write data by mistake, and the reliability of the eFuse storage circuits cannot be improved.

Contents of the invention

The purpose of the present invention is to provide a storage circuit and a storage array, so that when a user writes data into the storage circuit, the situation of wrong writing can be avoided to a certain extent, thereby improving the reliability of the storage circuit.

In a first aspect, the present invention provides a storage circuit, including: an access unit circuit and a first control circuit. The input terminal of the first control circuit is electrically connected to the m bit signal input terminals, the output terminal is electrically connected to the power supply terminal of the access unit circuit, and the power supply terminal of the first control circuit is electrically connected to the fuse signal terminal. The first control circuit is used for supplying power to the access unit circuit when the m bit signals satisfy the first preset condition and the fuse signal satisfies the second preset condition. Among them, m is a positive integer. The data storage terminal of the access unit circuit is electrically connected to the fuse signal terminal, and when the fuse signal satisfies the second preset condition, the access unit circuit is used to store the data written in the write data terminal.

Compared with the prior art, in the storage circuit provided by the present invention, the input terminal of the first control circuit is electrically connected to the m bit signal input terminals, and the output terminal is electrically connected to the power supply terminal of the access unit circuit. The first control circuit The power end of the fuse is electrically connected to the signal end of the fuse. Moreover, when the m bit signals input from the m bit signal terminals satisfy the first preset condition, and the fuse signal input from the fuse signal terminal satisfies the second preset condition, the first control circuit can provide the access unit circuit with the The required power supply voltage, the access circuit can write data normally. Based on this, the present invention can control the m bit signals and the fuse signal so that the first control circuit can supply power to the access unit circuit, and the access unit circuit can write data normally. Therefore, the present invention can avoid user error. The case of writing data. At the same time, the data storage terminal of the access unit circuit is also electrically connected to the fuse signal terminal. When the fuse signal meets the second preset condition, the access unit circuit can only write The data written in the data terminal is stored, which further improves the reliability of the storage circuit. It can be seen that the storage circuit provided by the present invention can only store the data written in the write data terminal when the m bit signals satisfy the first preset condition and the fuse signal satisfies the second preset condition. Therefore, the storage circuit provided by the present invention can prevent the user from writing data by mistake to a certain extent, thereby improving the reliability of the storage circuit.

In a second aspect, the present invention further provides a storage array, including a plurality of storage circuits described in the first aspect, and the plurality of storage circuits are arranged in an array. The write data control terminal of each storage circuit is electrically connected to other write data control terminals of the corresponding row, and the read data control terminal of each storage circuit is electrically connected to other read data control terminals of the corresponding row. The write data terminal of each storage circuit is electrically connected to other write data terminals of the corresponding column, and the read data terminal of each storage circuit is electrically connected to other read data terminals of the corresponding column.

Compared with the prior art, the beneficial effect of the storage array provided by the present invention is the same as that of the storage circuit described in the first aspect above, and will not be repeated here.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 is a schematic structural diagram of a storage circuit provided by an embodiment of the present invention;

2 to 4 are schematic structural diagrams of the first control sub-circuit provided by the embodiment of the present invention;

FIG. 5 is a schematic structural diagram of an access unit circuit provided by an embodiment of the present invention;

6 is a schematic structural diagram of a sense amplifier provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a second control circuit provided by an embodiment of the present invention;

8 to 10 are schematic structural diagrams of the second control sub-circuit provided by the embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a storage array provided by an embodiment of the present invention.

Reference signs:

1-storage circuit, 11-first control circuit,

12-access unit circuit, 111-first control sub-circuit,

112-the first voltage generation sub-circuit, 1111-multi-bit enabling control module,

1111a-first NOR gate, 1111b-AND gate,

1112-the first NAND gate, 1113-the NOT gate,

121-write sub-circuit, 1211-second NOR gate,

122-fuse, 123-reading sub-circuit,

13-Second control circuit, 14-Sensitive amplifier,

131-the second control subcircuit, 132-the second voltage generation subcircuit,

1311-the second NAND gate, 2-storage array.

Detailed ways

In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their sequence is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and words such as "first" and "second" do not necessarily limit the difference.

It should be noted that, in the present invention, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

In the present invention, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (one) of a, b or c may represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b and c Combination, where a, b, c can be single or multiple.

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Electrically programmable fuse (Electrically programmable fuse, abbreviated as eFuse) is a one-time programmable memory developed by electromigration. Fuse programming is performed based on the principle of electromigration, and the programmed information can be permanently stored. The eFuse circuit can not only be used as a storage circuit to store important information in the chip, but also can be used as a redundant circuit to improve the reliability of the chip.

At present, eFuse storage circuits are widely used in aviation, mobile devices, routers and other fields, and higher requirements are placed on the reliability of eFuse storage circuits. However, in some existing eFuse storage circuits, there are still cases where users write data by mistake, and the reliability of the eFuse storage circuits cannot be improved.

In view of the above problems, an embodiment of the present invention provides a storage circuit 1 . As shown in FIG. 1 , the storage circuit 1 provided by the embodiment of the present invention includes: an access unit circuit 12 and a first control circuit 11 . The input terminal of the first control circuit 11 is electrically connected to the m bit signal input terminals, the output terminal is electrically connected to the power supply terminal of the access unit circuit 12, and the power supply terminal of the first control circuit 11 is electrically connected to the fuse signal terminal FS. The first control circuit 11 is configured to supply power to the access unit circuit 12 when the m bit signals satisfy the first preset condition and the fuse signal satisfies the second preset condition. where m is a positive integer. The data storage terminal of the access unit circuit 12 is electrically connected to the fuse signal terminal FS. When the fuse signal meets the second preset condition, the access unit circuit 12 is used to store the data written in the write data terminal.

It can be seen from the schematic structural diagram of the storage circuit 1 provided by the embodiment of the present invention that in the storage circuit 1 provided by the embodiment of the present invention, the input terminal of the first control circuit 11 is electrically connected to the m bit signal input terminals, and the output terminal is connected to the access unit The power supply terminal of the circuit 12 is electrically connected, and the power supply terminal of the first control circuit 11 is electrically connected to the fuse signal terminal FS. Moreover, when the m bit signals input from the m bit signal terminals satisfy the first preset condition, and the fuse signal input from the fuse signal terminal FS satisfies the second preset condition, the first control circuit 11 can send the information to the access unit circuit 12 provides the required power supply voltage VDD_CELL, so that the access circuit 1 can write data normally. Based on this, the embodiment of the present invention can control the m bit signals and the fuse signal so that the first control circuit 11 can supply power to the access unit circuit 12, and the access unit circuit 12 can write data normally. Therefore, this The embodiment of the invention can avoid the situation that the user writes data by mistake. At the same time, the data storage terminal of the access unit circuit 12 is also electrically connected to the fuse signal terminal FS. When the fuse signal satisfies the second preset condition, the access unit circuit 12 can Storing the data written in the write data terminal further improves the reliability of the storage circuit 1 . It can be seen that the storage circuit 1 provided by the embodiment of the present invention can only write the data written in the write data terminal when the m bit signals satisfy the first preset condition and the fuse signal satisfies the second preset condition. to store. Therefore, the storage circuit 1 provided by the embodiment of the present invention can avoid the situation that the user writes data by mistake to a certain extent, thereby improving the reliability of the storage circuit 1 .

in practical applications. In order to minimize the probability of the user writing data by mistake, preferably, m≥4. When m=4, the probability of being able to write data normally is only 1/16, and the probability of not being able to write data is 15/16, which can avoid the occurrence of users writing data by mistake to the greatest extent.

In a possible implementation manner, as shown in FIG. 1 , the first control circuit 11 includes a first control subcircuit 111 and a first voltage generation subcircuit 112 . The input terminal of the first control subcircuit 111 is electrically connected to the m bit signal input terminals I ₁ , I ₂ , I ₃ , and I ₄ , and the output terminal of the first control subcircuit 111 is connected to the control circuit of the first voltage generation subcircuit 112. The terminals are electrically connected, and are used to control the on-off of the first voltage generating sub-circuit 112 under the action of m-bit signals. The power terminal of the first voltage generating sub-circuit 112 is electrically connected to the fuse signal terminal FS, and the output terminal of the first voltage generating sub-circuit 112 is electrically connected to the power terminal of the access unit circuit 12 for supplying power to the access unit circuit 12 .

In the specific implementation process, by controlling the input of the m-bit signal so that it meets the first preset condition, under the action of the m-bit signal, the output signal of the first control sub-circuit 111 controls the first voltage generation sub-circuit 112 is turned on. When the first voltage generating sub-circuit 112 is turned on, when the fuse signal satisfies the second preset condition, the first voltage generating sub-circuit 112 supplies power to the access unit circuit 12 . Based on this, when m bit signals do not satisfy the first preset condition, the output signal of the first control subcircuit 111 cannot turn on the first voltage generation subcircuit 112, and at this time, the first voltage generation subcircuit 112 cannot The unit circuit 12 is powered to prevent users from writing data by mistake. In addition, even if the first voltage generation sub-circuit 112 is turned on under the action of m bit signals, that is, when the m bit signals satisfy the first preset condition, but the fuse signal does not satisfy the second preset condition, The first voltage generation sub-circuit 112 also cannot generate the power supply voltage VDD_CELL required by the access unit circuit 12, and the access unit circuit 12 cannot write data in the absence of power supply, which also avoids the situation where the user writes data by mistake .

Please refer to FIG. 1 to FIG. 4 together. In some embodiments, the first control subcircuit 111 includes at least one multi-bit enable control module 1111 , a first NAND gate 1112 and a NOT gate 1113 . The input end of at least one multi-bit enable control module 1111 is electrically connected to the m bit signal input ends; the output end of at least one multi-bit enable control module 1111 is correspondingly connected to the input end of the first NAND gate 1112, and the first NAND The output terminal of the NOT gate 1112 is electrically connected to the input terminal of the NOT gate 1113 .

The first voltage generating sub-circuit 112 includes a first transistor T1, a second transistor T2, a first resistor R1 and a second resistor R2. The control terminal of the first transistor T1 is electrically connected to the output terminal of the NOT gate 1113, the first electrode of the first transistor T1 is electrically connected to the fuse signal terminal FS through the first resistor R1, and the first electrode of the first transistor T1 is also connected to the first electrode of the first transistor T1. The control ends of the two transistors T2 are electrically connected, and the second electrode of the first transistor T1 is grounded. The first electrode of the second transistor T2 is electrically connected to the fuse signal terminal FS, the second electrode of the second transistor T2 is grounded through the second resistor R2, and the second electrode of the second transistor T2 is also connected to the power supply terminal of the access unit circuit 12 electrical connection.

It can be understood that the above-mentioned first transistor T1 is an N-type transistor, that is, it is turned on when the control terminal is at a high level (logic "1"). The second transistor T2 is a P-type transistor, that is, it is turned on when the control terminal is at a low level (logic "0"). The above-mentioned second preset condition is that the fuse signal terminal FS is at a high level (logic “1”).

In a specific implementation, when the first transistor T1 needs to be turned on, it is necessary to make the level of the control terminal of the first transistor T1 high (logic “1”). When the first transistor T1 is turned on, the first electrode is directly connected to the second electrode, and since the second electrode is directly grounded, the first electrode is also at a low level (logic "0"). And because there is a first resistor R1 between the first electrode of the first transistor T1 and the fuse signal terminal FS, it can prevent the fuse signal terminal FS from being directly connected to the ground terminal and being set to a low level (logic "0") . At this time, the first electrode of the first transistor T1 outputs a low level (logic "0") signal to the control terminal of the second transistor T2, thereby turning on the second transistor T2. When the signal of the fuse signal terminal FS is at low level (logic “0”), no voltage signal is generated even if the second transistor T2 is turned on, that is, the power supply voltage VDD_CELL required by the access unit circuit 12 cannot be generated. Only when the fuse signal terminal FS is at a high level, the second electrode of the second transistor T2 can generate the power supply voltage VDD_CELL required by the access unit circuit 12 . Similarly, the purpose of setting the second resistor R2 is to prevent the second electrode of the second transistor T2 from being directly grounded and set to a low level (logic "0").

Furthermore, as shown in FIG. 2 to FIG. 4 , the multi-bit enable control module 1111 in the above embodiment includes at least one first NOR gate 1111a and at least one AND gate 1111b, and m≥4. The input terminals of each first NOR gate 1111 a are respectively electrically connected to at least two bit signal input terminals, and the output terminals of each first NOR gate 1111 a are electrically connected to the first input terminal of the first NAND gate 1112 . The input terminal of each AND gate 1111b is electrically connected to at least two bit signal input terminals respectively, and the output terminal of each AND gate 1111b is connected to the second input terminal of the first NAND gate 1112 .

In practical applications, when the input end of the multi-bit enable control module 1111 is connected to the input end of the bit signal, the input end of the first NOR gate 1111a and the input end of the AND gate 1111b can be alternately connected to the input end of the bit signal, That is, the odd-numbered bit signal input terminals are connected to the input terminal of the first NOR gate 1111a, and the even-numbered bit signal input terminals are connected to the input terminal of the AND gate 1111b. In this way, the m bit signals can satisfy the first preset condition only when "0"s and "1"s are arranged alternately. That is, when m=4, the m bit signals must be "0101", which avoids the situation that the m bit signals are "0011" caused by noise interference, etc., can further reduce the probability of wrong writing, and improve the storage circuit. 1 reliability. In addition, after changing the connection order, the bit signal input ends sorted into even numbers are connected to the input ends of the first NOR gate 1111a, and the bit signal input ends sorted into odd numbers are connected to the input ends of the AND gate 1111b. The order of the m bit signals is adjusted. At this time, when m=4, the m bit signals are "1010". For this, the embodiment of the present invention does not specifically limit it.

It can be understood that NAND gates, NOR gates, AND gates, and NOT gates are all basic logic circuits in digital circuits.

The NAND gate has at least two input terminals and one output terminal. When all the input terminals are high level (logic "1"), the output is low level (logic "0"); when at least one of the input terminals is When low level (logic "0"), the output is high level (logic "1").

A NOR gate has at least two inputs and one output. When any input is high (logic "1"), the output is low (logic "0"); when all inputs are low Level (logic "0"), the output is high (logic "1").

An AND gate has at least two inputs and one output, and the circuit output is high (logic "1") only when all inputs are high (logic "1"), otherwise the output is low level (logic "0").

The NOT gate has an input terminal and an output terminal. When the input terminal is high level (logic "1"), the output terminal is low level (logic "0"); otherwise, when the input terminal is low level (logic "0") "0"), the output is high (logic "1").

Exemplarily, as shown in FIG. 2 , when m=4, that is, there are 4 bit signal input terminals, then the first control subcircuit 111 should also have 4 input terminals accordingly. The first control subcircuit 111 may include a multi-bit enable control module 1111 , a first NAND gate 1112 and a NOT gate 1113 . Specifically, the first control subcircuit 111 includes a first NOR gate 1111 a , an AND gate 1111 b , a first NAND gate 1112 and a NOT gate 1113 . The first input end of the first NOR gate 1111a is electrically connected with the first bit signal input end _I1 , the second input end of the first NOR gate 1111a is electrically connected with the third bit signal input end I3, and the first bit signal input end _I3 is electrically connected. The output terminal of the NOR gate 1111 a is electrically connected to the first input terminal of the first NAND gate 1112 . The first input end of the AND gate 1111b is electrically connected to the second bit signal input end _I2 , the second input end of the AND gate 1111b is electrically connected to the fourth bit signal input end _I4 , and the output end of the AND gate 1111b is electrically connected to the fourth bit signal input end I4. A second input terminal of a NAND gate 1112 is connected, and an output terminal of the first NAND gate 1112 is electrically connected with an input terminal of a NOT gate 1113 . At this time, the first preset condition is: m bit signals are "0101", that is, the first bit signal is "0", the second bit signal is "1", and the third bit signal is "0", The fourth bit signal is "1". Then the output of the first NOR gate 1111a is "0", the output of the AND gate 1111b is "1", then the output of the first NOR gate 1112 is "0", and the output of the NOT gate 1113 is "1". , the first transistor T1 can be turned on.

Exemplarily, as shown in FIG. 3 , when m=6, that is, there are 6 bit signal input terminals, then the first control sub-circuit 111 should also have 6 input terminals accordingly. The first control sub-circuit 111 may include a multi-bit enable control module 1111 and a first NAND gate 1112 and a first NAND gate 1113 . Specifically, the first control subcircuit 111 includes a first NOR gate 1111 a , an AND gate 1111 b , a first NAND gate 1112 and a NOT gate 1113 . Wherein, the first NOR gate 1111a has 3 input terminals, and the AND gate 1111b has 3 input terminals. The first input end of the first NOR gate 1111a is electrically connected with the first bit signal input end _I1 , the second input end of the first NOR gate 1111a is electrically connected with the third bit signal input end I3, and the first bit signal input end _I3 is electrically connected. The third input end of the NOR gate 1111a is electrically connected to the fifth bit signal input end _I5 , and the output end of the first NOR gate 1111a is electrically connected to the first input end of the first NAND gate 1112. The first input end of the AND gate 1111b is electrically connected to the second bit signal input end _I2 , the second input end of the AND gate 1111b is electrically connected to the fourth bit signal input end _I4 , and the third input end of the AND gate 1111b It is electrically connected with the sixth bit signal input terminal _I6 , and the output terminal of the AND gate 1111b is connected with the second input terminal of the first NAND gate 1112, and the output terminal of the first NAND gate 1112 is electrically connected with the input terminal of the NOT gate 1113. connect. At this time, the first preset condition is that the m bit signals are "010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the second bit signal is "0". The four bit signals are "1", the fifth bit signal is "0", and the sixth bit signal is "1". Then the output of the first NOR gate 1111a is "0", the output of the AND gate 1111b is "1", then the output of the first NOR gate 1112 is "0", and the output of the NOT gate 1113 is "1". , the first transistor T1 can be turned on. It should be understood that when m=6 in the above embodiment, there may also be a first NOR gate 1111a with 4 input terminals and an AND gate 1111b with 2 input terminals in the multi-bit enable control module 1111. The embodiment of the invention does not specifically limit this.

Exemplarily, as shown in FIG. 4 , when m=8, that is, there are 8 bit signal input terminals, then the first control subcircuit 111 should also have 8 input terminals accordingly. The first control subcircuit 111 may include two multi-bit enable control modules 1111 , a first NAND gate 1112 and a NOT gate 1113 . Specifically, the first control subcircuit 111 includes 2 first NOR gates 1111a, 2 AND gates 1111b, 1 first NAND gate 1112 and 1 NOT gate 1113. The 2 first NOR gates 1111a have 4 input terminals, respectively electrically connected to the first bit signal input terminal I ₁ , the third bit signal input terminal I ₃ , the fifth bit signal input terminal I ₅ and the seventh bit signal input terminal I ₇ , two The output terminals of the first NOR gate 1111a are electrically connected to the first input terminal and the third input terminal of the first NAND gate 1112 respectively. The two AND gates 1111b have 4 input terminals in total, which are respectively connected to the second bit signal input terminal I ₂ , the fourth bit signal input terminal I ₄ , the sixth bit signal input terminal I ₆ and the eighth bit signal input terminal _I8 is electrically connected, and the output ends of two AND gates 1111b are electrically connected with the second input end of the first NAND gate 1112 and the fourth input end respectively, the output end of the first NAND gate 1112 and the input end of the NOT gate 1113 electrical connection. At this time, the first preset condition is that the m bit signals are "01010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the first bit signal is "0". The four bit signals are "1", the fifth bit signal is "0", the sixth bit signal is "1", the seventh bit signal is "0", and the eighth bit signal is "1". Then the outputs of the two first NOR gates 1111a are both "1", and the outputs of the two AND gates 1111b are also "1". Then, the output of the first NOR gate 1112 is "0", and the NOT gate When the output of 1113 is "1", the first transistor T1 can be turned on. It can be understood that, when m=8, the first control subcircuit 111 may only include a multi-bit enable control module 1111, a first NAND gate 1112 and a NOT gate 1113. At this time, the multi-bit enable control The first NOR gate 1111a and the AND gate 1111b in the module 1111 may have 4 input terminals respectively; or, the first NOR gate 1111a in the multi-bit enable control module 1111 has 3 input terminals, and the AND gate 1111b has 5 input terminals. or, a first NOR gate 1111a in the multi-bit enabling control module 1111 has 3 input terminals, an AND gate 1111b has 2 input terminals, and another AND gate 1111b has 3 input terminals end. Since there are many transformable situations, it cannot be exhaustive, and this embodiment of the present invention does not limit it.

It can be understood that, in the above-mentioned embodiment, the arrangement order of the m-bit signals is only related to the type of digital logic gate connected to it, that is, if the first NOR gate in the multi-bit enabling control module 1111 is adjusted in actual operation 1111a and the order of the AND gate 1111b, the first preset condition should be adjusted accordingly, which is not specifically limited in this embodiment of the present invention.

In a possible implementation manner, as shown in FIG. 5 , the access unit circuit 12 includes a write sub-circuit 121 , a read sub-circuit 123 and a fuse 122 . The first end of the write sub-circuit 121 is electrically connected to the write data terminal BS and the write data control end WL respectively, the second end of the write sub-circuit 121 is electrically connected to the first end of the read sub-circuit 123, and the write The power terminal of the sub-circuit 121 is electrically connected to the output terminal of the first control circuit 11 . The first end of the fuse 122 is electrically connected to the fuse signal terminal FS, and the second end of the fuse 122 is electrically connected to the second end of the write sub-circuit 121 and the first end of the read sub-circuit 123 . The control terminal of the reading sub-circuit 123 is electrically connected to the reading data control terminal RL, and the second terminal of the reading sub-circuit 123 is electrically connected to the reading data terminal BL.

In some embodiments, the writing sub-circuit 121 includes a second NOR gate 1211 and a third transistor T3. The first input terminal of the second NOR gate 1211 is electrically connected to the write data terminal BS, the second input terminal of the second NOR gate 1211 is electrically connected to the write data control terminal WL, and the output terminal of the second NOR gate 1211 It is electrically connected to the control terminal of the third transistor T3 , and the power supply terminal of the second NOR gate 1211 is electrically connected to the output terminal of the first control circuit 11 . The first electrode of the third transistor T3 is electrically connected to the fuse signal terminal FS through the fuse 122 , and the second electrode of the third transistor T3 is grounded. The reading sub-circuit 123 includes a fourth transistor T4. The control end of the fourth transistor T4 is electrically connected to the read data control end RL, the first electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3, and the second electrode of the fourth transistor T4 is electrically connected to the read data end. BL is electrically connected.

It can be understood that the third transistor T3 and the fourth transistor T4 are both N-type transistors, that is, they are turned on when the control terminal is at a high level (logic “1”).

In the phase of writing data, the write data control terminal WL is low level (logic “0”), that is, the input signal of the second input terminal of the second NOR gate 1211 is low level (logic “0”). In the case that the second NOR gate 1211 can write normally, it can be determined that the fuse signal still satisfies the above-mentioned second preset condition at this time, that is, the fuse signal terminal is at a high level (logic “1”). At this time, since the first end of the fuse 122 is electrically connected to the fuse signal terminal FS, the second end of the fuse 122 is connected to the first electrode of the third transistor T3. If the third transistor T3 is turned on, the fuse 122 If the third transistor T3 is not turned on, the fuse 122 will not be blown. That is, whether the fuse 122 is blown or not is determined by whether the third transistor T3 is turned on or not. Since the control terminal of the third transistor T3 is electrically connected to the output terminal of the second NOR gate 1211, when the input signal of the second input terminal of the second NOR gate 1211 is low level (logic "0"), The input signal of the first input terminal of the second NOR gate 1211 directly determines the output signal of the second NOR gate 1211 . Exemplarily, when the input signal of the first input terminal of the second NOR gate 1211 is low level (logic "0"), the second NOR gate 1211 outputs a high level (logic "1"), and the second NOR gate 1211 is turned on. Three-transistor T3, fuse 122 is blown, then the stored data is code "1"; The invertor 1211 outputs a low level (logic "0"), the third transistor T3 is not turned on, the fuse 122 is not blown, and the stored data is encoded as "0".

In the phase of reading data, the read data control terminal RL is at a high level (logic “1”), thereby controlling the fourth transistor T4 to be turned on. Since the writing of data has been completed at this time, in order to avoid wrong writing, it is necessary to set the fuse signal terminal FS to a low level (logic “0”). The first electrode of the fourth transistor T4 is directly electrically connected to the second electrode, that is, the state of the fuse 122 can be read by the read data terminal BL. If the fuse 122 is blown, the impedance is infinite, and if the fuse 122 is not blown and remains connected, the impedance is approximately infinitesimal.

In a possible implementation manner, as shown in FIG. 6 and FIG. 7 , the storage circuit 1 further includes a sense amplifier 14 and a second control circuit 13 . The input end of the second control circuit 13 is electrically connected to the m bit signal input ends, and the output end is electrically connected to the power supply end of the sense amplifier 14, and the second control circuit 13 is used to satisfy the first preset condition when the m bit signals case, power is supplied to the sense amplifier 14 . The input end of the sense amplifier 14 is electrically connected to the output end of the access unit circuit 12 for reading data stored in the access unit circuit 12 .

As shown in FIG. 6 , the input terminal of the sense amplifier 14 is electrically connected to the read data terminal BL. The sense amplifier 14 is used to detect the blown state of the fuse 122 , and convert the blown state into a corresponding voltage signal output, so as to complete the reading of the data stored in the storage circuit 1 . In FIG. 6 , CK is the clock signal terminal, VDD_AMP is the power supply terminal of the sense amplifier 14 , AP is the first node, AN is the second node, and VOP is the output terminal of the sense amplifier 14 . The sense amplifier 14 has a mirror symmetrical structure, so by comparing the impedance of the fuse 122 with the resistance of the fourth resistor R4, the comparison result can be output through the output terminal VOP. If the fuse 122 is in a blown state, the impedance is infinite, that is, it is greater than the resistance of the fourth resistor R4, and the output terminal VOP will output a high level (logic "1"), that is, the value stored in the access unit circuit 12 will be read. The data is code "1"; if the fuse 122 is connected, the impedance is approximately infinitesimal, that is, less than the resistance of the fourth resistor R4, then the output terminal VOP will output a low level (logic "0"), that is, read The data stored in the access unit circuit 12 is coded "0".

In some embodiments, as shown in FIG. 7 , the second control circuit 13 includes a second control subcircuit 131 and a second voltage generation subcircuit 132 . The input terminal of the second control subcircuit 131 is electrically connected to the input terminals of the m bit signals, and the output terminal of the second control subcircuit 131 is electrically connected to the control terminal of the second voltage generation subcircuit 132, which is used for the m bit signal Under the action of the second voltage generation sub-circuit 132 is controlled on and off. The power supply terminal of the second voltage generation sub-circuit 132 is electrically connected to the common power supply terminal VDD, and the output terminal of the second voltage generation sub-circuit 132 is electrically connected to the power supply terminal of the sense amplifier 14 for supplying power to the sense amplifier 14 .

In the specific implementation process, by controlling the input of the m-bit signal so that it meets the first preset condition, under the action of the m-bit signal, the output signal of the second control sub-circuit 131 controls the second voltage generation sub-circuit 132 is turned on. In the event of conduction of the second voltage generating sub-circuit 132 , the second voltage generating sub-circuit 132 supplies power to the sense amplifier 14 . Based on this, when the m bit signals do not meet the first preset condition, the output signal of the second control subcircuit 131 cannot turn on the second voltage generation subcircuit 132, and at this time, the second voltage generation subcircuit 132 cannot generate sensitive The power supply voltage VDD_AMP required by the amplifier 14, that is, the second voltage generation sub-circuit 132 cannot supply power to the sense amplifier 14, and the sense amplifier 14 cannot normally read data without power supply, which ensures the security of the data and further improves The reliability of the storage circuit 1 is improved.

In some embodiments, as shown in FIG. 7 to FIG. 10 , the second control subcircuit 131 includes at least one multi-bit enable control module 1111 and a second NAND gate 1311 . The second voltage generating sub-circuit 132 includes a fifth transistor T5 and a third resistor R3. The input end of at least one multi-bit enabling control module 1111 is electrically connected to the m bit signal input ends, the output end of at least one multi-bit enabling control module 1111 is electrically connected to the input end of the second NAND gate 1311, and the second AND The output end of the NOT gate 1311 is electrically connected to the control end of the fifth transistor T5. The first electrode of the fifth transistor T5 is electrically connected to the common power supply terminal VDD, the second electrode of the fifth transistor T5 is grounded through the third resistor R3, and the second electrode of the fifth transistor T5 is also electrically connected to the power supply terminal of the sense amplifier 14 .

It can be understood that the above-mentioned fifth transistor T5 is a P-type transistor, that is, it is turned on at a low level (logic "0").

In specific implementation, when the fifth transistor T5 needs to be turned on, it is necessary to make the level of the control terminal of the fifth transistor T5 low (logic "0"). When the fifth transistor T5 is turned on, the first electrode and the second electrode are directly connected. Since the first electrode is electrically connected to the common power supply terminal VDD, and there is a third resistor R3 between the second electrode and the ground terminal, the second electrode Both the first electrode and the second electrode are at high level (logic "1") under the effect of the common power supply terminal VDD. The second electrode of the fifth transistor T5 is electrically connected to the power supply terminal of the sense amplifier 14 , so that the power supply voltage VDD_AMP required by the sense amplifier 14 is generated.

Exemplarily, as shown in FIG. 8 , when m=4, that is, there are 4 bit signal input terminals, the second control subcircuit 131 should also have 4 input terminals accordingly. The second control subcircuit 131 may include a multi-bit enable control module 1111 and a second NAND gate 1311 . Specifically, the second control subcircuit 131 includes a first NOR gate 1111 a , an AND gate 1111 b and a second NAND gate 1311 . The first input end of the first NOR gate 1111a is electrically connected with the first bit signal input end _I1 , the second input end of the first NOR gate 1111a is electrically connected with the third bit signal input end I3, and the first bit signal input end _I3 is electrically connected. The output terminal of the NOR gate 1111 a is electrically connected to the first input terminal of the second NAND gate 1311 . The first input end of the AND gate 1111b is electrically connected to the second bit signal input end _I2 , the second input end of the AND gate 1111b is electrically connected to the fourth bit signal input end _I4 , and the output end of the AND gate 1111b is electrically connected to the fourth bit signal input end I4. The second input terminal of the second NAND gate 1311 is connected, and the output terminal of the second NAND gate 1311 is electrically connected with the control terminal of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "0101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the third bit signal is "0". The four-bit signal is "1". Then the output of the first NOR gate 1111a is "0", the output of the AND gate 1111b is "1", then the output of the second NAND gate 1311 is "0", and the fifth transistor T5 can be turned on.

Exemplarily, as shown in FIG. 9 , when m=6, that is, there are 6 bit signal input terminals, then the second control subcircuit 131 should also have 6 input terminals accordingly. The second control subcircuit 131 may include a multi-bit enable control module 1111 and a second NAND gate 1311 . Specifically, the second control subcircuit 131 includes a first NOR gate 1111 a , an AND gate 1111 b and a second NAND gate 1311 . Wherein, the first NOR gate 1111a has 3 input terminals, and the AND gate 1111b has 3 input terminals. The first input end of the first NOR gate 1111a is electrically connected with the first bit signal input end _I1 , the second input end of the first NOR gate 1111a is electrically connected with the third bit signal input end I3, and the first bit signal input end _I3 is electrically connected. The third input terminal of the NOR gate 1111a is electrically connected to the fifth bit signal input terminal _I5 , and the output terminal of the first NOR gate 1111a is electrically connected to the first input terminal of the second NAND gate 1311. The first input end of the AND gate 1111b is electrically connected to the second bit signal input end _I2 , the second input end of the AND gate 1111b is electrically connected to the fourth bit signal input end _I4 , and the third input end of the AND gate 1111b It is electrically connected with the sixth bit signal input terminal _I6 , and the output terminal of the AND gate 1111b is connected with the second input terminal of the second NAND gate 1311, and the output terminal of the second NAND gate 1311 is connected with the control terminal of the fifth transistor T5 electrical connection. At this time, the first preset condition is that the m bit signals are "010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the second bit signal is "0". The four bit signals are "1", the fifth bit signal is "0", and the sixth bit signal is "1". Then the output of the first NOR gate 1111a is "0", the output of the AND gate 1111b is "1", then the output of the second NAND gate 1311 is "0", and the fifth transistor T5 can be turned on. It should be understood that when m=6 in the above embodiment, there may also be a first NOR gate 1111a with 4 input terminals and an AND gate 1111b with 2 input terminals in the multi-bit enable control module 1111. The embodiment of the invention does not specifically limit this.

Exemplarily, as shown in FIG. 10 , when m=8, that is, there are 8 bit signal input terminals, the second control subcircuit 131 should also have 8 input terminals accordingly. The second control subcircuit 131 may include two multi-bit enable control modules 1111 and a second NAND gate 1311 . Specifically, the second control subcircuit 131 includes 2 first NOR gates 1111a, 2 AND gates 1111b and 1 second NAND gate 1311. The 2 first NOR gates 1111a have 4 input ends in total, respectively and The first bit signal input end I ₁ , the third bit signal input end I ₃ , the fifth bit signal input end I ₅ and the seventh bit signal input end I ₇ are electrically connected, and two first NOR gates 1111a The output terminals of the NAND gate 1311 are respectively electrically connected to the first input terminal and the third input terminal. The two AND gates 1111b have 4 input terminals in total, which are respectively connected to the second bit signal input terminal I ₂ , the fourth bit signal input terminal I ₄ , the sixth bit signal input terminal I ₆ and the eighth bit signal input terminal _I8 is electrically connected, and the output terminals of the two AND gates 1111b are electrically connected with the second input terminal and the fourth input terminal of the second NAND gate 1311 respectively, and the output terminal of the second NAND gate 1311 is connected with the control of the fifth transistor T5. electrical connection. At this time, the first preset condition is that the m bit signals are "01010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the first bit signal is "0". The four bit signals are "1", the fifth bit signal is "0", the sixth bit signal is "1", the seventh bit signal is "0", and the eighth bit signal is "1". Then the outputs of the two first NOR gates 1111a are both "1", and the outputs of the two AND gates 1111b are also "1". Then, the output of the second NOR gate 1311 is "0", which can lead to The fifth transistor T5 is turned on. It can be understood that, when m=8, the second control subcircuit 131 may only include one multi-bit enable control module 1111 and a second NAND gate 1311, at this time, the multi-bit enable control module 1111 The first NOR gate 1111a and the AND gate 1111b may have 4 input terminals respectively; or, the first NOR gate 1111a in the multi-bit enable control module 1111 has 3 input terminals, and the AND gate 1111b has 5 input terminals; Alternatively, one first NOR gate 1111a in the multi-bit enable control module 1111 has 3 input terminals, one AND gate 1111b has 2 input terminals, and the other AND gate 1111b has 3 input terminals. Since there are many transformable situations, it cannot be exhaustive, and this embodiment of the present invention does not limit it.

With reference to accompanying drawings 2 to 4 and accompanying drawings 8 to 10, it can be seen that the circuit structure of the first control sub-circuit 111 is similar to that of the second control sub-circuit 131, therefore, in practical applications, in order to save In order to reduce the cost, the first control subcircuit 111 and the second control subcircuit 131 can also be combined into one, that is, the input terminal of the negated gate 1113 of the first control subcircuit 111 is directly electrically connected to the control terminal of the fifth transistor T5.

As shown in FIG. 11 , the embodiment of the present invention also provides a storage array 2 , which includes a plurality of storage circuits 1 described in the first aspect, and the plurality of storage circuits 1 are arranged in an array. The write data control terminal WL of each storage circuit 1 is electrically connected to other write data control terminals WL of the row, and the read data control terminal RL of each storage circuit 1 is electrically connected to other read data control terminals RL of the row. connect. The write data terminal BS of each storage circuit 1 is electrically connected to other write data terminals BS of the column, and the read data terminal BL of each storage circuit 1 is electrically connected to other read data terminals BL of the column.

As shown in FIG. 11 , the above storage array 2 is an 8×8 array, that is, each row and each column has 8 storage circuits. The write data control terminals WL of the 8 storage circuits 1 in each row are commonly connected together, and the read data control terminals RL of the 8 storage circuits 1 in each row are also commonly connected together. The write data terminals BS of the 8 storage circuits 1 in each column are commonly connected together, and the read data terminals BL of the 8 storage circuits 1 in each column are also commonly connected together. The fuse signal terminals FS of the 64 storage circuits 1 are commonly connected, and the power supply terminals VDD_CELL of the 64 storage circuits 1 are also commonly connected together.

Compared with the prior art, the beneficial effect of the memory array 2 provided by the embodiment of the present invention is the same as that of the above-mentioned memory circuit 1 , which will not be repeated here.

Although the present invention has been described in conjunction with various embodiments herein, in implementing the claimed invention, those skilled in the art can understand and realize the disclosure by referring to the drawings, the disclosure, and the appended claims. Other Variations of Embodiments. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

Although the invention has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (10)

1. A storage circuit, characterized in that it comprises: an access unit circuit and a first control circuit; the input end of the first control circuit is electrically connected to m bit signal input ends, and the output end is connected to the access unit circuit The power supply terminal of the unit circuit is electrically connected, the power supply terminal of the first control circuit is electrically connected to the signal terminal of the fuse, the first control circuit is used to satisfy the first preset condition when the m bit signals meet the first preset condition, and the fuse When the signal satisfies the second preset condition, supplying power to the access unit circuit; wherein, m is a positive integer; The data storage end of the access unit circuit is electrically connected to the fuse signal end, and when the fuse signal satisfies the second preset condition, the access unit circuit is used to write to the write data end The entered data is stored. 2. The storage circuit according to claim 1, wherein the first control circuit comprises a first control subcircuit and a first voltage generation subcircuit; The input terminal of the first control subcircuit is electrically connected to the input terminals of the m bit signals, and the output terminal of the first control subcircuit is electrically connected to the control terminal of the first voltage generation subcircuit, for Under the action of the m bit signals, controlling the on-off of the first voltage generating sub-circuit; The power supply end of the first voltage generation sub-circuit is electrically connected to the fuse signal end, and the output end of the first voltage generation sub-circuit is electrically connected to the power supply end of the access unit circuit, for providing the The access unit circuit supplies power. 3. The storage circuit according to claim 2, wherein the first control subcircuit comprises at least one multi-bit enable control module, a first NAND gate and a NOT gate; The input end of the at least one multi-bit enable control module is electrically connected to the m bit signal input ends; the output end of the at least one multi-bit enable control module corresponds to the input end of the first NAND gate connected, the output end of the first NAND gate is electrically connected to the input end of the NOT gate; The first voltage generation sub-circuit includes a first transistor, a second transistor, a first resistor, and a second resistor; wherein, the control terminal of the first transistor is electrically connected to the output terminal of the NOT gate, and the first The first electrode of the transistor is electrically connected to the signal terminal of the fuse through the first resistor, the first electrode of the first transistor is also electrically connected to the control terminal of the second transistor, and the first electrode of the first transistor is electrically connected to the control terminal of the second transistor. The two electrodes are grounded; the first electrode of the second transistor is electrically connected to the fuse signal terminal, the second electrode of the second transistor is grounded through the second resistor, and the second electrode of the second transistor is also connected to the ground through the second resistor. It is electrically connected with the power supply end of the access unit circuit. 4. The storage circuit according to claim 3, wherein the multi-bit enabling control module comprises at least one first NOR gate and at least one AND gate, and m≥4, wherein: The input terminals of each of the first NOR gates are respectively electrically connected to at least two of the bit signal input terminals, and the output terminals of each of the first NOR gates are connected to the first input terminals of the first NAND gates. The terminals are electrically connected; the input terminals of each of the AND gates are respectively electrically connected to at least two of the bit signal input terminals, and the output terminals of each of the AND gates are connected to the second input terminals of the first NAND gate. . 5. The storage circuit according to any one of claims 1-4, wherein the access unit circuit comprises a write sub-circuit, a read sub-circuit and a fuse; The first end of the writing sub-circuit is electrically connected to the writing data end and the writing data control end respectively, and the second end of the writing sub-circuit is electrically connected to the first end of the reading sub-circuit , the power supply end of the writing sub-circuit is electrically connected to the output end of the first control circuit; The first end of the fuse is electrically connected to the signal end of the fuse, and the second end of the fuse is electrically connected to the second end of the writing sub-circuit and the first end of the reading sub-circuit at the same time. connect; The control end of the reading sub-circuit is electrically connected to the reading data control end, and the second end of the reading sub-circuit is electrically connected to the reading data end. 6. The storage circuit according to claim 5, wherein the write sub-circuit comprises a second NOR gate and a third transistor; wherein, the first input terminal of the second NOR gate is connected to the The write data end is electrically connected, the second input end of the second NOR gate is electrically connected to the write data control end, and the output end of the second NOR gate is electrically connected to the control end of the third transistor. The power terminal of the second NOR gate is electrically connected to the output terminal of the first control circuit; the first electrode of the third transistor is electrically connected to the signal terminal of the fuse through the fuse, so The second electrode of the third transistor is grounded; The read sub-circuit includes a fourth transistor; wherein, the control end of the fourth transistor is electrically connected to the read data control end, and the first electrode of the fourth transistor is connected to the first electrode of the third transistor. The electrodes are electrically connected, and the second electrode of the fourth transistor is electrically connected to the read data terminal. 7. The storage circuit according to claim 4, further comprising a sense amplifier and a second control circuit; wherein: The input end of the second control circuit is electrically connected to the input ends of the m bit signals, and the output end is electrically connected to the power supply end of the sense amplifier, and the second control circuit is used for the m bit signal When the first preset condition is met, supply power to the sense amplifier; The input terminal of the sense amplifier is electrically connected with the output terminal of the access unit circuit, and is used for reading data stored in the access unit circuit. 8. The storage circuit according to claim 7, wherein the second control circuit comprises a second control subcircuit and a second voltage generation subcircuit; The input terminal of the second control subcircuit is electrically connected to the input terminals of the m bit signals, and the output terminal of the second control subcircuit is electrically connected to the control terminal of the second voltage generation subcircuit, for Under the action of the m bit signals, controlling the on-off of the second voltage generation sub-circuit; The power supply terminal of the second voltage generating subcircuit is electrically connected to the common power supply terminal, and the output terminal of the second voltage generating subcircuit is electrically connected to the power supply terminal of the sense amplifier for supplying power to the sense amplifier. 9. The storage circuit according to claim 8, wherein the second control subcircuit comprises at least one multi-bit enable control module and a second NAND gate; the second voltage generation subcircuit comprises a fifth transistor and a third resistor; The input end of the at least one multi-bit enable control module is electrically connected to the m bit signal input ends, and the output end of the at least one multi-bit enable control module is electrically connected to the input end of the second NAND gate. connected, the output end of the second NAND gate is electrically connected to the control end of the fifth transistor; The first electrode of the fifth transistor is electrically connected to the common power supply terminal, the second electrode of the fifth transistor is grounded through the third resistor, and the second electrode of the fifth transistor is also connected to the sense amplifier. The power terminal is electrically connected. 10. A storage array, characterized in that it comprises a plurality of storage circuits according to any one of claims 1-9, and a plurality of storage circuits are arranged in an array; wherein: The write data control terminal of each storage circuit is electrically connected to other write data control terminals of the row, and the read data control terminal of each storage circuit is electrically connected to other read data control terminals of the row. Terminal connection; The write data terminal of each storage circuit is electrically connected to the other write data terminals of the column, and the read data terminal of each storage circuit is electrically connected to the other read data terminals of the column.

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