JP2015167061A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read information stored in an anti-fuse element with high sensitivity.SOLUTION: A semiconductor device includes: a determination circuit 133 for generating a determination signal AFBLB on the basis of the potential of a sense node AFBL; a current control circuit 131 connected between the wiring of an internal potential VPERI and the sense node, to which the determination signal AFBLB is supplied; a current control circuit 132 connected between the wiring of a ground potential VSS and the sense node AFBL, to which the determination signal AFBLB is supplied; an anti-fuse element AF connected between the power supply wiring VBBSV and the sense node AFBL; and a rectifier circuit 140 for rectifying currents flowing through the anti-fuse element AF. Thus, it is possible to increase a voltage being applied between both ends of the anti-fuse element without increasing a power supply voltage in a sense circuit. Therefore, it is possible to improve reading sensitivity.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an antifuse element.

  In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a defective memory cell is replaced with a redundant memory cell, whereby the defective memory cell is relieved. The address of the defective memory cell is programmed in a nonvolatile memory element such as an antifuse element in the manufacturing stage (see Patent Document 1).

  Examples of the nonvolatile memory element include a fuse circuit, a fuse element, and an antifuse element. In particular, the anti-fuse element is insulated between both ends in the initial state, and transitions to a conductive state if dielectric breakdown is caused by applying a high voltage between both ends. And after dielectric breakdown, since it cannot return from a conduction | electrical_connection state to an insulation state, memory | storage of irreversible and non-volatile information is attained.

  Here, it is known that the resistance value of the antifuse element after dielectric breakdown is not necessarily constant and has a large variation. That is, the resistance value may be sufficiently low due to dielectric breakdown, or the resistance value may remain relatively high even after dielectric breakdown. For this reason, the sense circuit that reads out information stored in the antifuse element is a highly sensitive circuit so that it can correctly determine whether or not the breakdown is present even when there is such a variation in resistance value. It is necessary to adopt a configuration.

JP 2007-80302 A

  In order to read out the information stored in the antifuse element with high sensitivity, it is considered effective to increase the voltage applied across the antifuse element during reading. However, simply increasing the voltage applied across the antifuse element simply increases the leakage current in the sense circuit, and thus the read sensitivity cannot always be increased sufficiently.

  A semiconductor device according to one aspect of the present invention includes first to third power supply lines to which first to third potentials are supplied, a determination circuit that generates a determination signal based on the potential of a sense node, and the first A first current control circuit which is connected between one power supply wiring and the sense node and whose conduction state is controlled based on the determination signal; and is connected between the second power supply wiring and the sense node. A second current control circuit whose conduction state is controlled based on the determination signal, an antifuse element connected between the third power supply wiring and the sense node, and via the antifuse element And a rectifier circuit that rectifies the flowing current.

  A semiconductor device according to another aspect of the present invention includes first to third power supply wirings to which first to third potentials are supplied, a determination circuit that generates a determination signal based on a potential of a sense node, A first conductive type first transistor connected between a first power supply line and the sense node and supplied with the determination signal to a gate electrode, and between the second power supply line and the sense node. A second transistor of a second conductivity type connected to the gate electrode and supplied with the determination signal; an antifuse element connected between the third power supply line and the sense node; and the antifuse element A third transistor of the first conductivity type connected in series, wherein a potential difference between the first potential and the third potential is larger than a potential difference between the first potential and the second potential. With features That.

  According to the present invention, since the voltage applied across the antifuse element can be increased without increasing the power supply voltage in the sense circuit, the read sensitivity is improved. In addition, even if the resistance value of the antifuse element is low, the backflow of current to the antifuse element is prevented, so that unintended current generation can be prevented.

1 is a block diagram showing a configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. FIG. 2 is a block diagram for explaining a configuration of antifuse circuits 51a and 52a and a pump circuit 100 according to the first embodiment. 2 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, and a rectifier circuit 140 according to the first embodiment. FIG. FIG. 6 is a timing chart for explaining the operation of the first embodiment. FIG. 5 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, and a rectifier circuit 140 according to a modification of the first embodiment. FIG. 5 is a block diagram for explaining a configuration of antifuse circuits 51a and 52a and a pump circuit 100 according to a second embodiment. FIG. 5 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, a rectifier circuit 140, and a verify bit selection circuit 160 according to a second embodiment. FIG. 6 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, a rectifier circuit 140, and a verify bit selection circuit 160 according to a modification of the second embodiment. It is a timing diagram for demonstrating operation | movement of 2nd Embodiment. It is a block diagram for demonstrating the structure of the antifuse circuits 51a and 52a and the pump circuit 100 by 3rd Embodiment. 3 is a circuit diagram of an antifuse array 170. FIG. 3 is a circuit diagram of a driver circuit 191. FIG. It is a circuit diagram of the load circuit 110 in 3rd Embodiment. It is a circuit diagram of the connection circuit 120 in 3rd Embodiment. It is a circuit diagram of the sense circuit 130 in 3rd Embodiment. It is a circuit diagram of the rectifier circuit 140 in 3rd Embodiment. 3 is a circuit diagram of a latch block 180. FIG. 2 is a circuit diagram of a latch circuit 200. FIG. It is a timing diagram for demonstrating operation | movement of 3rd Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to each of the first to third preferred embodiments of the present invention.

  The semiconductor device 10 is a DDR4 (Double Data Rate 4) type synchronous DRAM. As external terminals, clock terminals 11a and 11b, command terminals 12a to 12d, an address terminal 13, a data input / output terminal 14 and a power supply terminal 15v, 15s at least.

  Complementary external clock signals CK and CKB are supplied to the clock terminals 11a and 11b, respectively. The external clock signals CK and CKB are supplied to the internal clock generation circuit 21. The internal clock generation circuit 21 generates an internal clock signal ICLK and supplies it to the DLL circuit 22 and various internal circuits. The DLL circuit 22 receives the internal clock signal ICLK, generates an internal clock signal LCLK for output, and supplies it to the data input / output circuit 80.

  The command terminals 12a to 12d are supplied with a command signal CMD including a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, a chip select signal CS, and the like. These command signals CMD are supplied to the command decoder 31. The command decoder 31 generates various internal commands ICMD by holding, decoding, and counting command signals in synchronization with the internal clock signal ICLK.

  The address terminal 13 is supplied with an address signal ADD composed of a plurality of bits. Address signal ADD is supplied to address latch circuit 41 and latched in synchronization with internal clock signal ICLK. Of the address signal ADD latched by the address latch circuit 41, the row address XA is supplied to the row decoder 51, and the column address YA is supplied to the column decoder 52. Further, the redundant address RA is supplied to the redundant address decoder 55 when programming the antifuse element.

  The row decoder 51 selects one of the word lines WL included in the memory cell array 60 based on the row address XA.

  The row decoder 51 includes an antifuse circuit 51a and an address comparison circuit 51b. However, the antifuse circuit 51a is not limited to being configured in the row decode, and may be configured in a different area in the chip.

  The antifuse circuit 51a is a non-volatile storage element that stores information in a non-volatile manner, and may be, for example, a fuse circuit, a fuse element, or an antifuse element. In particular, the antifuse circuit 51a stores information such as a defective address. When the row address XA corresponding to the defective word line WL is input, the redundant word line RWL is selected instead of the word line WL. As a result, the redundant memory cell RMC can be accessed instead of the defective memory cell MC.

  The row address XA of the defective word line WL is stored in the antifuse circuit 51a, and the row address XA requested to be accessed and the row address XA stored in the antifuse circuit 51a are compared by the address comparison circuit 51b. . The operation of the antifuse circuit 51 a is controlled by the antifuse control circuit 54 and the redundant address decoder 55.

  The memory cell array 60 includes intersecting word lines WL and bit lines BL, and the memory cells MC are arranged at the intersections. The bit line BL is connected to the corresponding sense amplifier SA in the sense amplifier array 53.

  The column decoder 52 selects the bit line BL based on the column address YA.

  The column decoder 52 includes an antifuse circuit 52a and an address comparison circuit 52b. The antifuse circuit 52a is not limited to being configured in the column decode, but may be configured in a different region in the chip. Further, the antifuse circuits 51a and 52a may be configured by a plurality of antifuses arranged in an array.

  The anti-fuse circuit 52a is a non-volatile storage element that stores information in a non-volatile manner, and may be, for example, a fuse circuit, a fuse element, or an anti-fuse element. In particular, the antifuse circuit 52a stores defective address information and the like. When the column address YA corresponding to the defective bit line BL is input, the redundant bit line RBL is selected instead of the bit line BL. As a result, the redundant memory cell RMC can be accessed instead of the defective memory cell MC.

  The column address YA of the defective bit line BL is stored in the antifuse circuit 52a, and the column address YA requested to be accessed is compared with the column address YA stored in the antifuse circuit 52a by the address comparison circuit 52b. . The operation of the antifuse circuit 52 a is controlled by the antifuse control circuit 54 and the redundant address decoder 55.

  The bit line BL or redundant bit line RBL selected by the column decoder 52 is connected to the main amplifier 70 via the sense amplifier SA and the main I / O wiring MIO. The main amplifier 70 amplifies the read data read from the memory cell via the main I / O wiring MIO during the read operation and supplies the read data to the read / write bus RWBS, and the read / write bus RWBS during the write operation. Is supplied to the main I / O wiring MIO.

  The read / write bus RWBS is connected to the data input / output circuit 80. The data input / output circuit 80 serially outputs the read data DQ read in parallel via the read / write bus RWBS from the data input / output terminal 14 and the write input serially input via the data input / output terminal 14. Data DQ is supplied in parallel to the read / write bus RWBS.

  The power supply terminals 15v and 15s are supplied with the power supply potential VDD and the ground potential VSS, respectively. These power supply terminals 15v and 15s are connected to a power supply circuit 90. The power supply circuit 90 generates various internal potentials based on the power supply potential VDD and the ground potential VSS.

  The internal potential generated by the power supply circuit 90 includes internal potentials VPP, VARY, VPERI, and the like. The internal potential VPP is a potential generated by boosting the power supply potential VDD, and is mainly used in the row decoder 51. The internal potential VARY is a potential generated by stepping down the power supply potential VDD, and is mainly used in the sense amplifier row 53. The internal potential VPERI is a potential generated by stepping down the power supply potential VDD, and is used as a power supply potential in most circuit blocks.

  The internal potential VPP is also supplied to the pump circuit 100. The pump circuit 100 is a circuit that generates various potentials used during a connection operation and a load operation with respect to the antifuse circuits 51a and 52a. Here, the “connect operation” is a programming operation in which dielectric breakdown is caused by applying a high voltage across the antifuse element. Whether or not the antifuse element is broken down is determined by a “load operation”.

<First Embodiment>
FIG. 2 is a block diagram for explaining the configuration of the antifuse circuits 51a and 52a and the pump circuit 100 according to the first embodiment.

  As shown in FIG. 2, the antifuse circuits 51 a and 52 a include a load circuit 110, a connect circuit 120, a sense circuit 130, and a rectifier circuit 140.

  The load circuit 110 is a circuit block including an antifuse element, and is used during a connect operation and a load operation. The connect circuit 120 and the sense circuit 130 are used during a connect operation and a load operation, respectively.

  The rectifier circuit 140 is connected between the sense circuit, the load circuit 110, and the connect circuit, and rectifies the current flowing through the fuse element. The rectifier circuit 140 is used to prevent reverse current flow during the load operation.

  The load operation is controlled by a precharge signal PREB and a load signal LOADT supplied from the antifuse control circuit 54. The antifuse control circuit 54 is controlled by a reset signal RSTB that is activated when the semiconductor device 10 is initialized and a verify signal VRFY that is activated when the connect operation is verified.

  The connect operation is controlled by a select signal RSET and a redundant address RA supplied from the redundant address decoder 55. The redundant address decoder 55 is supplied with a redundant address RA (address of the defective word line WL or defective bit line BL) during the connection operation, and by decoding this, the antifuse circuit 51a, The redundant address RA is supplied to 52a.

  The sense circuit 130 senses information read from the antifuse element during the load operation and latches the sensed information to generate defective address information AFBLB that is a determination signal. The defective address information AFBLB is supplied to the address comparison circuits 51b and 52b. The address comparison circuits 51b and 52b compare the defective address information AFBLB with the row address XA or the column address YA, and if they do not match (mis-hit), the word line WL or the bit line based on the row address XA or the column address YA. Select BL. On the other hand, if the defective address information AFBLB matches the row address XA or the column address YA (hits), the redundant word line RWL or the redundant bit line RBL is selected.

  The pump circuit 100 includes a positive pump 101, negative pumps 102 and 103, power switches 104 and 105, and a reference potential generation circuit 106.

  The positive pump 101 is a circuit that generates a high potential VPPC by a pumping operation using the internal potential VPP. The high potential VPPC is, for example, 5.0V. The high potential VPPC generated by the positive pump 101 is supplied to the power switch 104. The power switch 104 supplies either the high potential VPPC or the power supply potential VDD to the power supply wiring VPPSV based on the program signal PGPT. The power supply wiring VPPSV is connected to the connect circuit 120.

  The negative pumps 102 and 103 are circuits that generate negative potentials VBBC and VBBL, respectively, by a pumping operation using the internal potential VPP. The negative potentials VBBC and VBBL are the same potential, for example, −1.0V. Negative potentials VBBC and VBBL generated by the negative pumps 102 and 103 are supplied to the power switch 105. The power switch 105 supplies one of the negative potentials VBBC and VBBL to the power wiring VBBSV based on the program signal PGNT. The power supply wiring VBBSV is connected to the load circuit 110. As an example, the power supply wiring VBBSV may be configured to be commonly connected to a plurality of antifuse elements AF in a configuration in which one antifuse element AF stores one bit.

  The reference potential generation circuit 106 generates a reference potential VREF based on the band gap reference potential VBGR. The band gap reference potential VBGR is a constant potential that does not depend on process variations, temperature changes, voltage changes, and the like. The reference potential VREF is supplied to the non-inverting input node (+) of the differential amplifier 151 included in the bias generation circuit 150. The output node of the differential amplifier 151 is fed back to the inverting input node (−) via the resistance element 152. A bias potential BIAS output from the output node of the differential amplifier 151 is supplied to the sense circuit 130.

  FIG. 3 is a circuit diagram of the load circuit 110, the connect circuit 120, the sense circuit 130, and the rectifier circuit 140 according to the first embodiment.

  As shown in FIG. 3, the load circuit 110 includes an anti-fuse element AF connected between the connection node AFN and the power supply wiring VBBSV, and an N-channel type MOS inserted between the connection node AFN and the connection node AFU. A transistor 111. Sense circuit 130 includes a sense node AFBL.

  The rectifier circuit 140 is connected between the MOS transistor 111 included in the load circuit 110 and the sense node AFBL included in the sense circuit 130. The rectifier circuit 140 includes a transistor 141. The transistor 141 is, for example, a PMOS transistor having a source / drain path between the connection node AFU and the node AFBL and having a gate electrode connected to the ground. In addition, the case where the transistor 141 includes an NMOS transistor having a source / drain path between the connection node AFU and the node AFBL is considered in accordance with a circuit configuration to be used.

  The anti-fuse element AF is insulated in the initial state, and when a high voltage is applied between both ends by the connecting operation, the dielectric breakdown is caused and the conductive state is brought into conduction. The circuit shown in FIG. 3 is a circuit portion corresponding to one antifuse element AF. Therefore, the circuits shown in FIG. 3 are provided in the semiconductor device 10 by the number of antifuse elements AF. The required number of antifuse elements AF is the number of storable redundant addresses × the number of bits of redundant addresses. In addition, the anti-fuse element AF may be required for the enable bit.

  The transistor 111 is a switch for controlling the connection between the antifuse element AF and the connection node AFU, and a load signal LOADT is supplied to the gate electrode. The substrate of the transistor 111 is connected to the power supply wiring VBBSV.

  The load signal LOADT is a signal that is activated to a high level during the load operation. During the load operation, the connection node AFU is connected to the power supply wiring VBBSV via the antifuse element AF. The connection node AFU is connected to a sense node AFBL in the sense circuit 130 through a rectifier circuit 140 including a P-channel MOS transistor 141. The gate electrode of the transistor 141 is fixed to the ground potential VSS, and the sense node AFBL does not become a negative potential even when the connection node AFU becomes a negative potential.

  The connect circuit 120 includes a P-channel MOS transistor 121 connected between the power supply line VPPSV and the connection node AFN. The gate electrode of transistor 121 receives the output signal of NAND gate circuit 122 that receives select signal RSET and the corresponding bit of redundant address RA. The select signal RSET is a signal assigned for each redundant address. When there are M + 1 redundant addresses that can be stored, the M + 1 bit select signal RSET is used. In the connect operation corresponding to the predetermined select signal RSET, if the logical level of the bit corresponding to the redundant address RA is high, the antifuse element AF is connected to the power supply wiring VPPSV.

  The sense circuit 130 includes a latch circuit in which an inverter circuit composed of a P-channel MOS transistor 131 and an N-channel MOS transistor 132 and an inverter circuit 133 that is a determination circuit are connected in a circulating manner. An input node of inverter circuit 133 is connected to sense node AFBL. The source of the transistor 131 is supplied with the internal potential VPERI, and the source of the transistor 132 is supplied with the ground potential VSS. The internal potential VPERI is, for example, 1.0V. A voltage (1.0 V) between the internal potential VPERI and the ground potential VSS is also used for the operation power supply of the inverter circuit 133.

  The P-channel type bias transistor 134 is connected between the transistor 131 and the sense node AFBL. The gate electrode of the bias transistor 134 receives the bias potential BIAS, and the current control circuit including the transistors 131 and 134 controls the amount of the sense current flowing through the sense node AFBL according to the bias potential BIAS.

  The P-channel type precharge transistor 135 is connected between the power supply line to which the internal potential VPERI is supplied and the sense node AFBL. The gate electrode of precharge transistor 135 receives precharge signal PREB. When the precharge signal PREB is activated to the low level, the sense node AFBL is precharged to the VPERI level (1.0 V).

  FIG. 4 is a timing chart for explaining the operation of the first embodiment.

  In the standby period T10, the program signals PGPT and PGNT are both at a low level. Therefore, the power supply potential VPPSV is supplied with the power supply potential VDD, and the power supply wiring VBBSV is supplied with the negative potential VBBL (−1. 0V) is supplied.

  In the connection period T11, the program signals PGPT and PGNT change to high level. Accordingly, the high potential VPPC (5.0 V) is supplied to the power supply wiring VPPSV, and the negative potential VBBC (−1.0 V) is supplied to the power supply wiring VBBSV via the negative pump 102. In this state, the select signal RSET sequentially changes to the high level, and each bit of the redundant address RA corresponding thereto is input to the connect circuit 120. The example shown in FIG. 4 shows a case where the select signal RSET is M + 1 bits (RSET <0> to RSET <M>) and the redundant address RA is n + 1 bits (RA <0> to RA <N>). .

  As a result, if the relevant bit of the redundant address RA is at a high level, a connect voltage of about 6 V is applied to both ends of the antifuse element AF shown in FIG. 3, so that the insulating film included in the antifuse element AF is formed. Breaks down. This operation is repeatedly executed until all redundant addresses RA are programmed by sequentially switching the select signal RSET to be activated.

  In the precharge period T12, the program signal PGNT returns to the low level, the verify signal VRFY is activated to the high level, and the precharge signal PREB is activated to the low level. As a result, the sense node AFBL in the sense circuit 130 is precharged to the VPERI level (1.0 V).

  In the verify period T13, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VBBSV via the rectifier circuit 140 and the antifuse element AF. Therefore, a sense current determined by the bias potential BIAS flows through the anti-fuse element AF, and the potential of the sense node AFBL changes according to the amount of the current.

  Here, when the antifuse element AF is not connected (in an insulated state), almost no sense current flows through the antifuse element AF, so that the potential of the connection node AFU is precharged as indicated by the symbol A. Maintain state.

  On the other hand, when the anti-fuse element AF is connected (when it is in a conductive state), a sense current flows through the anti-fuse element AF, so that the potential of the connection node AFU is greatly reduced as indicated by reference numeral B. .

  Further, when the anti-fuse element AF is connected (when it is in a conductive state), there are (i) a case where the resistance value is relatively high and (ii) a case where the resistance value is sufficiently low.

  (I) When the resistance value is relatively high even though the antifuse element AF is connected (conductive state), that is, when the antifuse element AF is in a semi-connected state, the sense current flowing through the antifuse element AF is Since it is small, the potential of the connection node AFU gradually decreases as indicated by the symbol C. When the potential of the sense node AFBL falls below the logic threshold value of the sense circuit 130, the inverter circuit 133 is inverted and the level of the sense node AFBL is rapidly lowered via the transistor 132. Thereby, the information read from the antifuse element AF is latched.

  In the present embodiment, in the verification period T13, the voltage applied to both ends of the antifuse element AF is VPERI (1.0 V) −VBBL (−1.0 V), and is about 2 V. As a result, a larger sense current can be secured as compared with the case where the voltage applied across the antifuse element AF is VPERI-VSS (= 1.0 V). For this reason, even in the semi-connected state, the potential of the sense node AFBL can be greatly reduced, and a correct sensing operation is guaranteed.

  (Ii) When the anti-fuse element AF is in a connected state and its resistance value is sufficiently low, as indicated by reference symbol B, the potential of the connection node AFU may rapidly decrease to around −1.0V. .

  In such a case, the rectifier circuit 140 exhibits a function of rectifying the current flowing through the fuse element. That is, since the rectifier circuit 140 is inserted between the sense node AFBL and the connection node AFU, the potential of the sense node AFBL does not drop below the ground potential VSS. Since the gate electrode of the transistor 141 is grounded, the transistor 141 becomes non-conductive when the potential of the connection node AFU rapidly decreases. This prevents the potential of the connection node AFU from becoming the ground voltage or lower. That is, current does not flow backward from the wiring to which the ground potential VSS is supplied (source of the transistor 132) toward the power supply wiring VBBSV.

  Further, in the example in which the VBBSV node shown in FIG. 3 is provided in common to the plurality of read circuits 130 and the corresponding antifuse elements AF, the resistance value is increased from the VBBSV node connected to the element AF having a sufficiently low resistance value. A current flows into the VBBSV node connected to the relatively high element AF, and this flow-in current causes the low potential side of the element AF having a relatively high resistance value to float, so that a sufficient potential difference does not occur at both ends of the element AF, resulting in a read failure. This phenomenon is considered. However, since the corresponding rectifier circuit 140 (transistor 141) becomes non-conductive in the element AF having a sufficiently low resistance value, current application is prevented, so that such a phenomenon can be prevented.

  In the reconnect period T14, if there is an antifuse element AF that is not correctly connected as a result of the verify operation, the reconnect operation is performed on the antifuse element AF.

  In the waiting period T15, a series of programming is completed.

  Next, after the programming is completed, information is read from the antifuse element AF every time the semiconductor device 10 is reset.

  In the reset period T16, the reset signal RSTB is activated to a low level.

  In the precharge period T17, the precharge signal PREB is activated to a low level. As a result, the sense node AFBL in the sense circuit 130 is precharged to the VPERI level (1.0 V).

  In the load period T18, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VBBSV via the rectifier circuit 140 and the antifuse element AF.

  The operation in the load period T18 is the same as the operation in the verify period T13 described above, and a difference occurs in the potential of the sense node AFBL depending on whether or not the antifuse element AF is connected.

  In the present embodiment, in the load period T18, the voltage applied across the antifuse element AF is about 2V, and a large sense current can be secured. Therefore, even in the half-connected state, the sense node AFBL Can be sufficiently lowered.

  Moreover, even when the anti-fuse element AF is in the connected state and its resistance value is sufficiently low, the power supply wiring VBBSV is supplied from the wiring (source of the transistor 132) supplied with the ground potential VSS due to the presence of the rectifier circuit 140. The current does not flow backward toward.

  As described above, according to the first embodiment, information held in the antifuse element AF can be read with high sensitivity while preventing a backflow of current. The above effect can also be obtained by connecting the source of the transistor 132 to the power supply wiring VBBSV. In this case, not only the design of the sense circuit 130 needs to be changed but also the transistor 132 is applied. Since the voltage increases, the leakage current of the transistor 132 increases during the sensing operation. Since the leakage current of the transistor 132 becomes a noise component with respect to the sense current, the read sensitivity is lowered. Considering these points, it is desirable to adopt the configuration of the above embodiment, instead of connecting the source of the transistor 132 to the power supply wiring VBBSV.

<Modification of First Embodiment>
FIG. 5 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, and a rectifier circuit 140 according to a modification of the first embodiment.

  The modification shown in FIG. 5 is the same as the circuit shown in FIG. 3 except that the polarities are all reversed with respect to the circuit shown in FIG. That is, P-channel MOS transistors 112 and 137 are used instead of the N-channel MOS transistors 111 and 132, and N-channel MOS transistors 123 and 137 are used instead of the P-channel MOS transistors 121, 131, 134, 135, and 141. 136, 138, 139, 142 are used.

  The rectifier circuit 140 is connected between the input nodes of the MOS transistor 112 included in the load circuit 110 and the inverter circuit 133 included in the sense circuit 130. The rectifier circuit 140 includes an NMOS transistor having a source / drain path between the input nodes of the MOS transistor 112 and the non-inverter circuit 133. The gate electrode of the transistor 142 is fixed to a fixed potential, for example, the internal potential VPERI.

  During the load operation, a potential (for example, 2.0 V) higher than the internal potential VPERI is applied to the power supply wiring VBBSV. Thereby, even when the antifuse element AF is connected and its resistance value is sufficiently low, current does not flow backward from the power supply wiring VBBSV to the source of the transistor 136. Thus, even when the polarity is reversed, the same effect can be obtained.

<Second Embodiment>
FIG. 6 is a block diagram for explaining the configuration of the antifuse circuits 51a and 52a and the pump circuit 100 according to the second embodiment.

  As shown in FIG. 6, in this embodiment, the bias generation circuit 150 is deleted, and the negative pump 102 and the reference potential generation circuit 106 are deleted from the pump circuit 100. Further, power switches 107 and 108 are used instead of the power switches 104 and 105. Further, a verify bit selection circuit 160 is added to the antifuse circuits 51a and 52a.

  The power switch 107 selects the high potential VPPC (6.0 V) or the negative potential VBB (−1.0 V) on the power wiring VBBSV in response to the program signal PGT, and outputs this to the power wiring VPPSV. The power switch 108 selects the negative potential VBB (−1.0 V) or the internal potential VPP (3.0 V) on the power wiring VBBSV in response to the program signal PGT, and outputs this as the connect signal AFREF. Since the other configuration is basically the same as that of the first embodiment shown in FIG. 2, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 7 is a circuit diagram of the load circuit 110, the connect circuit 120, the sense circuit 130, the rectifier circuit 140, and the verify bit selection circuit 160 according to the second embodiment.

  The rectifier circuit 140 according to the second embodiment is connected between the MOS transistor 111 included in the load circuit 110 and the sense node AFBL included in the sense circuit 130. The rectifier circuit 140 includes a transistor 141. The transistor 141 is, for example, a PMOS transistor having a source / drain path between the connection node AFU and the node AFBL and having a gate electrode connected to the ground. In addition, the case where the transistor 141 includes an NMOS transistor having a source / drain path between the connection node AFU and the node AFBL is considered in accordance with a circuit configuration to be used.

  As shown in FIG. 7, the load circuit 110 according to the second embodiment is inserted between the anti-fuse element AF connected between the power supply line VPPSV and the connection node AFN, and between the connection node AFN and the connection node AFU. N-channel MOS transistors 113 and 111 are provided. The gate electrode of the transistor 113 is fixed to the internal potential VPP, and its substrate is connected to the power supply wiring VBBSV.

  The connection circuit 120 according to the second embodiment includes N-channel MOS transistors 124 and 125 connected between a connection node AFN and a wiring to which a ground potential VSS is supplied. A connect signal AFREF activated during the connect operation is supplied to the gate electrode of the transistor 124. Further, the output signal of the NAND gate circuit 126 receiving the select signal RSET and the corresponding bit of the redundant address RA is supplied to the gate electrode of the transistor 125.

  In the sense circuit 130 according to the second embodiment, an N-channel type enable transistor 231 is added instead of the bias transistor 134 being omitted. A precharge signal PREB is supplied to the gate electrode of the enable transistor 231. With this configuration, the current control circuit including the transistors 132 and 231 is activated during a period in which the precharge signal PREB is at a high level.

  The verify bit selection circuit 160 includes a P-channel MOS transistor 161 connected between the wiring to which the internal potential VPERI is supplied and the sense circuit 130, and a P-channel MOS transistor 162 connected in series between them. , 163. The bit corresponding to the redundant address RA is supplied to the gate electrode of the transistor 162, and the enable signal ENB and its inverted signal are supplied to the gate electrodes of the transistors 161 and 163, respectively. With this configuration, when the enable signal ENB is activated at a low level, or when the enable signal ENB is deactivated at a high level and the corresponding bit of the redundant address RA is at a low level, the verify is performed. The bit selection circuit 160 supplies the internal potential VPERI to the sense circuit 130.

  FIG. 8 is a circuit diagram of a load circuit 110, a connect circuit 120, a sense circuit 130, a rectifier circuit 140, and a verify bit selection circuit 160 according to a modification of the second embodiment.

  The modification shown in FIG. 8 is shown in FIG. 7 in that an N-channel MOS transistor 127 is added to the connect circuit 120 and the connection order of the transistors 132 and 231 included in the sense circuit 130 is reversed. It is different from the circuit. Since the other configuration is the same as that of the circuit shown in FIG. 7, the same reference numerals are given to the same elements, and redundant description is omitted.

  The source of the transistor 127 is connected to the source of the transistor 124, and the connect signal AFREF and its inverted signal are supplied to the drain and gate electrodes, respectively. With this configuration, the source of the transistor 124 is fixed at the low level (the ground potential VSS) during the period in which the connect signal AFREF is inactivated to the low level. The operation of the sense circuit 130 is the same as that of the circuit shown in FIG.

  FIG. 9 is a timing chart for explaining the operation of the second embodiment.

  In the standby period T20, the program signal PGT is at a low level, and therefore, the negative potential VBB (−1.0 V) is supplied to the power supply wirings VPPSV and VBBSV.

  In the connection period T21, the program signal PGT changes to a high level. As a result, the high potential VPPC (6.0 V) is supplied to the power supply wiring VPPSV, and the ground potential VSS (0 V) is supplied to the power supply wiring VBBSV. The level of the connect signal AFREF is the internal potential VPP (3.0 V). In this state, the select signal RSET sequentially changes to the high level, and each bit of the redundant address RA corresponding thereto is input to the connect circuit 120. The example shown in FIG. 9 also shows the case where the select signal RSET is M + 1 bits (RSET <0> to RSET <M>) and the redundant address RA is n + 1 bits (RA <0> to RA <N>). ing.

  As a result, if the relevant bit of the redundant address RA is at a high level, a connection voltage of about 6 V is applied to both ends of the antifuse element AF shown in FIG. 7 or FIG. 8, thereby being included in the antifuse element AF. The insulation film breaks down. This operation is repeatedly executed until all redundant addresses RA are programmed by sequentially switching the select signal RSET to be activated.

  The above operation may be repeatedly performed on the antifuse elements AF that are not correctly connected after the verify operation. The verify operation is performed by activating the sense circuit 130 by setting the enable signal ENB to a low level.

  In the waiting period T22, a series of programming is completed.

  After the programming is completed, information is read from the antifuse element AF every time the semiconductor device 10 is reset.

  In the reset period T23, when the reset signal RSTB is activated to the low level, the precharge signal PREB is activated to the low level in the subsequent precharge period T24. As a result, the sense node AFBL in the sense circuit 130 is precharged to the VPERI level (1.0 V).

  In the load period T25, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VPPSV via the rectifier circuit 140 and the antifuse element AF. Therefore, a sense current flows through the antifuse element AF, and the potential of the sense node AFBL changes according to the amount of the current. At this time, a voltage of about 2 V is applied to both ends of the antifuse element AF, as in the first embodiment.

  When the antifuse element AF is not connected (in an insulated state), almost no sense current flows through the antifuse element AF, so that the potential of the connection node AFU is in a precharged state as indicated by symbol A. To maintain. On the other hand, when the anti-fuse element AF is connected (when it is in a conductive state), a sense current flows through the anti-fuse element AF, so that the potential of the connection node AFU is greatly reduced as indicated by reference numeral B. .

  Further, when the antifuse element AF is in a semi-connected state, the sense current flowing through the antifuse element AF is small, so that the potential drop of the connection node AFU is moderate as shown by reference C. Also in the embodiment, since a voltage of about 2 V is applied to both ends of the antifuse element AF during the load operation, it is possible to perform the sense operation with higher sensitivity.

  Further, when the anti-fuse element AF is in the connected state and its resistance value is sufficiently low, the potential of the connection node AFU rapidly decreases to around −1.0 V as indicated by reference symbol C, but this embodiment In FIG. 5, since the rectifier circuit 140 is inserted between the sense node AFBL and the connection node AFU, the potential of the sense node AFBL does not fall below the ground potential VSS. That is, current does not flow backward from the wiring (source of the transistor 132) supplied with the ground potential VSS toward the power supply wiring VPPSV.

<Third Embodiment>
FIG. 10 is a block diagram for explaining the configuration of the antifuse circuits 51a and 52a and the pump circuit 100 according to the third embodiment.

  As shown in FIG. 10, in this embodiment, the antifuse circuits 51 a and 52 a are configured by an antifuse array 170 and a latch block 180. Since the other configuration is basically the same as that of the second embodiment shown in FIG. 6, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 11 is a circuit diagram of the antifuse array 170.

  As shown in FIG. 11, the antifuse array 170 includes a plurality of load circuits 110 arranged in an array. In the example shown in FIG. 11, a plurality of load circuits 110 form an array of N + 1 rows × M + 1 columns. Each row corresponds to each bit of the redundant address RA, and each column corresponds to one redundant address RA.

  The antifuse array 170 includes a plurality of connect circuits 120, a sense circuit 130, and a rectifier circuit 140 that are commonly assigned to a plurality of load circuits 110 arranged in the row direction, and a plurality of loads arranged in the column direction. A driver circuit 191 assigned to each of the circuits 110 is provided.

  The rectifier circuit 140 is connected between the corresponding connection node AFU and the sense node AFBL. For example, the rectifier circuit 140 <0> is connected between the connection node AFU <0> and the sense node AFBL <0>. The configuration of the rectifier circuit 140 will be described in detail with reference to FIG.

  Among the plurality of load circuits 110, the plurality of load circuits 110 arranged in the row direction are commonly connected to the respective connection nodes AFU. Thus, the plurality of load circuits 110 arranged in the row direction are commonly connected to the corresponding sense circuit 130 via the corresponding rectifier circuit 140. In FIG. 11, N + 1 connection nodes AFU are represented as AFU <0> to AFU <N>.

  The driver circuit 191 selects a plurality of load circuits 110 arranged in the column direction among the plurality of load circuits 110. The driver circuit 191 generates a program signal WLP and a read signal WLR based on the corresponding select signal RSET and main word signal MWLR, and supplies these signals in common to the plurality of load circuits 110 arranged in the column direction. In FIG. 11, M + 1 select signals RSET are expressed as RSET <0> to RSET <M>, and M + 1 main word signals MWLR are expressed as MWLR <0> to MWLR <M>.

  The main word signal MWLR is generated by an AND gate circuit 193 that receives the load signal LOADT and the output signal of the corresponding register circuit 192. The register circuit 192 is provided corresponding to each column, and forms a shift register by being cascaded as shown in FIG. The load clock signal LOADCLK is supplied to the clock node of the register circuit 192, whereby the latch data is sequentially shifted in synchronization with the clocking of the load clock signal LOADCLK. These register circuits 192 are reset when the load signal LOADT is inactivated to a low level.

  FIG. 12 is a circuit diagram of the driver circuit 191.

  As shown in FIG. 12, the driver circuit 191 includes an OR gate circuit 194 that receives the main word signal MWLR and the select signal RSET, and an AND gate circuit 195 that receives the select signal RSET and the program signal PGT.

  The output signal of the OR gate circuit 194 is output as a read signal WLR via the buffer circuit 196. Since the buffer circuit 196 is supplied with the internal potential VPP (3.0 V) and the potential on the power supply wiring VBBSV as the operation power supply, the activation level of the read signal WLR becomes the internal potential VPP (3.0 V).

  On the other hand, the output signal of the AND gate circuit 195 is output as the program signal WLP via the buffer circuit 197. Since the power supply wirings VPPSV and VBBSV are connected to the buffer circuit 197, the level of the program signal WLP during the connection operation becomes the high potential VPPC (6.0 V) on the power supply wiring VPPSV, and the program signal during the load operation The level of WLP becomes a negative potential VBB (−1.0 V) on the power supply wiring VBBSV.

  FIG. 13 is a circuit diagram of the load circuit 110 in the third embodiment.

  As shown in FIG. 13, the load circuit 110 according to the third embodiment includes an antifuse element AF and a transistor 111 connected in series. A program signal WLP is supplied to one end of the antifuse element AF, and a read signal WLR is supplied to the gate electrode of the transistor 111. A power supply wiring VBBSV is connected to the substrate of the transistor 111.

  The drain of the transistor 111 is connected to the connection node AFU. As shown in FIG. 11, the connection nodes AFU are commonly connected in a plurality of load circuits 110 arranged in the row direction.

  FIG. 14 is a circuit diagram of the connect circuit 120 in the third embodiment.

  As shown in FIG. 14, the connect circuit 120 according to the third embodiment includes transistors 124 and 125 connected in series between a connection node AFU and a wiring to which a ground potential VSS is supplied. A connect signal AFREF is supplied to the gate electrode of the transistor 124, and a bit corresponding to the redundant address RA is supplied to the gate electrode of the transistor 125. Further, the substrate of the transistor 124 is connected to the power supply wiring VBBSV, thereby preventing a high voltage from being applied to the transistor 125.

  FIG. 15 is a circuit diagram of the sense circuit 130 in the third embodiment.

  As shown in FIG. 15, the sense circuit 130 according to the third embodiment is different from the sense circuit 130 shown in FIG. 3 in that an N-channel MOS transistor 232 is added instead of removing the bias transistor 134. Is different. Since the other points are the same as those of the sense circuit 130 shown in FIG. 3, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The transistor 232 is inserted between the sense node AFBL and the input node of the inverter circuit 133, and a load signal LOADT is supplied to its gate electrode. Therefore, when the load signal LOADT is activated to a high level, the sense node AFBL and the input node of the inverter circuit 133 are short-circuited.

  FIG. 16 is a circuit diagram of the rectifier circuit 140 in the third embodiment.

  As shown in FIG. 16, the rectifier circuit 140 in the third embodiment includes a transistor 141 connected between a connection node AFU and a sense node AFBL. That is, it has the same circuit configuration as the rectifier circuit 140 shown in FIG. The gate electrode of the transistor 141 is fixed to the ground potential VSS, and the substrate is connected to the power supply wiring VBBSV.

  The circuit configuration of the antifuse array 170 has been described above. When programming the antifuse array 170 having such a configuration, one or more antifuse elements are used using a plurality of connect circuits 120 in a state where any column is selected using the driver circuit 191. A high voltage is applied across the AF. Thereby, programming is performed in units of columns. When reading information from the antifuse array 170, the driver circuit 191 activates the load signal LOADT in a state where any column is selected, thereby causing a sense current to flow through the plurality of antifuse elements AF. As a result, a loading operation is performed in units of columns.

  The defective address information AFBLB read by the load operation is supplied to the latch block 180 shown in FIG.

  FIG. 17 is a circuit diagram of the latch block 180.

  As shown in FIG. 17, the latch block 180 includes a plurality of latch circuits 200 arranged in an array. In the example shown in FIG. 17, a plurality of latch circuits 200 constitutes an array of N + 1 rows × M + 1 columns. Each row corresponds to each bit of the redundant address RA, and each column corresponds to one redundant address RA.

  Among the plurality of latch circuits 200, a plurality of latch circuits 200 arranged in the row direction are commonly supplied with corresponding bits of the defective address information AFBLB. In FIG. 17, N + 1-bit defective address information AFBLB is expressed as AFBLB <0> to AFBLB <N>.

  The selection of the plurality of latch circuits 200 arranged in the column direction among the plurality of latch circuits 200 is performed by the main word signal MWLR. The circuit for generating the main word signal MWLR has already been described.

  FIG. 18 is a circuit diagram of the latch circuit 200.

  As shown in FIG. 18, the latch circuit 200 includes two inverter circuits 201 and 202 that are connected in a circulating manner, a transistor 203 for inputting a corresponding bit of the defective address information AFBLB, and a transistor that outputs the latched information. 204.

  A corresponding main word signal MWLR is supplied to the gate electrode of the transistor 203. As a result, each bit of the defective address information AFBLB read from the antifuse array 170 is transferred to the corresponding latch circuit 200.

  The output signal REDX is supplied to the gate electrode of the transistor 204. The transistor 204 is connected between the inverter circuits 201 and 202 and the output line RX. Thus, when the output signal REDX is activated, the information held in the latch circuit 200 is output to the output line RX. . As shown in FIG. 17, the plurality of latch circuits 200 arranged in the row direction share an output line RX. In FIG. 17, N + 1 output lines RX are represented as RX <0> to RX <N>. The M + 1-bit output signal REDX is expressed as REDX <0> to REDX <M>.

  With this configuration, when a load operation is performed on the antifuse array 170, the defective address information AFBLB read from the array-shaped load circuit 110 is successively transferred to the array-shaped latch circuit 200. The defective address information AFBLB transferred to the latch circuit 200 is supplied to the address comparison circuits 51b and 52b via the output line RX.

  Next, the operation of the third embodiment will be described.

  FIG. 19 is a timing chart for explaining the operation of the third embodiment.

  In the standby period T30, the program signal PGT is at a low level, and therefore, the negative potential VBB (−1.0 V) is supplied to the power supply wirings VPPSV and VBBSV.

  In the connection period T31, the program signal PGT changes to a high level. As a result, the high potential VPPC (6.0 V) is supplied to the power supply wiring VPPSV, and the ground potential VSS (0 V) is supplied to the power supply wiring VBBSV. The level of the connect signal AFREF is the internal potential VPP (3.0 V). Then, while the predetermined main word signal MWLR is activated, the select signal RSET is sequentially set to the high level, and each bit of the redundant address RA corresponding thereto is input to the plurality of connect circuits 120. As a result, the redundant address RA is programmed in the plurality of load circuits 110 constituting the selected column.

  Such an operation is performed for all the columns by switching the selection of the main word signal MWLR. Thereby, each column of the antifuse array 170 is programmed with a corresponding redundant address RA. The above operation may be repeatedly performed on the antifuse elements AF that are not correctly connected after the verify operation.

  After the programming is completed, information is read from the antifuse element AF every time the semiconductor device 10 is reset.

  In the reset period T33, the reset signal RSTB is activated to a low level.

  In the precharge period T34, the precharge signal PREB is activated to a low level. As a result, the sense nodes AFBL in all the sense circuits 130 are precharged to the VPERI level (1.0 V).

  In the load period T35, the precharge is released and the load signal LOADT is activated to a high level. As a result, the sense node AFBL is connected to the power supply wiring VPPSV via the rectifier circuit 140 and the antifuse element AF. Therefore, a sense current flows through the antifuse element AF, and the potential of the sense node AFBL changes according to the amount of the current. At this time, a voltage of about 2 V is applied to both ends of the antifuse element AF, as in the first and second embodiments.

  When the antifuse element AF is not connected (in an insulated state), almost no sense current flows through the antifuse element AF, so that the potential of the connection node AFU is in a precharged state as indicated by symbol A. To maintain. On the other hand, when the anti-fuse element AF is connected (when it is in a conductive state), a sense current flows through the anti-fuse element AF, so that the potential of the connection node AFU is greatly reduced as indicated by reference numeral B. .

  Further, when the antifuse element AF is in a semi-connected state, the sense current flowing through the antifuse element AF is small, so that the potential drop of the connection node AFU is moderate as shown by reference C. Also in the embodiment, since a voltage of about 2 V is applied to both ends of the antifuse element AF during the load operation, it is possible to perform the sense operation with higher sensitivity.

  Further, when the anti-fuse element AF is in the connected state and its resistance value is sufficiently low, the potential of the connection node AFU rapidly decreases to around −1.0 V. In this embodiment, the sense node AFBL Since the rectifier circuit 140 is inserted between the connection node AFU and the potential of the sense node AFBL does not drop below the ground potential VSS. That is, current does not flow backward from the wiring (source of the transistor 132) supplied with the ground potential VSS toward the power supply wiring VPPSV.

  The defective address information AFBLB read in this way is written in a predetermined latch circuit 200 included in the latch block 180. Therefore, if the above operation is sequentially performed on each column, the defective address information AFBLB written on each column is transferred to the latch block 180 one after another. In the example shown in FIG. 19, all transfer operations are completed in the precharge period T36 and the load period T37 by repeating the load operation M + 1 times.

  Even when the load circuits 110 including the antifuse elements AF are arranged in an array as in the third embodiment described above, it is possible to obtain the same effects as those in the first and second embodiments. Become.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, the configuration of the rectifier circuit 140 of the above embodiment and the circuit related thereto has been described as an example when applied to an antifuse element. However, application to a nonvolatile memory element such as a fuse circuit or a fuse element is also considered. obtain.

  For example, in the above embodiment, the case where the present invention is applied to a DRAM (Dynamic Random Access Memory) has been described as an example. However, the application target of the present invention is not limited to this, and PCM (Phase Change Memory), ReRAM (Resistive Random Access Memory), MRAM (Magnetrogenic Random Access Memory), STT-RAM (Spin Transfer Torque Memory), and other types of semiconductor devices that can be used as a semiconductor memory such as flash memory The present invention can also be applied to logic semiconductor devices.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11a, 11b Clock terminal 12a-12d Command terminal 13 Address terminal 14 Data input / output terminal 15v, 15s Power supply terminal 21 Internal clock generation circuit 22 DLL circuit 31 Command decoder 41 Address latch circuit 51 Row decoder 51a, 52a Antifuse circuit 51b, 52b Address comparison circuit 52 Column decoder 53 Sense amplifier row 54 Redundant address decoder 55 Redundant address decoder 60 Memory cell array 70 Main amplifier 80 Data input / output circuit 90 Power supply circuit 100 Pump circuit 101 Positive pump 102, 103 Negative pump 104, 105 Power supply Switch 106 Reference potential generation circuit 107, 108 Power switch 110 Load circuit 111, 113, 123-125, 127, 132, 136, 142, 203, 204, 232 N-channel MOS transistors 112, 121, 131, 137, 141, 161-163 P-channel MOS transistors 133 Inverter circuit 120 Connect circuit 122 NAND gate circuit 126 AND gate circuit 130 Sense circuits 134, 138 Bias transistors 135 and 139 Precharge transistor 140 Rectifier circuit 150 Bias generation circuit 151 Differential amplifier 152 Resistive element 160 Verify bit selection circuit 170 Antifuse array 180 Latch block 191 Driver circuit 192 Register circuits 193 and 195 AND gate circuit 194 OR gate circuit 196, 197 Buffer circuit 200 Latch circuit 201, 202 Inverter circuit 231 Enable transistor AF Antifuse element AFBL Sense node AFN, AFU Connection node BL Bit line MC Memory cell RBL Redundant bit line RMC Redundant memory cell RWBS Read / write bus RWL Redundant word line RX Output line SA Sense amplifiers VPPSV, VBBSV Power line WL Word line

Claims (18)

First to third power supply lines to which first to third potentials are respectively supplied;
A determination circuit that generates a determination signal based on the potential of the sense node;
A first current control circuit connected between the first power supply wiring and the sense node, the conduction state of which is controlled based on the determination signal;
A second current control circuit connected between the second power supply wiring and the sense node, the conduction state of which is controlled based on the determination signal;
A fuse element connected between the third power supply wiring and the sense node;
And a rectifier circuit for rectifying a current flowing through the fuse element.   The semiconductor device according to claim 1, wherein the rectifier circuit includes a first transistor connected in series to the fuse element.   The first transistor is a PMOS transistor having a source / drain path between the sense node and the fuse element and a gate electrode connected to the second power supply line. The semiconductor device according to claim 2.   3. The semiconductor device according to claim 2, wherein the first transistor is an NMOS transistor having a source / drain path between the sense node and the fuse element.   5. The semiconductor device according to claim 1, wherein a potential difference between the first potential and the third potential is larger than a potential difference between the first potential and the second potential.   6. The semiconductor device according to claim 1, wherein the determination circuit includes an inverter circuit having an input node connected to the sense node.   The semiconductor device according to claim 6, further comprising a precharge circuit that precharges the sense node to the first potential. The first current control circuit includes a second transistor of a first conductivity type connected between the first power supply line and the sense node, and supplied with the determination signal to a gate electrode.
The second current control circuit includes a third transistor of a second conductivity type connected between the second power supply line and the sense node, and supplied with the determination signal to a gate electrode. The semiconductor device according to claim 1.   9. The semiconductor device according to claim 8, wherein the first current control circuit further includes a bias transistor that is connected in series to the first transistor and controls a current flowing through the sense node.   10. The semiconductor according to claim 8, wherein the second current control circuit further includes an enable transistor that is connected in series to the second transistor and is rendered conductive during a sensing operation by the determination circuit. apparatus.   2. A plurality of fuse elements are assigned to a sense circuit including the determination circuit, the first current control circuit, the second current control circuit, and the rectifier circuit. The semiconductor device according to any one of 10.   The semiconductor device according to claim 1, wherein the second potential is a ground potential, and the third potential is a negative potential lower than the ground potential.   The semiconductor device according to claim 1, wherein the second potential is a power supply potential higher than a ground potential, and the third potential is higher than the power supply potential. A memory cell assigned a predetermined address;
A redundant memory cell that is replaced when the memory cell is defective,
The semiconductor device according to claim 1, wherein the fuse element stores a logic level of a bit constituting the predetermined address.   The semiconductor device according to claim 1, wherein the fuse element is an antifuse. First to third power supply lines to which first to third potentials are respectively supplied;
A determination circuit that generates a determination signal based on the potential of the sense node;
A first conductivity type first transistor connected between the first power supply line and the sense node and having the determination signal supplied to a gate electrode;
A second conductivity type second transistor connected between the second power supply line and the sense node and supplied with the determination signal to a gate electrode;
An antifuse element connected between the third power supply wiring and the sense node;
A third transistor of the first conductivity type connected in series to the antifuse element,
A semiconductor device, wherein a potential difference between the first potential and the third potential is larger than a potential difference between the first potential and the second potential.   The semiconductor device according to claim 16, wherein the determination circuit includes an inverter circuit having an input node connected to the sense node and an output node connected to the gate electrodes of the first and second transistors. .   18. The semiconductor device according to claim 17, wherein the inverter circuit operates using a potential difference between the first potential and the second potential as a power supply voltage.

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