CN221202509U - High-precision low-jitter clock oscillator circuit - Google Patents
High-precision low-jitter clock oscillator circuit Download PDFInfo
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- CN221202509U CN221202509U CN202322778251.XU CN202322778251U CN221202509U CN 221202509 U CN221202509 U CN 221202509U CN 202322778251 U CN202322778251 U CN 202322778251U CN 221202509 U CN221202509 U CN 221202509U
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Abstract
The utility model discloses a high-precision low-jitter clock oscillator circuit which comprises a first current source I1, a second current source I2, a variable resistor R, a capacitor C, a discharge transistor M0, a comparator, a switch group, a frequency divider and an inverter, wherein the comparator, the frequency divider and the inverter are sequentially connected, the output end of the frequency divider outputs a first switch control signal, the output end of the inverter outputs a second switch control signal, the first switch control signal and the second switch control signal are used for controlling the state of the switch group, and the switch group comprises a first switch state and a second switch state. The utility model can eliminate the influence of low-frequency noise on the output signal, and obtain the clock oscillator with high precision, good stability and low jitter.
Description
Technical Field
The utility model relates to the field of integrated circuit design, in particular to a high-precision low-jitter clock oscillator circuit capable of eliminating low-frequency noise.
Background
With the development of the internet of things, the requirement on the standby time of the battery is higher and higher, and a lower power consumption scheme design is required. The wireless transceiver application can save power consumption by adopting a timing wake-up mode, which puts higher requirements on the precision of a timing clock. Passive crystal oscillators can provide a stable and high precision clock source but are costly, and to overcome this disadvantage more and more on-chip RC oscillator schemes are used, but often not very accurate, and although the steps of calibration can be small using calibration techniques, it is difficult to calibrate the frequency to the target frequency due to the presence of noise.
As shown In fig. 1, the conventional relaxation RC oscillator assumes that the current values of the first current source I1 and the second current source 12 are I, in1 and In2 are noise currents respectively, a variable resistor is R, a fixed capacitor is C, a discharge transistor is M0, a resistance noise voltage is Vn1, an equivalent input noise voltage of a comparator is Vn2, an output of the comparator is Vout, and a delay of the comparator is Tdelay. Irrespective of the noise effect, the output frequency relationship of the oscillator is derived as follows:
I.e.
Since R is adjustable, the output frequency is theoretically determined by the adjustable step accuracy of R, but due to the presence of noise, equation (1) is rewritten as:
the delay of the comparator is negligible compared with the period of the oscillator, the current noise is far smaller than the current value, i.e I1 > In1, and the simplified formula (3) is:
Can be simplified into:
As can be seen from (5), the oscillator output frequency fluctuates due to random fluctuations In Vn1, vn2, in2, assuming that the parameter R, C does not change with time t, and the noise Vn1, vn2, in2 is a function of time t. The resistance noise Vn1 is white noise, the low frequency band of the current source and the comparator noise is mainly flicker noise, the high frequency is mainly thermal noise, the noise is averaged due to the fact that the clock period is counted for a plurality of times, but the low frequency flicker noise is difficult to eliminate by counting for a plurality of times due to the fact that the counting times are limited.
Disclosure of utility model
The utility model aims to: in order to solve the problem that the precision of an RC oscillator is limited due to the existence of low-frequency noise in the prior art, the utility model provides a high-precision low-jitter clock oscillator circuit.
The technical scheme is as follows: the utility model provides a high-precision low-jitter clock oscillator circuit which comprises a first current source I1, a second current source I2, a variable resistor R, a capacitor C, a discharge transistor M0, a comparator, a switch group, a frequency divider and an inverter, wherein the comparator, the frequency divider and the inverter are sequentially connected, the output end of the frequency divider outputs a first switch control signal, the output end of the inverter outputs a second switch control signal, and the first switch control signal and the second switch control signal are used for controlling the switch state of the switch group;
The switch group comprises a current source switch group and a comparator switch group, the current source switch group is connected between the first current source I1 and the second current source I2, the variable group R and the capacitor C, and the comparator switch group is positioned in the comparator;
The comparator comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein the connection point of the drain electrode of the first transistor M1 and the drain electrode of the third transistor M3 is a node A, the connection point of the drain electrode of the second transistor M2 and the drain electrode of the fourth transistor M4 is a node B, and the connection point of the grid electrode of the first transistor M1 and the grid electrode of the second transistor M2 is a node C;
the switch group comprises a first switch state and a second switch state, when the switch group is in the first switch state, the first current source I1 is connected with the variable group R, the second current source I2 is connected with the capacitor C, the variable group R is connected with the grid electrode of the third transistor M3, the capacitor C is connected with the grid electrode of the fourth transistor M4, the node A is connected with the node C, and the node B is connected with the grid electrode of the fifth transistor M5; when the switch group is in the second switch state, the first current source I1 is connected with the capacitor C, the second current source I2 is connected with the variable group R, the variable resistor R is connected with the grid electrode of the fourth transistor M4, the capacitor C is connected with the grid electrode of the third transistor M3, the node B is connected with the node C, and the node A is connected with the grid electrode of the fifth transistor M5.
Further, the current source switch group comprises a switch S1, a switch S2, a switch S3 and a switch S4, and the first current source I1 is connected with the capacitor C through the switch S1; the second current source I2 is connected with the variable group R through a switch S2; the first current source I1 is connected with the variable group R through a switch S3; the second current source I2 is connected with the capacitor C through a switch S4; the first switch control signal is used for controlling the switches S1 and S2, and the second switch control signal is used for controlling the switches S3 and S4.
Further, the comparator switch group comprises a switch S5, a switch S6, a switch S7, a switch S8, a switch S9, a switch S10, a switch S11 and a switch S12, wherein the variable resistor R is connected with the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 through the switch S6 and the switch S8 respectively; the capacitor C is connected with the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 through a switch S7 and a switch S5 respectively; the node A and the node B are respectively connected with the node C through a switch S9 and a switch S10; one end of the switch S11 is connected with the node A, and one end of the switch S12 is connected with the node B; the other end of the switch S11 is connected with the other end of the switch S12 and is connected with the grid electrode of the fifth transistor M5; the first switch control signal is used for controlling the switch S7, the switch S8, the switch S10 and the switch S11, and the second switch control signal is used for controlling the switch S5, the switch S6, the switch S9 and the switch S12.
Further, in the comparator, the first transistor M1, the second transistor M2, and the fifth transistor M5 are PMOS transistors, the third transistor M3 and the fourth transistor M4 are NMOS transistors, the sources of the first transistor M1, the second transistor M2, and the fifth transistor M5 are connected to a power source, the sources of the third transistor M3 and the fourth transistor M4 are connected to a third current source I3, and the drain of the fifth transistor M5 is connected to a fourth current source I4.
Further, in the comparator, the first transistor M1, the second transistor M2, and the fifth transistor M5 are NMOS transistors, the third transistor M3 and the fourth transistor M4 are PMOS transistors, the sources of the third transistor M3 and the fourth transistor M4 are connected to the third current source I3, the sources of the first transistor M1, the second transistor M2, and the fifth transistor M5 are grounded, and the drain of the fifth transistor M5 is connected to the fourth current source I4.
Further, the frequency divider is a divide-by-two frequency divider.
Further, the grid electrode of the discharge transistor is connected with the output of the comparator, the drain electrode of the discharge transistor is connected with the capacitor, and the source electrode of the discharge transistor is grounded.
Compared with the prior art, the high-precision low-jitter clock oscillator circuit provided by the utility model uses the signal output by the oscillator and the reverse signal thereof as a group of switch control signals for controlling all switches in the clock oscillator, so that the influence of low-frequency noise in two adjacent turnover periods of the comparator is mutually reversed, the time length of one big clock period after two frequency division is fixed, and the influence of the low-frequency noise on the frequency of the output signal is eliminated. The clock oscillator is not limited by low-frequency noise any more, the output signal frequency precision is high, the jitter is low, the stability is good, and an accurate and stable clock source can be provided for wireless receiving and transmitting.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional relaxation RC oscillator;
FIG. 2 is a schematic diagram of a high-precision low-jitter clock oscillator circuit according to an embodiment;
FIG. 3 is a schematic circuit diagram of a low frequency noise cancellation current source;
FIG. 4 is a schematic circuit diagram of a low frequency noise cancellation comparator;
Fig. 5 is a schematic diagram of the voltage at each node in a high precision low jitter clock oscillator circuit.
Detailed Description
The utility model is further illustrated by the following description in conjunction with the accompanying drawings and specific embodiments.
Embodiment one:
A high-precision low-jitter clock oscillator circuit is shown in FIG. 2, and comprises a first current source I1, a second current source I2, a variable resistor R, a capacitor C, a discharge transistor M0 and a comparator, wherein the grid electrode of the discharge transistor is connected with the output of the comparator, the drain electrode of the discharge transistor is connected with the capacitor, and the source electrode of the discharge transistor is grounded. The frequency divider is characterized by further comprising a switch group, a frequency divider and an inverter, wherein the comparator, the frequency divider and the inverter are sequentially connected, the output end of the frequency divider outputs a first switch control signal clk_a, and the output end of the inverter outputs a second switch control signal clk_b. The first and second switch control signals clk_a and clk_b may each be used as a final oscillator output signal.
As shown in the figure, the switch group includes a current source switch group and a comparator switch group, the current source switch group is connected between the first current source I1 and the second current source I2 and the variable group R and the capacitor C, and the comparator switch group is located inside the comparator.
The frequency divider is a divide-by-two frequency divider.
As shown in fig. 3, the current source switch group includes a switch S1, a switch S2, a switch S3, and a switch S4, where the first current source I1 is connected to the capacitor C through the switch S1; the second current source I2 is connected with the variable group R through a switch S2; the first current source I1 is connected with the variable group R through a switch S3; the second current source I2 is connected with the capacitor C through a switch S4; the first switch control signal clk_a is used for controlling the switches S1 and S2, and the second switch control signal clk_b is used for controlling the switches S3 and S4.
As shown in fig. 4, the comparator includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5, wherein a connection point between a drain electrode of the first transistor M1 and a drain electrode of the third transistor M3 is a node a, a connection point between a drain electrode of the second transistor M2 and a drain electrode of the fourth transistor M4 is a node B, and a connection point between a gate electrode of the first transistor M1 and a gate electrode of the second transistor M2 is a node C.
In this embodiment, the first transistor M1, the second transistor M2, and the fifth transistor M5 are PMOS transistors, the third transistor M3, and the fourth transistor M4 are NMOS transistors, the sources of the first transistor M1, the second transistor M2, and the fifth transistor M5 are connected to a power source, the sources of the third transistor M3 and the fourth transistor M4 are connected to a third current source I3, and the drain of the fifth transistor M5 is connected to a fourth current source I4.
As shown in fig. 4, the comparator switch group includes a switch S5, a switch S6, a switch S7, a switch S8, a switch S9, a switch S10, a switch S11, and a switch S12, where the variable resistor R is connected to the gate of the third transistor M3 and the gate of the fourth transistor M4 through the switch S6 and the switch S8, respectively; the capacitor C is connected with the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 through a switch S7 and a switch S5 respectively; the node A and the node B are respectively connected with the node C through a switch S9 and a switch S10; one end of the switch S11 is connected with the node A, and one end of the switch S12 is connected with the node B; the other end of the switch S11 is connected with the other end of the switch S12 and is connected with the grid electrode of the fifth transistor M5; the first switch control signal clk_a is used for controlling the switch S7, the switch S8, the switch S10 and the switch S11, and the second switch control signal clk_b is used for controlling the switch S5, the switch S6, the switch S9 and the switch S12.
The switch group is controlled by a first switch control signal clk_a and a second switch control signal clk_b, clk_a and clk_b being a pair of opposite signals.
As shown in fig. 5, the voltage waveforms of the nodes in the circuit are shown, and the working principle of the circuit is described with reference to fig. 5:
when the first switch control signal clk_a is at a low level and the second switch control signal clk_b is at a high level, the switch group is in the first switch state. At this time, the switches S1, S2, S7, S8, S10, and S11 are opened, and the switches S3, S4, S5, S6, S9, and S12 are closed. The first current source I1 is connected with the variable group R, the second current source I2 is connected with the capacitor C, the variable group R is connected with the grid electrode of the third transistor M3, the capacitor C is connected with the grid electrode of the fourth transistor M4, the node A is connected with the node C, and the node B is connected with the grid electrode of the fifth transistor M5. At this time, the first current source I1 generates a voltage V1 through the variable resistor R, assuming that the clock oscillation frequency is much larger than the low frequency noise,
Let vn=v1+v2+in2×r In formula (5), or vn=v1+v2+in1×r (6)
And Vn is approximately constant.
Equivalent of the effect of Vn to V1, there are:
V1＝I*R+Vn (7)
The second current source I2 charges the capacitor C, and when V2 reaches V1, the comparator turns over, i.e.:
I*T1＝C*(I*R+Vn) (8)
After the comparator is turned over for 2 times, the output of the two-frequency dividing circuit reverses clk_a and clk_b, at this time, the first switch control signal clk_a is at a high level, the second switch control signal clk_b is at a low level, and the switch group is in a second switch state. At this time, the switches S1, S2, S7, S8, S10, and S11 are closed, and the switches S3, S4, S5, S6, S9, and S12 are opened. The first current source I1 is connected with the capacitor C, the second current source I2 is connected with the variable group R, the variable resistor R is connected with the grid electrode of the fourth transistor M4, the capacitor C is connected with the grid electrode of the third transistor M3, the node B is connected with the node C, and the node A is connected with the grid electrode of the fifth transistor M5. At this time, the second current source I2 generates a voltage V1 by flowing through the variable resistor R, and the equivalent noise Vn is equivalent to V1, and includes:
V1＝I*R-Vn (9)
The first current source I1 charges the capacitor C, and when V2 reaches V1, the comparator turns over, i.e.:
I*T2＝C*(I*R-Vn) (10)
After 2 times of flipping, clk_a and clk_b are inverted again, and the above process is repeated.
Let the timing clock period be T,
T＝T1+T2 (11)
Taking equations (8) and (10) into equation (11), t=2×r×c, i.e. the final output clock frequency isThe low frequency noise is eliminated, thereby realizing a low jitter high precision clock source that is not affected by the low frequency noise.
Embodiment two:
The second embodiment is different from the first embodiment in that the structure inside the comparator is different, but the working principle is the same, and the effect is the same. In the second embodiment, the first transistor M1, the second transistor M2, and the fifth transistor M5 are all NMOS transistors, the third transistor M3 and the fourth transistor M4 are all PMOS transistors, the sources of the third transistor M3 and the fourth transistor M4 are connected to the third current source I3, the sources of the first transistor M1, the second transistor M2, and the fifth transistor M5 are grounded, and the drain of the fifth transistor M5 is connected to the fourth current source I4.
Claims (7)
1. The high-precision low-jitter clock oscillator circuit comprises a first current source I1, a second current source I2, a variable resistor R, a capacitor C, a discharge transistor M0, a comparator and a switch group, wherein the comparator, the frequency divider and the inverter are sequentially connected, the output end of the frequency divider outputs a first switch control signal, the output end of the inverter outputs a second switch control signal, and the first switch control signal and the second switch control signal are used for controlling the switch state of the switch group;
The switch group comprises a current source switch group and a comparator switch group, the current source switch group is connected between the first current source I1 and the second current source I2, the variable group R and the capacitor C, and the comparator switch group is positioned in the comparator;
The comparator comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein the connection point of the drain electrode of the first transistor M1 and the drain electrode of the third transistor M3 is a node A, the connection point of the drain electrode of the second transistor M2 and the drain electrode of the fourth transistor M4 is a node B, and the connection point of the grid electrode of the first transistor M1 and the grid electrode of the second transistor M2 is a node C;
The switch group comprises a first switch state and a second switch state, when the switch group is in the first switch state, the first current source I1 is connected with the variable group R, the second current source I2 is connected with the capacitor C, the variable group R is connected with the grid electrode of the third transistor M3, the capacitor C is connected with the grid electrode of the fourth transistor M4, the node A is connected with the node C, and the node B is connected with the grid electrode of the fifth transistor M5; when the switch group is in the second switch state, the first current source Il is connected with the capacitor C, the second current source I2 is connected with the variable group R, the variable resistor R is connected with the gate of the fourth transistor M4, the capacitor C is connected with the gate of the third transistor M3, the node B is connected with the node C, and the node a is connected with the gate of the fifth transistor M5.
2. The high-precision low-jitter clock oscillator circuit according to claim 1, wherein the current source switch group comprises a switch S1, a switch S2, a switch S3 and a switch S4, and the first current source I1 is connected with the capacitor C through the switch S1; the second current source I2 is connected with the variable group R through a switch S2; the first current source I1 is connected with the variable group R through a switch S3; the second current source I2 is connected with the capacitor C through a switch S4; the first switch control signal is used for controlling the switches S1 and S2, and the second switch control signal is used for controlling the switches S3 and S4.
3. The high-precision low-jitter clock oscillator circuit according to claim 1 or 2, wherein the comparator switch group comprises a switch S5, a switch S6, a switch S7, a switch S8, a switch S9, a switch S10, a switch S11 and a switch S12, and the variable resistor R is connected with the gate of the third transistor M3 and the gate of the fourth transistor M4 through a switch S6 and a switch S8 respectively; the capacitor C is connected with the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 through a switch S7 and a switch S5 respectively; the node A and the node B are respectively connected with the node C through a switch S9 and a switch S10; one end of the switch S11 is connected with the node A, and one end of the switch S12 is connected with the node B; the other end of the switch S11 is connected with the other end of the switch S12 and is connected with the grid electrode of the fifth transistor M5; the first switch control signal is used for controlling the switch S7, the switch S8, the switch S10 and the switch S11, and the second switch control signal is used for controlling the switch S5, the switch S6, the switch S9 and the switch S12.
4. The high-precision low-jitter clock oscillator circuit according to claim 1 or 2, wherein in the comparator, the first transistor M1, the second transistor M2 and the fifth transistor M5 are PMOS transistors, the third transistor M3 and the fourth transistor M4 are NMOS transistors, the sources of the first transistor M1, the second transistor M2 and the fifth transistor M5 are connected to a power supply, the sources of the third transistor M3 and the fourth transistor M4 are connected to a third current source I3, and the drain of the fifth transistor M5 is connected to a fourth current source I4.
5. The high-precision low-jitter clock oscillator circuit according to claim 1 or 2, wherein in the comparator, the first transistor M1, the second transistor M2 and the fifth transistor M5 are all NMOS transistors, the third transistor M3 and the fourth transistor M4 are all PMOS transistors, the sources of the third transistor M3 and the fourth transistor M4 are connected to the third current source I3, the sources of the first transistor M1, the second transistor M2 and the fifth transistor M5 are grounded, and the drain of the fifth transistor M5 is connected to the fourth current source I4.
6. The high precision low jitter clock oscillator circuit of claim 1 or 2 wherein the frequency divider is a divide-by-two frequency divider.
7. The high-precision low-jitter clock oscillator circuit of claim 1 or 2 wherein the discharge transistor has a gate connected to the comparator output, a drain connected to the capacitor, and a source connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322778251.XU CN221202509U (en) | 2023-10-17 | 2023-10-17 | High-precision low-jitter clock oscillator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322778251.XU CN221202509U (en) | 2023-10-17 | 2023-10-17 | High-precision low-jitter clock oscillator circuit |
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| CN221202509U true CN221202509U (en) | 2024-06-21 |
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| CN202322778251.XU Active CN221202509U (en) | 2023-10-17 | 2023-10-17 | High-precision low-jitter clock oscillator circuit |
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2023
- 2023-10-17 CN CN202322778251.XU patent/CN221202509U/en active Active
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