CN220887774U - Rectangular-section silicon rod combination, silicon wafer combination, sliced product, battery piece and photovoltaic module - Google Patents
Rectangular-section silicon rod combination, silicon wafer combination, sliced product, battery piece and photovoltaic module Download PDFInfo
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- CN220887774U CN220887774U CN202322172851.1U CN202322172851U CN220887774U CN 220887774 U CN220887774 U CN 220887774U CN 202322172851 U CN202322172851 U CN 202322172851U CN 220887774 U CN220887774 U CN 220887774U
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 267
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 266
- 239000010703 silicon Substances 0.000 title claims abstract description 266
- 235000012431 wafers Nutrition 0.000 claims abstract description 150
- 238000005520 cutting process Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 229940095676 wafer product Drugs 0.000 abstract description 7
- 238000002360 preparation method Methods 0.000 abstract description 2
- 230000035939 shock Effects 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000011166 aliquoting Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
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Abstract
The utility model relates to a rectangular section silicon rod combination, a rectangular silicon wafer combination, a piece-divided product prepared from the silicon wafer, a battery piece and a photovoltaic module. Particularly, by determining all different product specifications and numbers, a half-wafer combination scheme can be established, so that high-efficiency crystal utilization rate is realized, silicon wafers and half-wafer products with different number requirements are obtained, and compared with the current single silicon wafer product, the combination scheme can realize higher crystal utilization rate, the utilization rate is improved by more than 10%, the production efficiency is improved, and the production cost of the silicon wafers is reduced; the half-wafer silicon wafer product obtained by the combination mode can realize the preparation of a half-wafer finished silicon wafer at the silicon wafer end, and improve the battery efficiency loss caused by thermal shock damage to the battery wafer and mechanical damage additionally generated in the current laser scribing process.
Description
Technical Field
The utility model relates to the technical field of photovoltaic power generation, in particular to a rectangular section silicon rod combination and rectangular silicon wafer combination, a sliced product prepared from the silicon wafer, a battery slice and a photovoltaic module.
Background
With the development of the photovoltaic industry, the power requirements of component products are continuously improved. In order to meet the requirements of higher power component products, on one hand, a certain level of power boost target can be achieved by continuously increasing the battery conversion efficiency, but still the component products with higher competitiveness cannot be met. Thus, from another aspect, increasing the effective area of the component product is a major competing way to increase the power of the component, based on different product size applications.
The silicon chip product is used as a basic material of the photovoltaic module, the size of the silicon chip is closely related to the size of the module product, and different module products can be manufactured by different silicon chip products so as to meet different and multiple module application scenes, therefore, the requirements of the silicon chip products with different sizes are continuously provided, and the production and the manufacture of the silicon chip products are greatly adversely affected.
Meanwhile, with the continuous development and maturity of battery technology, the product demand of a battery end on half-piece silicon wafers is continuously enhanced, and as a silicon wafer manufacturing unit, not only the cost performance of silicon wafer manufacturing is considered, but also the different demands of customers on silicon wafer products are considered.
In order to meet the requirements of different silicon chip products at the battery assembly end, the crystal utilization rate at the silicon chip end shows a decreasing trend, and particularly along with the continuous development of rectangular silicon chips, the edge distance proportion of the rectangular silicon chips is larger and larger, so that the effective utilization rate of a monocrystalline silicon rod is increased and continuously decreased when rectangular square rods are processed, the effective output of a crystal pulling link is greatly influenced, and great resistance is caused to the reduction of the production cost at the silicon chip end.
Therefore, how to provide silicon wafer products with various specifications in a more cost-effective scheme is a key to the deep research of the silicon wafer manufacturing link, so that the silicon wafer manufacturing link can be compatible with the market demand of mainstream square wafers, the potential demand of rectangular wafers and the demand of future batteries.
Disclosure of utility model
In order to solve the problems, the utility model aims to provide a silicon wafer product combination and a silicon rod product combination, wherein the combination analysis of different products is performed by controlling the sizes of the silicon wafer combination section or the silicon rod combination section to form a consistent product solution, silicon wafer products with different sizes can be processed simultaneously, and the maximum output is realized by the crystal utilization rate. Furthermore, based on the silicon chip requirements of different sizes, the patent provides a silicon chip size combination scheme, so that half-chip combinations with different specification sizes and different numbers can be obtained on the same single crystal silicon rod at one time, namely, the unit output of the single crystal silicon rod is facilitated, and meanwhile, the requirements of at least two or more silicon chip products on different numbers can be met.
Item 1. A rectangular section silicon rod assembly,
The silicon rod combination comprises N silicon rods, wherein N is a positive integer greater than or equal to 2, the two groups of opposite side lengths of the rectangular section of the 1 st silicon rod are respectively a1 and b1, a1 is greater than or equal to b1, the two groups of opposite side lengths of the rectangular section of the 2 nd silicon rod are respectively a2 and b2, a2 is greater than or equal to b2, … … th (N-1) th silicon rod is respectively a (N-1) and b (N-1), a (N-1) is greater than or equal to b (N-1), the two groups of opposite side lengths of the rectangular section of the N th silicon rod are respectively aN aN and bN, aN is greater than or equal to bN, and a1 is greater than or equal to a2 and is greater than or equal to … … and is greater than or equal to a (N-1) is greater than or equal to aN.
And 2. According to the silicon rod combination in the item 1, when N=2, the first silicon rod rectangular section a1 side and the second silicon rod rectangular section a2 side are jointed to form a first combined section graph, the middle point of the jointed a1 side and the middle point of the jointed a2 side are overlapped, the first combined section graph is subjected to circumscribing, and the area ratio of the first combined section graph to the circumscribing is more than or equal to 70%.
Item 3. The silicon rod combination of item 2, the ratio of the first combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
Item 4. According to the silicon rod combination of item 1, when n=3, the first silicon rod rectangular section a1 edge is bonded with the second silicon rod rectangular section a2 edge to form a first combined section pattern, the largest extension edge of the first combined section pattern is bonded with the third silicon rod rectangular section a3 edge to form a second combined section pattern, the second combined section pattern is rounded, the ratio of the first combined section pattern area to the rounded area is greater than or equal to 70%,
The distance between the two farthest points of the second combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, one side length of the second combined section graph is the maximum extension, and the side is called as the maximum extension side.
Item 5. The silicon rod combination of item 4, the first combined cross-sectional pattern area to the circumscribed circle area ratio is greater than or equal to 80%.
According to the silicon rod combination of item 1, when N is greater than 3, the first silicon rod rectangular section a1 edge and the second silicon rod rectangular section a2 edge are jointed to form a first combined section pattern, the largest extension edge of the first combined section pattern and the third silicon rod rectangular section a3 edge are jointed to form a second combined section pattern, the largest extension edge of the second combined section pattern and the third silicon rod rectangular section a3 edge are jointed to form a third combined section pattern, the largest extension edge of the third combined section pattern and the fourth silicon rod rectangular section a4 edge are jointed to form a fourth combined section pattern, and the like, the (N-1) th combined section pattern is made into a circumcircle, the area ratio of the (N-1) th combined section pattern and the circumcircle is more than or equal to 70%,
The distance between the two farthest points of any combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, and one side length of the combined section graph is the maximum extension, and the side is called as the maximum extension side.
Item 7. The silicon rod combination of item 6, the first combined cross-sectional pattern area to the circumscribed circle area ratio is greater than or equal to 80%.
Item 8. The silicon rod combination according to any one of items 1 to 7, wherein the silicon rod rectangular cross-section side length in the silicon rod combination is selected from at least one of: 166+ -2 mm, 170.75 + -2 mm, 180+ -2 mm, 182+ -2 mm, 183.75 + -2 mm, 190+ -2 mm, 198+ -2 mm, 207+ -2 mm, 210+ -2 mm, 212+ -2 mm, 218+ -2 mm, 218.2+ -2 mm, 219+ -2 mm, 220+ -2 mm, 227.8+ -2 mm, 228+ -2 mm, 230+ -2 mm, 253+ -2 mm, 274+ -2 mm, 275+ -2 mm, 282+ -2 mm.
Item 9. The silicon rod combination according to any one of items 1 to 7, wherein the silicon rod rectangular cross-sectional dimension in the silicon rod combination is selected from one, two or more of the following:
(182+ -2) x (166+ -2) mm;
(182+ -2) x (170.75 + -2) mm;
(182+ -2) x (180+ -2) mm;
(182+ -2) x (182+ -2) mm;
(183.75 ±2) × (182±2) mm;
(190+ -2) x (182+ -2) mm;
(198 + -2) x (182 + -2) mm;
(207±2) × (182±2) mm;
(210±2) × (182±2) mm;
(212+ -2) x (182+ -2) mm;
(218±2) × (207±2) mm;
(218.2±2) × (182±2) mm;
(218.2±2) × (198±2) mm;
(218.2±2) × (210±2) mm;
(218.2 + -2) × (220 + -2) mm;
(218.8 + -2) x (207+ -2) mm;
(219±2) × (182±2) mm;
(220+ -2) x (182+ -2) mm;
(227.8±2) × (182±2) mm;
(227.8+ -2) x (218.8 + -2) mm;
(228±2) × (182±2) mm;
(253±2) × (182±2) mm;
(253±2) × (218±2) mm;
(274+ -2) x (207+ -2) mm;
(274 + -2) × (227.8 + -2) mm;
(274±2) × (253±2) mm;
(275±2) × (198±2) mm;
(275±2) × (210±2) mm;
(275 + -2) × (220 + -2) mm;
(275±2) × (230±2) mm;
(282±2) × (220±2) mm;
(182+ -2) x (72.5+ -2) mm;
(182+ -2) x (79.1+ -2) mm;
(182+ -2) x (79.75 + -2) mm;
(182+ -2) x (87+ -2) mm;
(182+ -2) x (91.875 + -2) mm;
(182+ -2) x (96.6+ -2) mm;
(182+ -2) x (96.75+ -2) mm;
(182+ -2) x (97+ -2) mm;
(182+ -2) x (98.8+ -2) mm;
(182+ -2) x (107.7+ -2) mm;
(182+ -2) x (108.6+ -2) mm;
(182+ -2) x (118.5+ -2) mm;
(182+ -2) x (124.1+ -2) mm;
(182+ -2) x (144.7+ -2) mm.
Item 10. The silicon rod combination according to any one of items 1 to 7, wherein N.gtoreq.3, wherein the three silicon rods have rectangular cross-sectional dimensions respectively selected from the following three groups
Group 1:
(182+ -2) x (93+ -2) mm;
(182+ -2) x (97+ -2) mm;
(182+ -2) x (101+ -2) mm;
(182+ -2) x (105+ -2) mm;
(182+ -2) x (109+ -2) mm;
(182+ -2) x (113+ -2) mm;
(182±2) × (117±2) mm;
(182+ -2) x (121+ -2) mm;
(182+ -2) x (125+ -2) mm;
(182+ -2) x (129+ -2) mm;
(182 + -2) × (136 + -2) mm;
(182+ -2) x (146+ -2) mm;
(210+ -2) x (107+ -2) mm;
(210+ -2) x (111+ -2) mm;
(210+ -2) x (115+ -2) mm;
(210+ -2) x (119+ -2) mm;
(210+ -2) x (126+ -2) mm;
(210+ -2) x (136+ -2) mm; (210+ -2) x (146+ -2) mm; (218.2±2) × (111±2) mm; (218.2±2) × (115±2) mm; (218.2 + -2) × (119 + -2) mm; (218.2±2) × (126±2) mm; (218.2 + -2) × (136 + -2) mm; (218.2 + -2) × (146 + -2) mm; group 2:
(182+ -2) x (73+ -2) mm;
(182+ -2) x (77+ -2) mm;
(182+ -2) x (81+ -2) mm;
(182+ -2) x (85+ -2) mm;
(182+ -2) x (89+ -2) mm;
(210+ -2) x (71+ -2) mm;
(210+ -2) x (75+ -2) mm;
(210+ -2) x (79+ -2) mm;
(210+ -2) x (83+ -2) mm;
(210+ -2) x (87+ -2) mm;
(210+ -2) x (91+ -2) mm;
(210+ -2) x (95+ -2) mm;
(210+ -2) x (99+ -2) mm;
(218.2±2) × (71±2) mm; (218.2±2) × (75±2) mm; (218.2 + -2) × (79 + -2) mm; (218.2 + -2) × (83 + -2) mm; (218.2±2) × (87±2) mm; (218.2 + -2) × (91 + -2) mm; (218.2.+ -. 2) x (95.+ -. 2) mm; (218.2 + -2) × (99 + -2) mm;
(218.2 + -2) × (103 + -2) mm;
(218.2±2) × (107±2) mm;
Group 3:
(166+ -2) x (83+ -2) mm;
(182+ -2) x (91+ -2) mm;
(210+ -2) x (105+ -2) mm;
(218.2.+ -. 2) x (109.1.+ -. 2) mm.
Item 11. The silicon rod combination according to any one of items 1 to 7, wherein the ratio of lengths of adjacent two sides of the rectangular cross section of any one of the silicon rods satisfies: greater than or equal to 1/90 and less than or equal to 89/90.
The silicon rod assembly according to any one of items 1 to 7, wherein the silicon rod assembly comprises at least one silicon rod with a rectangular cross section and a ratio of lengths of adjacent two sides of 2+ -0.2.
Item 13. A rectangular silicon wafer assembly,
The silicon wafer combination comprises N silicon wafers, wherein N is a positive integer greater than or equal to 2, wherein the two groups of opposite side lengths of the rectangular section of the 1 st silicon wafer are respectively a1 and b1, a1 is greater than or equal to b1, the two groups of opposite side lengths of the rectangular section of the 2 nd silicon wafer are respectively a2 and b2, a2 is greater than or equal to b2, the two groups of opposite side lengths of the rectangular section of the … … th (N-1) silicon wafer are respectively a (N-1) and b (N-1), a (N-1) is greater than or equal to b (N-1), the two groups of opposite side lengths of the rectangular section of the N-th silicon wafer are respectively aN and bN, aN is greater than or equal to bN, and a1 is greater than or equal to a2 and is greater than or equal to … … and is greater than or equal to a (N-1).
In one embodiment of the utility model, when a1, a2 … …, a (N-1), aN are equal and b1, b2 … …, b (N-1), bN are equal, the silicon wafer sizes included in the silicon wafer combination are equal. When a1 is equal to b1, a2 is equal to b2, a3 is equal to b3, … … aN is equal to bN, the silicon wafers included in the silicon wafer combination are square silicon wafers.
And 14. When N=2, the rectangular section a1 side of the first silicon wafer is jointed with the rectangular section a2 side of the second silicon wafer to form a first combined section graph, the middle point of the jointed rectangular section a1 side is superposed with the middle point of the laminated rectangular section a2 side, the first combined section graph is subjected to circumscribing, and the area ratio of the first combined section graph to the circumscribing is more than or equal to 70%.
Item 15. The silicon wafer assembly of item 14, the ratio of the first combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
Item 16. The silicon wafer assembly of item 13, when n=3, the first silicon wafer rectangular section a1 edge is bonded to the second silicon wafer rectangular section a2 edge to form a first assembled section pattern, the largest extension edge of the first assembled section pattern is bonded to the third silicon wafer rectangular section a3 edge to form a second assembled section pattern, the second assembled section pattern is rounded, the ratio of the first assembled section pattern area to the rounded area is greater than or equal to 70%,
The distance between the two farthest points of the second combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, one side length of the second combined section graph is the maximum extension, and the side is called as the maximum extension side.
Item 17. The silicon wafer assembly of item 16, wherein the ratio of the first combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
Item 18. When N > 3, the silicon wafer assembly of item 13, the first silicon wafer rectangular section a1 edge and the second silicon wafer rectangular section a2 edge are joined to form a first assembled section pattern, the maximum extension edge of the first assembled section pattern and the third silicon wafer rectangular section a3 edge are joined to form a second assembled section pattern, the maximum extension edge of the second assembled section pattern and the third silicon wafer rectangular section a3 edge are joined to form a third assembled section pattern, the maximum extension edge of the third assembled section pattern and the fourth silicon wafer rectangular section a4 edge are joined to form a fourth assembled section pattern, and so on, the (N-1) th assembled section pattern is circumscribed, the (N-1) th assembled section pattern area is greater than or equal to 70% of the circumscribed circle area,
The distance between the two farthest points of any combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, and one side length of the combined section graph is the maximum extension, and the side is called as the maximum extension side.
Item 19. The silicon wafer assembly of item 18, wherein the ratio of the first combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
Item 20. The silicon wafer combination according to any one of items 13 to 19, wherein the silicon wafer rectangular cross-section side length in the silicon wafer combination is selected from at least one of: 166+ -2 mm, 170.75 + -2 mm, 180+ -2 mm, 182+ -2 mm, 183.75 + -2 mm, 190+ -2 mm, 198+ -2 mm, 207+ -2 mm, 210+ -2 mm, 212+ -2 mm, 218+ -2 mm, 218.2+ -2 mm, 219+ -2 mm, 220+ -2 mm, 227.8+ -2 mm, 228+ -2 mm, 230+ -2 mm, 253+ -2 mm, 274+ -2 mm, 275+ -2 mm, 282+ -2 mm.
The silicon wafer assembly according to any one of items 13 to 19, wherein the silicon wafer rectangular cross-sectional dimension is selected from one, two or more of the following:
(182+ -2) x (166+ -2) mm;
(182+ -2) x (170.75 + -2) mm;
(182+ -2) x (180+ -2) mm;
(182+ -2) x (182+ -2) mm;
(183.75 ±2) × (182±2) mm;
(190+ -2) x (182+ -2) mm;
(198 + -2) x (182 + -2) mm;
(207±2) × (182±2) mm;
(210±2) × (182±2) mm;
(212+ -2) x (182+ -2) mm;
(218±2) × (207±2) mm;
(218.2±2) × (182±2) mm;
(218.2±2) × (198±2) mm;
(218.2±2) × (210±2) mm;
(218.2 + -2) × (220 + -2) mm;
(218.8 + -2) x (207+ -2) mm;
(219±2) × (182±2) mm;
(220+ -2) x (182+ -2) mm;
(227.8±2) × (182±2) mm;
(227.8+ -2) x (218.8 + -2) mm;
(228±2) × (182±2) mm;
(253±2) × (182±2) mm;
(253±2) × (218±2) mm;
(274+ -2) x (207+ -2) mm;
(274 + -2) × (227.8 + -2) mm;
(274±2) × (253±2) mm;
(275±2) × (198±2) mm;
(275±2) × (210±2) mm;
(275 + -2) × (220 + -2) mm;
(275±2) × (230±2) mm;
(282±2) × (220±2) mm;
(182+ -2) x (72.5+ -2) mm;
(182+ -2) x (79.1+ -2) mm;
(182+ -2) x (79.75 + -2) mm;
(182+ -2) x (87+ -2) mm;
(182+ -2) x (91.875 + -2) mm;
(182+ -2) x (96.6+ -2) mm;
(182+ -2) x (96.75+ -2) mm;
(182+ -2) x (97+ -2) mm;
(182+ -2) x (98.8+ -2) mm;
(182+ -2) x (107.7+ -2) mm;
(182+ -2) x (108.6+ -2) mm;
(182+ -2) x (118.5+ -2) mm;
(182+ -2) x (124.1+ -2) mm;
(182+ -2) x (144.7+ -2) mm.
The silicon wafer combination according to any one of items 13 to 19, wherein N.gtoreq.3, wherein the rectangular cross-sectional dimensions of the three silicon wafers are respectively selected from the following three groups
Group 1:
(182+ -2) x (93+ -2) mm;
(182+ -2) x (97+ -2) mm;
(182+ -2) x (101+ -2) mm;
(182+ -2) x (105+ -2) mm;
(182+ -2) x (109+ -2) mm;
(182+ -2) x (113+ -2) mm;
(182±2) × (117±2) mm;
(182+ -2) x (121+ -2) mm; (182+ -2) x (125+ -2) mm; (182+ -2) x (129+ -2) mm; (182 + -2) × (136 + -2) mm; (182+ -2) x (146+ -2) mm; (210+ -2) x (107+ -2) mm; (210+ -2) x (111+ -2) mm; (210+ -2) x (115+ -2) mm; (210+ -2) x (119+ -2) mm; (210+ -2) x (126+ -2) mm; (210+ -2) x (136+ -2) mm; (210+ -2) x (146+ -2) mm; (218.2±2) × (111±2) mm; (218.2±2) × (115±2) mm; (218.2 + -2) × (119 + -2) mm; (218.2±2) × (126±2) mm; (218.2 + -2) × (136 + -2) mm; (218.2 + -2) × (146 + -2) mm; group 2:
(182+ -2) x (73+ -2) mm;
(182+ -2) x (77+ -2) mm;
(182+ -2) x (81+ -2) mm;
(182+ -2) x (85+ -2) mm;
(182+ -2) x (89+ -2) mm;
(210+ -2) x (71+ -2) mm;
(210+ -2) x (75+ -2) mm;
(210+ -2) x (79+ -2) mm;
(210+ -2) x (83+ -2) mm;
(210+ -2) x (87+ -2) mm;
(210+ -2) x (91+ -2) mm;
(210+ -2) x (95+ -2) mm;
(210+ -2) x (99+ -2) mm;
(218.2±2) × (71±2) mm;
(218.2±2) × (75±2) mm;
(218.2 + -2) × (79 + -2) mm;
(218.2 + -2) × (83 + -2) mm;
(218.2±2) × (87±2) mm;
(218.2 + -2) × (91 + -2) mm;
(218.2.+ -. 2) x (95.+ -. 2) mm;
(218.2 + -2) × (99 + -2) mm;
(218.2 + -2) × (103 + -2) mm;
(218.2±2) × (107±2) mm;
Group 3:
(166+ -2) x (83+ -2) mm;
(182+ -2) x (91+ -2) mm;
(210+ -2) x (105+ -2) mm;
(218.2.+ -. 2) x (109.1.+ -. 2) mm.
Item 23. The silicon wafer assembly of any one of items 13 to 19, wherein the ratio of lengths of adjacent two sides of the rectangular cross section of any one of the silicon wafers satisfies: greater than or equal to 1/90 and less than or equal to 89/90.
Item 24. The wafer assembly of any one of items 13 to 19, wherein the wafer assembly comprises at least one wafer having a rectangular cross-section with a length ratio of 2.+ -. 0.2 on adjacent sides.
Item 25. A sliced product made from any one of the silicon wafers in the silicon wafer combination of any one of items 13 to 24, which is a sliced silicon wafer obtained by cutting the any one of the silicon wafers.
Item 26. The sliced product of item 25, which is a sliced piece of silicon from any of the silicon halves, trisections, quarters, penta-quarters, hexa-quarters, or octa-quarters.
In one embodiment of the utility model, the size of the split silicon wafer obtained by halving the silicon wafer is half of that of the silicon wafer, and halving comprises two cutting modes parallel to the long side direction and the wide side direction of the silicon wafer. Likewise, trisection, quartering, penta-aliquoting, hexa-aliquoting, or octa-aliquoting also include various ways of cutting the silicon wafer.
Item 27. A battery sheet made from the sliced silicon wafer of any one of items 25 or 26.
Item 28. A photovoltaic module of the cell value of item 27.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments of the present utility model will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Figure 1 shows a schematic cross-sectional view of a silicon rod in accordance with one embodiment of the present utility model.
Fig. 2 shows a schematic cross-sectional view of a silicon rod of a comparative example embodiment.
Fig. 3 shows a schematic cross-sectional view of a silicon rod of a comparative example embodiment.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
As described above, the present utility model provides a rectangular silicon wafer assembly, where the silicon wafer assembly includes two or more silicon wafers, all silicon wafers in the silicon wafer assembly have the same size, any silicon wafer in the silicon wafer assembly is cut to obtain a cut piece product, and the piece product may be a piece of any silicon wafer in the width or length direction, for example, a piece of any silicon wafer in the width or length direction.
In one embodiment, when the length and width of the silicon wafer are not the same, the ratio of the length to width of the silicon wafer is: 1.8, 1.83, 1.92, 2, 2.01, 2.07, 2.1, 2.15, 2.2.
And preparing a battery by using the sliced product to obtain battery slices with corresponding sizes, for example, when a silicon slice combination comprises two silicon slices with the dimensions of (190+/-2) x (182+/-2) mm, performing halving cutting on the silicon slices along the length direction to obtain four sliced products with the dimensions of (95+/-2) x (182+/-2) mm, and preparing the battery slices by using the sliced products, wherein the sizes of the corresponding battery slices are (95+/-2) x (182+/-2).
Because the size of the silicon wafer combination is flexible and various, the corresponding whole solar cell or the slicing cell formed by the silicon wafer/slicing product can form the photovoltaic module with more flexible and various power, and can meet the requirements of various powers of the photovoltaic module.
When the number of related silicon wafers in the silicon wafer combination is more than 2, and the sizes of the silicon wafers in the silicon wafer combination are not completely consistent, the silicon wafers can be obtained by processing the same silicon rod, the utilization rate of the silicon rod can be improved, and therefore the processing cost of the silicon wafers is saved.
The following table 1 lists the dimensions of a series of silicon wafer combinations to be prepared according to the present utility model, in which the silicon wafer combinations comprise at least three silicon wafer dimensions, respectively indicated as a series, B series and C series in the tables, which are respectively selected from the dimensions indicated in the tables below.
TABLE 1
Wherein H represents the width of the silicon wafer, and L represents the length of the silicon wafer.
According to the combination type of the silicon chip products, the combination design of various schemes can be carried out on the crystal round bar with a certain diameter. The A/B/C series silicon chip can be any one (A/B/C series) of the tables, and the D series silicon chip product can also be directly designed into any one (A/B/C series) of the whole multiple silicon chip with the same size and the same long side or short side. The D-series silicon wafer definition in this patent covers the current industry whole wafer definition, i.e. M10 (182 x 182) silicon wafers in industry standard D-series can be considered as a combination of two B-series 182 x 91 half silicon wafers.
In order to maximally increase the crystal utilization rate, the half-piece products in the half-piece silicon wafer combination can be different numbers of the same product specification; but also can represent different numbers of half-sheet products with different specifications.
The chamfer angle of the silicon wafer product is a chamfer angle with different arc length projections, and the range of the arc length chamfer angle is 1.5-7.5+/-0.5 mm.
The silicon wafer design scheme can form a one-to-one correspondence with the single crystal round bar, and in the process of processing the round bar into a square bar, the square bar product can be processed according to different silicon wafer combination schemes.
The different scheme combinations correspond to different crystal diameters, and the crystal diameters can be calculated according to the silicon wafer combinations with different sizes and the geometric relationship of the circumscribed circles.
Wherein the allowable range of the diameter of the round bar of the crystal bar is 220-600mm; wherein the diameter of the round bar is +5mm of the diameter of the finished product of the original bar.
The A/B/C/D series square bar products can be obtained by machining under the condition of the silicon chip combination and the crystal bar diameter of the design target, and the square bar products are also the silicon bar composition protected by the utility model.
Meanwhile, according to the actual customer needs, symmetrical and asymmetrical machining can be performed on the D-series square bar products to obtain the A/B/C-series square bar products with different sizes.
Aiming at the A series square bar products and the B series square bar products obtained in the above, the A series and the B series products of the design targets can be obtained through slicing processing.
The method comprises the steps of firstly determining the sizes of various (more than or equal to 2) half-wafer products required to be processed simultaneously, ensuring the highest utilization rate and the minimum circumscribed circle comprising all rectangular half-wafer combinations, or keeping the longest size of an irregular pattern formed by the various half-wafer combinations to be minimum, and finally taking the longest size of the irregular pattern as the diameter of a circle, namely the calculated circle as the circle with the smallest diameter with the highest utilization rate. The combination mode with the highest half-sheet utilization rate should follow the maximum size sequential welt stacking combination mode, namely according to the size of the required half-sheet product, the largest single-side size edge in the half-sheet specification is selected as the initial position of combination stacking, and the maximum single-side size is defined; searching a 2 nd large single-side size smaller than the maximum single-side size, overlapping the 2 nd large single-side size with the maximum single-side size, and forming a 1 st nonstandard combined rectangle, wherein the 1 st nonstandard combined rectangle has a maximum boundary size, namely maximum extension, and the size is defined as a 1 st maximum size; searching a new 2 nd large single-side size smaller than the 1 st maximum size, overlapping the 1 st maximum size side to form a 2 nd nonstandard combined rectangle, and forming the 2 nd maximum extension, namely the 2 nd maximum size; searching for a 3 rd large single-side size smaller than the 2 nd maximum size, and overlapping the 3 rd maximum size with the 2 nd maximum size to form a 3 rd nonstandard combined rectangle, wherein the 3 rd maximum size is also existed; and the combination stacking of all the needed half pieces is completed by analogy. The stacking mode is the optimal combination mode with the highest utilization rate.
Further example, referring to fig. 1, a silicon wafer combination mode is used for combination, a circular silicon rod is provided, the diameter of the cross section of the circular silicon rod is 220 mm-600 mm, a series D (182±2×182±2 mm) and a or series C (182±x) half silicon wafer products are prepared by cutting, and finally, a combination scheme of D1+a/C4 is obtained simultaneously, so that the silicon rod diameter of the circular silicon rod is realized when the highest crystal utilization rate is realized, and a silicon wafer combination analysis model is established by analyzing the size relation of two silicon wafers;
diameter phi of silicon rod = diameter phi+5mm of finished product of circumscribed circle
Crystal utilization% =sum of all half areas mm 2/round area of silicon rod mm 2%100%
The maximum crystal utilization rate of the D1+A/C4 combination scheme is known by establishing the circumscribed circle relation in a half-sheet combination mode; the crystal utilization rate is highest when the size of the A+C series half tablet is 182 x 58+/-3 mm, and the crystal utilization rate is 75%.
Comparative example:
referring to fig. 2, a single D-series (all-square) silicon wafer product is obtained by squaring with a round bar machine, a round silicon bar is provided, the diameter of the cross section of the round silicon bar is 220 mm-600 mm, the D-series is prepared by cutting, and the utilization rate of round-square crystals is only about 63%.
Referring to fig. 3, a single D series 182 x (rectangular) silicon wafer product is obtained by squaring a round bar machine, and a round silicon bar is provided, wherein the cross section diameter of the round silicon bar is 250 mm-600 mm, the D series is prepared by cutting, the utilization rate of the round square crystal is only about 62%, and the utilization rate of the crystal is gradually reduced as the aspect ratio K is larger or smaller, and is about 62% at the aspect ratio k=1.
In summary, by determining all the required specifications and numbers of different products, a silicon wafer combination scheme can be established, so that the minimum crystal diameter can be realized, and silicon wafers and half-wafer products with different numbers of requirements can be simultaneously prepared; the half-wafer silicon wafer product obtained by the combination mode can realize the preparation of a half-wafer finished silicon wafer at the silicon wafer end, and improve the battery efficiency loss caused by thermal shock damage to the battery wafer and mechanical damage additionally generated in the current laser scribing process.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments of the present utility model have been described above with reference to the accompanying drawings, but the present utility model is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present utility model and the scope of the claims, which are to be protected by the present utility model.
Claims (28)
1. A rectangular section silicon rod combination is characterized in that,
The silicon rod combination comprises N silicon rods, wherein N is a positive integer greater than or equal to 2, the two groups of opposite side lengths of the rectangular section of the 1 st silicon rod are respectively a1 and b1, a1 is greater than or equal to b1, the two groups of opposite side lengths of the rectangular section of the 2 nd silicon rod are respectively a2 and b2, a2 is greater than or equal to b2, … … th (N-1) th silicon rod is respectively a (N-1) and b (N-1), a (N-1) is greater than or equal to b (N-1), the two groups of opposite side lengths of the rectangular section of the N th silicon rod are respectively aN aN and bN, aN is greater than or equal to bN, and a1 is greater than or equal to a2 and is greater than or equal to … … and is greater than or equal to a (N-1) is greater than or equal to aN.
2. The silicon rod combination according to claim 1, wherein when n=2, the first silicon rod rectangular section a1 side and the second silicon rod rectangular section a2 side are jointed to form a first combined section pattern, the middle point of the jointed a1 side and the middle point of the a2 side are overlapped, the first combined section pattern is subjected to circumscribing, and the area ratio of the first combined section pattern to the circumscribing is greater than or equal to 70%.
3. The silicon rod combination of claim 2, wherein the ratio of the first combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
4. The silicon rod assembly of claim 1, wherein when N=3, the first silicon rod rectangular section a1 edge and the second silicon rod rectangular section a2 edge are jointed to form a first combined section pattern, the largest extension edge of the first combined section pattern and the third silicon rod rectangular section a3 edge are jointed to form a second combined section pattern, the second combined section pattern is circumscribing, the area ratio of the second combined section pattern to the circumscribing area is more than or equal to 70%,
The distance between the two farthest points of the second combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, one side length of the second combined section graph is the maximum extension, and the side is called as the maximum extension side.
5. The silicon rod assembly of claim 4 wherein the ratio of the second combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
6. The silicon rod combination according to claim 1, wherein when N > 3, the first silicon rod rectangular section a1 edge and the second silicon rod rectangular section a2 edge are jointed to form a first combined section pattern, the largest extension edge of the first combined section pattern and the third silicon rod rectangular section a3 edge are jointed to form a second combined section pattern, the largest extension edge of the second combined section pattern and the third silicon rod rectangular section a3 edge are jointed to form a third combined section pattern, the largest extension edge of the third combined section pattern and the fourth silicon rod rectangular section a4 edge are jointed to form a fourth combined section pattern, and so on, the (N-1) th combined section pattern is circumscribing, the ratio of the (N-1) th combined section pattern area to the circumscribing area is more than or equal to 70%,
The distance between the two farthest points of any combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, and one side length of the combined section graph is the maximum extension, and the side is called as the maximum extension side.
7. The silicon rod assembly of claim 6 wherein the ratio of the (N-1) th combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
8. The silicon rod assembly of any one of claims 1 to 7 wherein the silicon rod rectangular cross-section side length of the silicon rod assembly is selected from at least one of: 166+ -2 mm, 170.75 + -2 mm, 180+ -2 mm, 182+ -2 mm, 183.75 + -2 mm, 190+ -2 mm, 198+ -2 mm, 207+ -2 mm, 210+ -2 mm, 212+ -2 mm, 218+ -2 mm, 218.2+ -2 mm, 219+ -2 mm, 220+ -2 mm, 227.8+ -2 mm, 228+ -2 mm, 230+ -2 mm, 253+ -2 mm, 274+ -2 mm, 275+ -2 mm, 282+ -2 mm.
9. A silicon rod assembly according to any one of claims 1 to 7 wherein the silicon rod rectangular cross-sectional dimensions in the silicon rod assembly are selected from one, two or more of the following:
182+ -2×166+ -2 mm;
182 + -2X 170.75 + -2 mm;
182 + -2X 180 + -2 mm;
182 + -2X 182 + -2 mm;
183.75.+ -. 2X 182.+ -. 2 mm;
190+ -2×182+ -2 mm;
198+ -2×182+ -2 mm;
207.+ -. 2X 182.+ -. 2 mm;
210+ -2×182+ -2 mm;
212.+ -. 2X 182.+ -. 2 mm;
218.+ -. 2X 207.+ -. 2 mm;
218.2.+ -. 2X 182.+ -. 2 mm;
218.2.+ -. 2X 198.+ -. 2 mm;
218.2.+ -. 2X 210.+ -. 2 mm;
218.2.+ -. 2X 220.+ -. 2 mm;
218.8.+ -. 2X 207.+ -. 2 mm;
219.+ -. 2X 182.+ -. 2 mm;
220+ -2×182+ -2 mm;
227.8.+ -. 2X 182.+ -. 2 mm;
227.8.+ -. 2X 218.8.+ -. 2 mm;
228±2×182±2 mm;
253±2×182±2 mm;
253.+ -. 2X 218.+ -. 2 mm;
274.+ -. 2X 207.+ -. 2 mm;
274.+ -. 2X 227.8.+ -. 2 mm;
274.+ -. 2X 253.+ -. 2 mm;
275+ -2×198+ -2 mm;
275+ -2×210+ -2 mm;
275 + -2X 220 + -2 mm;
275+ -2×230+ -2 mm;
282±2×220±2 mm;
182 + -2X 72.5 + -2 mm;
182 + -2X 79.1 + -2 mm;
182 + -2X 79.75 + -2 mm;
182 + -2 x 87 + -2 mm;
182 + -2X 91.875 + -2 mm;
182 + -2X 96.6 + -2 mm;
182 + -2 x 96.75 + -2 mm;
182 + -2X 97 + -2 mm;
182 + -2X 98.8 + -2 mm;
182 + -2X 107.7 + -2 mm;
182 + -2X 108.6 + -2 mm;
182 + -2X 118.5 + -2 mm;
182 + -2X 124.1 + -2 mm;
182 + -2X 144.7 + -2 mm.
10. The silicon rod combination according to any one of claims 1 to 7, wherein N.gtoreq.3, wherein the three silicon rods have rectangular cross-sectional dimensions respectively selected from the following three groups
Group 1:
182 + -2X 93 + -2 mm;
182 + -2X 97 + -2 mm;
182 + -2 x 101 + -2 mm;
182 + -2X 105 + -2 mm;
182 + -2X 109 + -2 mm;
182 + -2X 113 + -2 mm;
182 + -2X 117 + -2 mm;
182 + -2X 121 + -2 mm;
182 + -2 x 125 + -2 mm;
182 + -2X 129 + -2 mm;
182 + -2X 136 + -2 mm;
182 + -2X 146 + -2 mm;
210+ -2×107+ -2 mm;
210+ -2×111+ -2 mm;
210+ -2×115+ -2 mm;
210+ -2×119+ -2 mm;
210+ -2×126+ -2 mm;
210+ -2×136+ -2 mm;
210+ -2×146+ -2 mm;
218.2.+ -. 2X 111.+ -. 2 mm;
218.2.+ -. 2X 115.+ -. 2 mm;
218.2.+ -. 2X 119.+ -. 2 mm; 218.2.+ -. 2X 126.+ -. 2 mm; 218.2.+ -. 2X 136.+ -. 2 mm; 218.2.+ -. 2X 146.+ -. 2 mm; group 2:
182 + -2X 73 + -2 mm; 182 + -2X 77 + -2 mm; 182 + -2X 81 + -2 mm; 182 + -2X 85 + -2 mm; 182 + -2X 89 + -2 mm; 210+ -2×71+ -2 mm; 210+ -2×75+ -2 mm; 210+ -2×79+ -2 mm; 210+ -2×83+ -2 mm; 210+ -2×87+ -2 mm; 210+ -2×91+ -2 mm; 210+ -2×95+ -2 mm; 210+ -2×99+ -2 mm; 218.2.+ -. 2X 71.+ -. 2 mm; 218.2.+ -. 2X 75.+ -. 2 mm; 218.2.+ -. 2X 79.+ -. 2 mm; 218.2.+ -. 2X 83.+ -. 2 mm; 218.2.+ -. 2X 87.+ -. 2 mm; 218.2.+ -. 2X 91.+ -. 2 mm; 218.2.+ -. 2X 95.+ -. 2 mm; 218.2.+ -. 2X 99.+ -. 2 mm; 218.2.+ -. 2X 103.+ -. 2 mm; 218.2.+ -. 2X 107.+ -. 2 mm; group 3:
166+ -2×83+ -2 mm;
182 + -2X 91 + -2 mm;
210+ -2×105+ -2 mm;
218.2.+ -. 2X 109.1.+ -. 2mm.
11. A silicon rod assembly according to any one of claims 1 to 7 wherein the ratio of lengths of adjacent sides of a rectangular cross section of any one silicon rod is such that: greater than or equal to 1/90 and less than or equal to 89/90.
12. A silicon rod assembly as defined in any one of claims 1 to 7 wherein the silicon rod assembly comprises at least one silicon rod having a rectangular cross section with a length ratio of 2±0.2 on adjacent sides.
13. A rectangular silicon wafer combination is characterized in that,
The silicon wafer combination comprises N silicon wafers, wherein N is a positive integer greater than or equal to 2, wherein the two groups of opposite side lengths of the rectangular section of the 1 st silicon wafer are respectively a1 and b1, a1 is greater than or equal to b1, the two groups of opposite side lengths of the rectangular section of the 2 nd silicon wafer are respectively a2 and b2, a2 is greater than or equal to b2, the two groups of opposite side lengths of the rectangular section of the … … th (N-1) silicon wafer are respectively a (N-1) and b (N-1), a (N-1) is greater than or equal to b (N-1), the two groups of opposite side lengths of the rectangular section of the N-th silicon wafer are respectively aN and bN, aN is greater than or equal to bN, and a1 is greater than or equal to a2 and is greater than or equal to … … and is greater than or equal to a (N-1).
14. The silicon wafer assembly of claim 13, wherein when N = 2, the first silicon wafer rectangular cross-section a1 edge and the second silicon wafer rectangular cross-section a2 edge are joined to form a first combined cross-section pattern, the midpoint of the joined a1 edge and the midpoint of the joined a2 edge are coincident, the first combined cross-section pattern is circumscribed, and the ratio of the first combined cross-section pattern area to the circumscribed circle area is greater than or equal to 70%.
15. The silicon wafer assembly of claim 14, wherein the ratio of the first combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
16. The silicon wafer assembly of claim 13 wherein when N=3, the first silicon wafer rectangular section a1 edge and the second silicon wafer rectangular section a2 edge are bonded to form a first combined section pattern, the largest extension edge of the first combined section pattern is bonded to the third silicon wafer rectangular section a3 edge to form a second combined section pattern, the second combined section pattern is circumscribed, the ratio of the second combined section pattern area to the circumscribed circle area is greater than or equal to 70%,
The distance between the two farthest points of the second combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, one side length of the second combined section graph is the maximum extension, and the side is called as the maximum extension side.
17. The silicon wafer assembly of claim 16, wherein the ratio of the second combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
18. The silicon wafer assembly of claim 13 wherein when N > 3, the first silicon wafer rectangular cross-section a1 edge and the second silicon wafer rectangular cross-section a2 edge are joined to form a first combined cross-section pattern, the first combined cross-section pattern has a maximum extension edge joined to the third silicon wafer rectangular cross-section a3 edge to form a second combined cross-section pattern, the second combined cross-section pattern has a maximum extension edge joined to the third silicon wafer rectangular cross-section a3 edge to form a third combined cross-section pattern, the third combined cross-section pattern has a maximum extension edge joined to the fourth silicon wafer rectangular cross-section a4 edge to form a fourth combined cross-section pattern, and so on, the (N-1) th combined cross-section pattern is circumscribed, the (N-1) th combined cross-section pattern area to the circumscribed circle area ratio is greater than or equal to 70%,
The distance between the two farthest points of any combined section graph in the direction parallel to the a1 side is a first extension, the distance between the two farthest points in the direction perpendicular to the a1 side is a second extension, the larger one of the first extension and the second extension is called as the maximum extension of the combined section graph, and one side length of the combined section graph is the maximum extension, and the side is called as the maximum extension side.
19. The silicon wafer assembly of claim 18, wherein the ratio of the (N-1) th combined cross-sectional pattern area to the circumscribed circle area is greater than or equal to 80%.
20. The silicon wafer combination according to any one of claims 13 to 19, wherein the silicon wafer rectangular cross-section side length of the silicon wafer combination is selected from at least one of the following: 166+ -2 mm, 170.75 + -2 mm, 180+ -2 mm, 182+ -2 mm, 183.75 + -2 mm, 190+ -2 mm, 198+ -2 mm, 207+ -2 mm, 210+ -2 mm, 212+ -2 mm, 218+ -2 mm, 218.2+ -2 mm, 219+ -2 mm, 220+ -2 mm, 227.8+ -2 mm, 228+ -2 mm, 230+ -2 mm, 253+ -2 mm, 274+ -2 mm, 275+ -2 mm, 282+ -2 mm.
21. The silicon wafer combination according to any one of claims 13 to 19, wherein the rectangular cross-sectional dimension of the silicon wafer in the silicon wafer combination is selected from one, two or more of the following:
182+ -2×166+ -2 mm;
182 + -2X 170.75 + -2 mm;
182 + -2X 180 + -2 mm;
182 + -2X 182 + -2 mm;
183.75.+ -. 2X 182.+ -. 2 mm;
190+ -2×182+ -2 mm;
198+ -2×182+ -2 mm;
207.+ -. 2X 182.+ -. 2 mm;
210+ -2×182+ -2 mm;
212.+ -. 2X 182.+ -. 2 mm;
218.+ -. 2X 207.+ -. 2 mm;
218.2.+ -. 2X 182.+ -. 2 mm;
218.2.+ -. 2X 198.+ -. 2 mm;
218.2.+ -. 2X 210.+ -. 2 mm;
218.2.+ -. 2X 220.+ -. 2 mm;
218.8.+ -. 2X 207.+ -. 2 mm;
219.+ -. 2X 182.+ -. 2 mm;
220+ -2×182+ -2 mm;
227.8.+ -. 2X 182.+ -. 2 mm;
227.8.+ -. 2X 218.8.+ -. 2 mm;
228±2×182±2 mm;
253±2×182±2 mm;
253.+ -. 2X 218.+ -. 2 mm;
274.+ -. 2X 207.+ -. 2 mm;
274.+ -. 2X 227.8.+ -. 2 mm;
274.+ -. 2X 253.+ -. 2 mm;
275+ -2×198+ -2 mm;
275+ -2×210+ -2 mm;
275 + -2X 220 + -2 mm;
275+ -2×230+ -2 mm;
282±2×220±2 mm;
182 + -2X 72.5 + -2 mm;
182 + -2X 79.1 + -2 mm;
182 + -2X 79.75 + -2 mm;
182 + -2 x 87 + -2 mm;
182 + -2X 91.875 + -2 mm;
182 + -2X 96.6 + -2 mm;
182 + -2 x 96.75 + -2 mm;
182 + -2X 97 + -2 mm;
182 + -2X 98.8 + -2 mm;
182 + -2X 107.7 + -2 mm;
182 + -2X 108.6 + -2 mm;
182 + -2X 118.5 + -2 mm;
182 + -2X 124.1 + -2 mm;
182 + -2X 144.7 + -2 mm.
22. The silicon wafer combination according to any one of claims 13 to 19, wherein N.gtoreq.3, wherein the rectangular cross-sectional dimensions of the three silicon wafers are each selected from the following three groups
Group 1:
182 + -2X 93 + -2 mm;
182 + -2X 97 + -2 mm;
182 + -2 x 101 + -2 mm;
182 + -2X 105 + -2 mm;
182 + -2X 109 + -2 mm;
182 + -2X 113 + -2 mm;
182 + -2X 117 + -2 mm;
182 + -2X 121 + -2 mm;
182 + -2 x 125 + -2 mm;
182 + -2X 129 + -2 mm;
182 + -2X 136 + -2 mm;
182 + -2X 146 + -2 mm;
210+ -2×107+ -2 mm;
210+ -2×111+ -2 mm;
210+ -2×115+ -2 mm; 210+ -2×119+ -2 mm; 210+ -2×126+ -2 mm; 210+ -2×136+ -2 mm; 210+ -2×146+ -2 mm; 218.2.+ -. 2X 111.+ -. 2 mm; 218.2.+ -. 2X 115.+ -. 2 mm; 218.2.+ -. 2X 119.+ -. 2 mm; 218.2.+ -. 2X 126.+ -. 2 mm; 218.2.+ -. 2X 136.+ -. 2 mm; 218.2.+ -. 2X 146.+ -. 2 mm; group 2:
182 + -2X 73 + -2 mm; 182 + -2X 77 + -2 mm; 182 + -2X 81 + -2 mm; 182 + -2X 85 + -2 mm; 182 + -2X 89 + -2 mm; 210+ -2×71+ -2 mm; 210+ -2×75+ -2 mm; 210+ -2×79+ -2 mm; 210+ -2×83+ -2 mm; 210+ -2×87+ -2 mm; 210+ -2×91+ -2 mm; 210+ -2×95+ -2 mm; 210+ -2×99+ -2 mm; 218.2.+ -. 2X 71.+ -. 2 mm; 218.2.+ -. 2X 75.+ -. 2 mm; 218.2.+ -. 2X 79.+ -. 2 mm; 218.2.+ -. 2X 83.+ -. 2 mm;
218.2.+ -. 2X 87.+ -. 2 mm;
218.2.+ -. 2X 91.+ -. 2 mm;
218.2.+ -. 2X 95.+ -. 2 mm;
218.2.+ -. 2X 99.+ -. 2 mm;
218.2.+ -. 2X 103.+ -. 2 mm;
218.2.+ -. 2X 107.+ -. 2 mm;
Group 3:
166+ -2×83+ -2 mm;
182 + -2X 91 + -2 mm;
210+ -2×105+ -2 mm;
218.2.+ -. 2X 109.1.+ -. 2mm.
23. The silicon wafer combination according to any one of claims 13 to 19, wherein the ratio of lengths of adjacent sides of the rectangular cross section of any one of the silicon wafers satisfies: greater than or equal to 1/90 and less than or equal to 89/90.
24. The combination of any one of claims 13 to 19, wherein the combination of silicon wafers comprises at least one rectangular cross section of silicon wafer having a length ratio of 2±0.2 on adjacent sides.
25. A sliced product made from any one of the silicon wafers in combination with any one of claims 13 to 24, wherein the sliced product is a sliced silicon wafer obtained by cutting the any one of the silicon wafers.
26. The diced product of claim 25, wherein the diced product is a diced silicon wafer from any of the silicon halves, trisections, quarters, penta-quarters, hexa-quarters, or octa-quarters.
27. A battery sheet, characterized in that the battery sheet is manufactured from the sliced product according to any one of claims 25 or 26.
28. A photovoltaic module, characterized in that it is made from the cell sheet according to claim 27.
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| CN2022221325198 | 2022-08-12 | ||
| CN202222132519 | 2022-08-12 |
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| CN202311016960.2A Pending CN116885045A (en) | 2022-08-12 | 2023-08-11 | Preparation method of rectangular silicon wafer combination, battery and assembly |
| CN202322172851.1U Active CN220887774U (en) | 2022-08-12 | 2023-08-11 | Rectangular-section silicon rod combination, silicon wafer combination, sliced product, battery piece and photovoltaic module |
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| CN202310670742.4A Pending CN116825889A (en) | 2022-08-12 | 2023-06-07 | Cutting method, utilization method of segmented battery and photovoltaic roof |
| CN202311016960.2A Pending CN116885045A (en) | 2022-08-12 | 2023-08-11 | Preparation method of rectangular silicon wafer combination, battery and assembly |
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