CN114619578A - Silicon rod processing method, silicon wafer, battery and battery assembly - Google Patents

Silicon rod processing method, silicon wafer, battery and battery assembly Download PDF

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Publication number
CN114619578A
CN114619578A CN202210256202.7A CN202210256202A CN114619578A CN 114619578 A CN114619578 A CN 114619578A CN 202210256202 A CN202210256202 A CN 202210256202A CN 114619578 A CN114619578 A CN 114619578A
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silicon
silicon rod
processing
line
lines
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Inventor
王猛
成路
郭瑞波
张济蕾
李成博
相鹏飞
尚小端
郗磊
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Longi Green Energy Technology Co Ltd
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Longi Green Energy Technology Co Ltd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0011Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264Inorganic materials
    • H01L31/028Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The application discloses a silicon rod processing method, a silicon wafer, a battery and a battery pack, and relates to the technical field of solar photovoltaics. The silicon rod processing method comprises the following steps: arranging the contour machining line and the dividing line on the same end face of the silicon rod; the plurality of contour processing lines enclose and synthesize an N-shaped polygon, wherein N is more than or equal to 4 and is an integer; the dividing line intersects the at least two contour processing lines to divide the N-polygon into at least two polygons, the polygons including: one of a triangle, a rectangle, and a trapezoid; and simultaneously cutting the contour processing line and the dividing line from one end surface of the silicon rod to the other end surface along the direction parallel to the axis of the silicon rod so as to cut the silicon rod into silicon ingots with at least two polygonal end surfaces. According to the silicon rod processing method, at least two small cuboid silicon ingots can be prepared through one-time cutting, the cutting precision is high, the silicon loss is small, and the product quality and the production efficiency of half or 1/N batteries can be effectively improved.

Description

Silicon rod processing method, silicon wafer, battery and battery pack
Technical Field
The application belongs to the technical field of solar photovoltaics, and particularly relates to a silicon rod processing method, a silicon wafer, a battery and a battery assembly.
Background
With the development of photovoltaic technology, solar energy is widely popularized as a green, environment-friendly and renewable energy source. Monocrystalline silicon wafers for solar cells are generally cut from silicon rods. In order to take account of the material utilization rate of the silicon rod and ensure the photoelectric efficiency of the subsequent photovoltaic module, a round silicon rod is generally squared to obtain a square rod, and then the square rod is sliced to obtain a silicon wafer so as to prepare a solar cell with a larger size.
In the prior art, in order to meet the requirements of cells and modules, when there are different requirements on the size of a silicon wafer, for example, small-sized cells (half-cell or 1/N-cell), the whole solar cell is usually cut to form half-cell or 1/N-cell. However, the above method of directly cutting the whole cell to prepare the small-sized cell is easy to cause quality problems such as edge breakage and hidden cracking at the side edge of the small-sized cell due to cutting, which results in high production cost and low production efficiency of the small-sized silicon wafer.
Disclosure of Invention
The embodiment of the application aims to provide a silicon rod processing method, a silicon wafer, a battery and a battery pack, and can provide a method for producing a small-size silicon rod/silicon wafer with high efficiency and low cost, so that the problems that the product quality is influenced and the manufacturing cost is increased by cutting after a traditional silicon wafer is prepared into a battery piece finished product are solved.
In a first aspect, embodiments of the present application provide a silicon rod processing method, which includes the following steps:
arranging a cutting wire net: arranging a contour machining line and a dividing line on the same end face of the silicon rod;
the plurality of contour machining lines enclose and synthesize an N-shaped polygon, wherein N is more than or equal to 4 and is an integer; the dividing line intersects at least two of the contour machining lines to divide the N-polygon into at least two polygons, the polygons including: one of a triangle, a rectangle, and a trapezoid;
processing the silicon rod: and simultaneously cutting the contour machining line and the dividing line from one end face to the other end face of the silicon rod along the direction parallel to the axis of the silicon rod so as to cut the silicon rod into silicon ingots with at least two end faces being polygonal.
Optionally, at least two of the plurality of contour machining lines are arranged in parallel;
the dividing line is perpendicularly intersected with the two parallel contour machining lines.
Optionally, the number of the contour machining lines is four, and the four contour machining lines enclose a shape like a Chinese character jing.
Optionally, an intersection point of the dividing line and the contour processing line is located on a M-equal division point of the contour processing line; wherein M is more than or equal to 2.
Optionally, the number of the dividing lines is at least two, at least two dividing lines are perpendicularly intersected, or at least two dividing lines are parallel.
Optionally, at least one of the intersections of the dividing line and the contour processing line is an intersection of two adjacent contour processing lines.
Optionally, at least two of the polygons have the same shape, or at least two of the polygons have different shapes.
In a second aspect, an embodiment of the present application further provides a silicon wafer, where the silicon wafer is processed from a silicon ingot whose end face is polygonal; the silicon ingot is prepared by the silicon rod processing method.
In a third aspect, an embodiment of the present application further provides a battery, where the battery is prepared from the above silicon wafer.
In a fourth aspect, embodiments of the present application further provide a battery assembly, where the battery assembly includes: the battery is provided.
In the embodiment of the application, both the contour machining line and the dividing line are arranged on the end surface of the same side of the silicon rod; the plurality of contour processing lines enclose to form an N-polygon, and the dividing line intersects with at least two contour processing lines to divide the N-polygon into at least two polygons, wherein the polygons comprise: one of a triangle, a rectangle, and a trapezoid; then, the contour processing line and the dividing line are simultaneously cut from one end face to the other end face of the silicon rod along a direction parallel to the axis of the silicon rod, so that the silicon rod is cut into silicon ingots with at least two polygonal end faces. In practical application, when the N-edge is square, at least two silicon ingots with rectangular end surfaces can be cut and prepared at one time by the method, namely at least two small cuboid silicon ingots are cut and prepared at one time, the cutting precision is high, the silicon loss is small, the cuboid silicon ingots can be cut subsequently, can form half or 1/N silicon chips, and then prepare half or 1/N batteries through a battery process, compared with the traditional battery chip preparation method of 'square bar-slice-battery chip-half battery', the embodiment of the application can be prepared from the source of half battery preparation from the silicon rod cutting process, avoids the problems of edge breakage, hidden breakage and the like easily generated in the production of half battery chips in the traditional method, therefore, the product quality and the production efficiency of half or 1/N cell can be effectively improved.
Drawings
FIG. 1 is a flow chart illustrating the steps of a method for processing a silicon rod according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of a cutting corresponding to the method for processing a silicon rod according to the embodiment of the present application;
fig. 3 is a second schematic view of a cutting corresponding to the method for processing a silicon rod according to the embodiment of the present application;
FIG. 4 is a third schematic view of a cutting operation according to the method for processing a silicon rod of the embodiment of the present application;
fig. 5 is a fourth schematic diagram illustrating cutting according to the silicon rod processing method of the embodiment of the present application.
Description of the reference numerals
10: a contour machining line; 20: and (6) dividing the line.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or described herein. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The method for processing a silicon rod according to the embodiments of the present application is described in detail with reference to the accompanying drawings.
Referring to fig. 1, a flow chart of steps of a method for processing a silicon rod according to an embodiment of the present disclosure is shown. Referring to fig. 2 to 5, cutting diagrams corresponding to the method for processing the silicon rod according to the embodiment of the present application are shown.
In an embodiment of the present application, a method for processing a silicon rod may specifically include the following steps:
step 101, arranging a cutting wire net: arranging a contour machining line and a dividing line on the same end face of the silicon rod; the plurality of contour machining lines enclose to form an N-shaped polygon, wherein N is more than or equal to 4 and is an integer; the dividing line intersects at least two of the contour machining lines to divide the N-polygon into at least two polygons, the polygons including: one of triangular, rectangular, and trapezoidal.
In the present embodiment, the silicon rod may include, but is not limited to, a columnar silicon rod, and the present embodiment is explained by taking an original columnar silicon rod (a silicon rod without cutting a flaw-piece) as an example.
In the present embodiment, the contour machining line and the dividing line are conventional cutting lines for cutting silicon rods. In the embodiment of the application, the contour machining line is a cutting line close to the circumferential edge of the silicon rod, the contour machining line can be regarded as a flaw-piece cutting line of the silicon rod, and the contour machining line is used for removing a flaw-piece of the cylindrical silicon rod so as to cut the cylindrical silicon rod into square rods; the dividing line is a cutting line for dividing the central region of the silicon rod, and may be regarded as a square bar cutting line for cutting a square bar from which a flaw-piece is removed by outline processing line cutting, and dividing the square bar (the central region of the silicon rod) into at least two silicon ingots.
In the embodiment of the present application, the N-shaped polygon enclosed by the plurality of contour processing lines may include, but is not limited to: polygonal shapes such as square, rectangle, pentagon, hexagon, etc. Silicon ingots with polygonal end faces include, but are not limited to: the end face is a rectangular cuboid, the end face is a square cuboid, the end face is a triangular column, the end face is a trapezoidal column and the like.
In the embodiment of the present application, the shapes of at least two polygons are the same, or the shapes of at least two polygons are different. Taking the division line as an example, one division line can divide the N-polygon into two polygons having the same shape, for example, a square into two rectangles. Alternatively, one dividing line may divide the N-polygon into two polygons of different shapes, for example, a right trapezoid into a triangle and a rectangle.
In the embodiments of the present application, adjacent contour processing lines may be in direct contact or non-contact with each other, and the dividing line and the contour processing line may also be in direct contact or non-contact with each other. As shown in fig. 2, the contour machining line and the parting line may intersect each other when projected from one end surface of the silicon rod to the other end surface. In order to improve the wiring difficulty of the contour processing lines and the dividing lines, the contour processing lines and the dividing lines can be sequentially distributed in a staggered manner on the end surfaces of the same side of the silicon rod along the extension direction of the axis of the silicon rod.
In the embodiment of the application, the dividing line and the contour machining line can intersect at any position of the N-shaped polygon when the silicon rod is projected from one end surface to the other end surface. In some embodiments, at least one of the intersection points of the dividing line and the contour machining line is the intersection point of two adjacent contour machining lines, or is projected from one end face of the silicon rod to the other end face, and the projection of the dividing line on the N-polygon is located on at least one corner of the N-polygon. As shown in fig. 3, the dividing line is located at the intersection of the two contour machining lines. In other embodiments, the projections of the dividing lines on the N-polygon may also all be located on the sides of the N-polygon, as projected from one end face of the silicon rod to the other end face.
In some embodiments of the present application, at least two of the plurality of contour lines are arranged in parallel; the parting line is perpendicularly intersected with the two parallel contour machining lines. For example, when the contour machining lines enclose an isosceles trapezoid, the dividing lines may intersect perpendicularly with the contour machining lines on two parallel sides of the isosceles trapezoid, so that the dividing lines can divide the isosceles trapezoid into two right-angled trapezoids, that is, the contour machining lines and the dividing lines can process the silicon rod into two silicon ingots with right-angled trapezoid end surfaces at one time. It is understood that when the N-gon is a regular N-gon, and the dividing line perpendicularly intersects two parallel contour processing lines at the bisector of the contour processing lines, the N-gon may be cut into two identical polygons.
In the embodiment of the present application, the number of the contour processing lines may be greater than or equal to four, that is, the polygons enclosed by the contour processing lines are quadrangles, pentagons, and the like. For example, when the number of the outline processing lines is four, the four outline processing lines may be formed in a shape of a closed rectangle, or the four outline processing lines may be formed in a shape of a square, so that the round silicon rod may be processed into a square rod by cutting off the edge skin of the round silicon rod in one processing.
In the embodiment of the present application, the intersection point of the dividing line and the contour processing line may be located at the M-division point of the contour processing line; wherein M is more than or equal to 2. For example, the N-edge is a square, when M is 2, the square can be divided into two by the dividing line, that is, the profile processing line and the dividing line can cut off the edge skin of the silicon rod at one time, and simultaneously cut the silicon rod into rectangular square rods with two end faces having the same area, and then a half silicon wafer can be formed by slicing the rectangular square rods, thereby preparing a half cell. It can be understood that, when the N-edge is a square and M is 3, the square can be cut into two rectangles with an area ratio of 1:2 by the dividing line, and then 1/3 silicon wafers and 2/3 silicon wafers can be obtained by slicing, so as to prepare 1/3 cells and 2/3 cells (corresponding to the whole cells prepared by cutting silicon wafers by a conventional square rod). In the embodiment of the present application, M is usually an integer for simpler preparation of the battery piece, but in practical applications, M may also be a non-integer, and the embodiment of the present application is not limited herein.
In practical applications, the number of the dividing lines may be one, two or more. In the above embodiments of the present application, the relationship between each dividing line and the contour machining line is explained. As shown in fig. 2, when the number of the dividing lines is one, one dividing line and a plurality of profile processing lines cut the silicon rod into 5 number of the split edges and 2 number of the silicon ingots. In some embodiments of the present application, when the number of the dividing lines is at least two, at least two dividing lines intersect perpendicularly, or at least two dividing lines are parallel. For example, when the number of the dividing lines is two, the two dividing lines may perpendicularly intersect, as shown in fig. 4, to cut the silicon rod into 8 kerbs and 4 silicon ingots, or the two dividing lines may be parallel, as shown in fig. 5, to cut the silicon rod into 8 kerbs and 3 silicon ingots. When the number of the dividing lines is more than two, the two dividing lines can be parallel or perpendicular. Of course, the included angle between two arbitrarily intersecting dividing lines may be any value within a range of 0 to 180 °, and only a part of exemplary descriptions are given in the embodiments of the present application, and other references may be performed.
It is understood that, the number of the dividing lines and the relationship between each dividing line and the contour machining line can be set by those skilled in the art according to actual conditions, and the present application only gives some exemplary descriptions, and other references may be implemented.
It should be noted that, in the embodiment of the present application, the end surfaces of the profile processing line and the dividing line on the same side of the silicon rod may be alternately arranged, or the dividing line is arranged after the wire mesh of the profile processing line is arranged, or the profile processing line is arranged after the position of the dividing line is determined, and the wire mesh is cut in multiple arrangement modes, which may be set by a person skilled in the art according to circumstances and is not limited in the embodiment of the present application.
Step 102, processing the silicon rod: and simultaneously cutting the contour machining line and the dividing line from one end face to the other end face of the silicon rod along the direction parallel to the axis of the silicon rod so as to cut the silicon rod into silicon ingots with at least two end faces being polygonal.
In the embodiment of the application, the silicon ingot with at least two rectangular end surfaces can be cut and prepared at one time by simultaneously cutting the silicon ingot with one end surface to the other end surface through the contour processing line and the dividing line, namely, at least two cuboid silicon ingots are cut and prepared at one time, so that the cutting precision is high, and the silicon loss is small; compared with the traditional cell preparation mode of 'square bar-slice-cell slice-half cell', the cell preparation method can be used for preparing half cells or 1/N cells from the silicon rod cutting process, and the problems that the half cells are prone to edge breakage, hidden breakage and the like in the traditional mode are avoided, so that the product quality and the production efficiency of the half cells or the 1/N cells can be effectively improved.
As shown in fig. 2, the silicon rod can be cut at one time to obtain six edge skins and two rectangular square rods at the edges by the wiring mode of the contour processing line and the dividing line on the end surface of the silicon rod, the cutting precision is high, the silicon loss is small, and the problems of low cutting precision and more silicon loss caused by adopting a plurality of clamping procedures in the conventional silicon rod cutting are solved.
To sum up, in the silicon rod processing method according to the embodiment of the present application, the contour processing line and the dividing line are simultaneously cut from one end surface of the silicon rod to the other end surface, so that at least two silicon ingots with rectangular end surfaces can be cut and prepared at one time, that is, at least two rectangular silicon ingots can be cut and prepared at one time, and thus, the cutting precision is high, and the silicon loss is small; compared with the traditional cell preparation mode of 'square bar-slice-cell slice-half cell', the embodiment of the application can avoid the problems of edge breakage, hidden cracking and the like easily generated in the production of half cells in the traditional mode from the source of the half cell preparation in the silicon rod cutting process, so that the product quality and the production efficiency of the half cells or the 1/N cells can be effectively improved.
The embodiment of the application also provides a silicon wafer, which is processed by a silicon ingot with a polygonal end face; the silicon ingot is prepared by the silicon rod processing method.
In the embodiment of the present application, the silicon ingot prepared by the silicon rod processing method may have advantages such as high cutting accuracy and low silicon loss, and further, a silicon wafer processed from the silicon ingot may have the advantages.
It should be noted that, in the embodiments of the present application, the preparation method of the silicon wafer may refer to the above embodiments, and details of the present application are not repeated herein.
In the embodiment of the application, a silicon ingot is sliced to form a half piece or 1/N piece of silicon wafer, and then the half piece or 1/N piece of battery is prepared through a battery process, compared with the traditional battery piece preparation mode of 'square bar-slice-battery piece-half piece of battery', the embodiment of the application can be used for cutting a silicon rod from the source of the half piece of battery preparation, and the problems of edge breakage, hidden breakage and the like easily generated in the production of the half piece of battery piece in the traditional mode are avoided, so that the product quality and the production efficiency of the half piece or 1/N piece of battery can be effectively improved.
The embodiment of the application also provides a battery, and the battery is prepared from the silicon wafer.
It should be noted that, in the embodiments of the present application, the method for preparing a silicon wafer for a battery may refer to the above embodiments, and details of the present application are not described herein again.
In the embodiment of the present application, a method for preparing the silicon wafer into the battery is a method for preparing a battery using crystalline silicon as a substrate in the field, for example, an SE-BSF battery, a PERC battery, a double-sided battery, a Topcon battery or an HJT battery, which is not described herein again.
In the embodiment of the application, the half-cell or 1/N-cell can be directly prepared by the method, compared with the traditional cell preparation method of 'square rod-slice-cell-half-cell', the embodiment of the application can be from the source of the half-cell preparation in the silicon rod cutting process, and the problems that the half-cell is easy to break edges, crack and the like in the traditional method are avoided, so that the product quality and the production efficiency of the half-cell or 1/N-cell can be effectively improved.
The embodiment of the application also provides a battery assembly which comprises the battery.
It should be noted that, in the embodiments of the present application, the method for preparing a battery may refer to the above embodiments, and details of the present application are not repeated herein.
In the embodiment of the application, because the battery is a half-piece or 1/N-piece battery, compared with a traditional battery piece preparation method of 'square rod-slice-battery piece-half-piece battery', the embodiment of the application can avoid the problems of edge breakage, hidden breakage and the like easily generated in the production of the half-piece battery piece in the traditional method from the source of the silicon rod cutting process, namely the preparation of the half-piece battery, so that the product quality and the production efficiency of the half-piece or 1/N-piece battery can be effectively improved.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method for processing a silicon rod is characterized by comprising the following steps:
arranging a cutting wire net: arranging a contour machining line and a dividing line on the same end face of the silicon rod;
the plurality of contour machining lines enclose and synthesize an N-shaped polygon, wherein N is more than or equal to 4 and is an integer; the dividing line intersects at least two of the contour machining lines to divide the N-polygon into at least two polygons, the polygons including: one of a triangle, a rectangle, and a trapezoid;
processing the silicon rod: and simultaneously cutting the contour machining line and the dividing line from one end face to the other end face of the silicon rod along the direction parallel to the axis of the silicon rod so as to cut the silicon rod into silicon ingots with at least two end faces being polygonal.
2. The method for processing a silicon rod according to claim 1, wherein at least two of the plurality of contour processing lines are disposed in parallel;
the dividing line is perpendicularly crossed with the two parallel contour machining lines.
3. The method for processing the silicon rod as recited in claim 2, wherein the number of the texturing lines is four, and the four texturing lines enclose a # -shaped structure.
4. The method for processing the silicon rod as recited in claim 3, wherein an intersection of the dividing line and the contour processing line is located at a point of M bisector of the contour processing line; wherein M is more than or equal to 2.
5. The method of processing a silicon rod as set forth in claim 3, wherein the number of the dividing lines is at least two, at least two of the dividing lines intersect perpendicularly, or at least two of the dividing lines are parallel.
6. The method of processing the silicon rod as set forth in claim 1, wherein at least one of the intersections of the dividing line and the profile processing line is an intersection of two adjacent profile processing lines.
7. The method of processing a silicon rod as set forth in claim 1, wherein at least two of the polygons have the same shape or at least two of the polygons have different shapes.
8. The silicon wafer is characterized in that the silicon wafer is processed from a silicon ingot with a polygonal end face; the silicon ingot is prepared by the method for processing a silicon rod according to any one of claims 1 to 7.
9. A battery prepared from the silicon wafer of claim 8.
10. A battery assembly, comprising: the battery of claim 9.
CN202210256202.7A 2022-03-15 2022-03-15 Silicon rod processing method, silicon wafer, battery and battery assembly Pending CN114619578A (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2024032787A1 (en) * 2022-08-12 2024-02-15 隆基绿能科技股份有限公司 Silicon wafer combination for photovoltaic panel and silicon wafer masterslice therefor, square bar, silicon rod, and cell

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