CN220829712U - Chip based on FPGA replaces 1553B external RAM - Google Patents

Abstract

A chip based on an FPGA for replacing 1553B external RAM comprises an FPGA chip and a 1553B protocol chip, wherein an IP core of a dual-port RAM is used in the FPGA, one port of the dual-port RAM is connected with a CPU, the other port of the dual-port RAM is connected with the 1553B protocol chip, the time sequence for controlling the original external RAM is converted into the time sequence for controlling the dual-port RAM in the FPGA, and the time sequence for controlling the dual-port RAM comprises a clock signal, a high-efficiency chip selection signal EN, a read-write signal WE, an ADDRESS line ADDRESS, a data line WRITEDATA for writing data and a data line READDATA for reading data. The utility model discloses use the FPGA to replace external RAM and can save the expense of RAM chip, when designing the schematic diagram, can design a chip less, can effectually practice thrift the usage space of circuit board when drawing PCB, can be more simple and convenient when processing the circuit board, practiced thrift the cost.

Description

Chip based on FPGA replaces 1553B external RAM

Technical Field

The utility model relates to the technical field of chips, in particular to a chip based on an FPGA for replacing 1553B external RAM.

Background

The U.S. military data bus standard MILs-STD-1553B is a centralized control type, command/response and time division serial bus standard, is equipment interconnected in modern avionics integrated systems, the communication system is centralized controlled by one or more bus controllers, the implementation of 1553B protocol in an embedded system is not as simple as the implementation on a PC, a large amount of program storage space is required for the embedded system, a large amount of data buffer space is required for receiving data, a large amount of processing time is required for a main processor, the main processor as an embedded system generally has low processing capacity, a coprocessor RAM is generally added to implement the protocol, and the present domestic use of a 1553B bus protocol interface chip is almost all the same, the cost is high, the use of external RAM is complex, the external RAM is used for a large number of times and is easy to damage, and the whole functions are difficult to implement.

Disclosure of Invention

The utility model provides a chip based on FPGA to replace 1553B external RAM in order to solve the problems.

The utility model adopts the technical scheme that:

A chip based on an FPGA for replacing 1553B external RAM comprises an FPGA chip and a 1553B protocol chip, wherein an IP core of a dual-port RAM is used in the FPGA, one port of the dual-port RAM is connected with a CPU, the other port of the dual-port RAM is connected with the 1553B protocol chip, the time sequence for controlling the original external RAM is converted into the time sequence for controlling the dual-port RAM in the FPGA, and the time sequence for controlling the dual-port RAM comprises a clock signal, a high-efficiency chip selection signal EN, a read-write signal WE, an ADDRESS line ADDRESS, a data line WRITEDATA for writing data and a data line READDATA for reading data.

The clock of the 1553B protocol chip is 16MHz, and only one 50MHz clock signal is arranged in the FPGA.

The clock signal of the 1553B protocol chip and the clock signal of the FPGA are converted into 100MHz after the clock signal of 50MHz of the FPGA is subjected to phase-locked loop frequency multiplication, and then the signals sent out from the 1553B protocol chip are synchronized by one beat by using the clock of 100MHz of the FPGA.

The RAM used in the FPGA is a single-port RAM.

The 1553B protocol chip controls RAMCS _n, RAMOE _n and RAMWR _n signals of the RAM to be input into the FPGA, and the signals input by the 1553B are firstly beaten inside the FPGA to become synchronous signals.

The data line and the address line of the 1553B protocol chip are multiplexed by the FPGA and the RAM and are of an input-output bidirectional type.

The utility model has the beneficial effects that: the utility model discloses use the FPGA to replace external RAM and can save the expense of RAM chip, when designing the schematic diagram, can design a chip less, can effectually practice thrift the usage space of circuit board when drawing PCB, can be more simple and convenient when processing the circuit board, practiced thrift the cost. After the FPGA is used for replacing the 1553B external RAM, the problem that the external RAM is damaged after being used for a plurality of times is solved, and the maintenance cost is saved. After the RAM is moved into the FPGA, the RAM can be monitored in real time through the FPGA. Therefore, raw materials and working procedures are saved, and the operation, control and use are simpler and more convenient.

Drawings

Fig. 1 is a schematic diagram of RAM connection signals according to the present utility model.

FIG. 2 is a timing diagram of a control dual port RAM of the present utility model.

FIG. 3 is a timing diagram of an external RAM according to the present utility model.

Fig. 4 is a diagram of one scenario of the RAM data flow of the present utility model.

Fig. 5 is another case of RAM data flow according to the present utility model.

Detailed Description

A chip based on an FPGA for replacing 1553B external RAM comprises an FPGA chip and a 1553B protocol chip, wherein an IP core of a dual-port RAM is used in the FPGA, one port of the dual-port RAM is connected to a CPU, the other port of the dual-port RAM is connected to the 1553B protocol chip, the time sequence for controlling the original external RAM is converted into the time sequence for controlling the dual-port RAM in the FPGA, the time sequence for controlling the dual-port RAM comprises a clock signal, a high-efficiency chip selection signal EN, a read-write signal WE, an ADDRESS line ADDRESS, a data line WRITEDATA for writing data and a data line READDATA for reading data, the data line and the ADDRESS line of the RAM are supplied to the FPGA and the 1553B protocol chip, and the control signals of the RAM, namely chip selection, read-write enabling and the control signals are provided by the 1553B protocol chip.

The clock of the 1553B protocol chip is 16MHz, only one 50MHz clock signal is arranged in the FPGA, and the clock has no homologous clock, so that the control signal given by the 1553B protocol chip can be completely received by the FPGA chip, and the situation of lack of signals can not occur.

The clock signal of the 1553B protocol chip and the clock signal of the FPGA are converted into 100MHz after the clock signal of 50MHz of the FPGA is subjected to phase-locked loop frequency multiplication, and then the signal sent out from the 1553B protocol chip is synchronized by one beat by using the clock of 100MHz of the FPGA, so that the original asynchronous signal is converted into a synchronous signal and is used again, and therefore the FPGA can be guaranteed to receive the complete signal sent out from the 1553B protocol chip.

The RAM used in the FPGA is a single-port RAM, and a double-port RAM can be selected, so that the double-port RAM can better distinguish the flow direction of data, and the CPU and the 1553B protocol chip can conveniently operate the double-port RAM.

The signals RAMCS _n, RAMOE _n and RAMWR _n of the 1553B protocol chip control RAM are input into the FPGA, signals input by the 1553B protocol chip are firstly beaten into synchronous signals in the FPGA, an external RAM timing diagram is formed, CLK is a clock signal, RAMCS _n is a low-effective chip selection signal, namely the RAM is selected when the clock signal is low; RAMWR _n is a read-write signal, which when low, indicates write data, and when high, indicates read data; RAMOE _n is an active-low output enable signal, i.e., RAM outputs data to the outside when it is low; ADDRESS is the ADDRESS line; DATA is the DATA line as shown in fig. 3. Controlling the timing of a dual port RAM, as shown in fig. 2, CLK is a clock signal, EN is an active high chip select signal, i.e., the RAM is selected when it is high; WE is a read-write signal, which indicates write data when it is high and read data when it is low; ADDRESS is the ADDRESS line; WRITEDATA is a data line for writing data, and READDATA is a data line for reading data.

The data line and the address line of the 1553B protocol chip are multiplexed by the FPGA and the RAM, and are of a bidirectional type of input and output, whether 1553B is sent to the CPU or the RAM through the FPGA is firstly distinguished, then whether input or output is carried out is distinguished, if the RAM is to be removed, the data and the address flow direction of the RAM need to be known if the RAM is replaced by an FPGA internal module, as shown in fig. 4, one condition of the data flow direction of the RAM is shown in fig. 5, and the other condition of the data flow direction of the RAM is shown in fig. 5.

Whether the 1553B protocol chip is given to the CPU or the RAM can be distinguished through RAMCS _n and a read-write signal given by the CPU, if RAMCS _n is pulled low and the CPU read-write signal is not pulled high, the data and the address are given to the RAM, on the basis, if RAMOE _n is pulled low and RAMWR _n is pulled high, the data in the RAM is read by 1553B, and if RAMOE _n is pulled high and RAMWR _n is pulled low, the data is written into the RAM by 1553B. After the RAM is selected, it is explained that the address lines should be entered into the FPGA to the RAM, and that this direction should be entered.

One of the CPU read/write signals is pulled high and RAMCS _n is not pulled low, which indicates that the data and address are 1553B protocol chips of the CPU, and on the basis, the address line is input into the FPGA to the RAM, and the direction is input. If the read signal is pulled high, the data line should be the 1553B protocol chip fed into the FPGA and the input. If the write signal is pulled high, the data line should be FPGA to 1553B protocol chip.

If RAMCS _n is pulled down and one of the CPU read/write signals is pulled up, the CPU controls the RAM, and after the RAM is replaced by the FPGA, the RAM can be directly operated in the internal mode without considering the direction of the data line address line at the external interface. If RAMCS _n is asserted low and the CPU read signal is asserted high, this indicates that the CPU is reading data from RAM. If RAMCS _n is asserted low and the CPU write signal is asserted high, this indicates that the CPU is writing data to RAM.

After distinguishing CPU operation from 1553B external chip operation, the original time sequence for operating the external RAM needs to be converted into the time sequence for operating the internal RAM of the FPGA. In writing to RAM, the address and data to be written should be ready before the chip select and write enable are in place, ensuring the stability of the written address and data. In the reading operation, the address should be prepared in advance, so that the stability of the address is ensured.

When the 1553B external chip operates the RAM, the time sequence conversion time is not excessively long, so that the RAM is prevented from preparing data or changing data and addresses when the 1553B protocol chip takes the data.

The foregoing describes the embodiments of the present utility model in detail, but the description is only a preferred embodiment of the present utility model and should not be construed as limiting the scope of the utility model. All equivalent changes and modifications within the scope of the present utility model are intended to be covered by the present utility model.

Claims (6)

1. The chip based on the FPGA for replacing the 1553B external RAM is characterized by comprising an FPGA chip and a 1553B protocol chip, wherein an IP core of a dual-port RAM is used in the FPGA, one port of the dual-port RAM is connected to a CPU, the other port of the dual-port RAM is connected to the 1553B protocol chip, the time sequence for controlling the original external RAM is converted into the time sequence for controlling the dual-port RAM in the FPGA, and the time sequence for controlling the dual-port RAM comprises a clock signal, a high-efficiency chip selection signal EN, a read-write signal WE, an ADDRESS line ADDRESS, a data line WRITEDATA for writing data and a data line READDATA for reading data.

2. The chip based on the FPGA replacing 1553B external RAM according to claim 1, wherein the clock of the 1553B protocol chip is 16MHz, and only one 50MHz clock signal is provided in the FPGA.

3. The chip based on the 1553B external RAM of claim 2, wherein the clock signal of the 1553B protocol chip and the clock signal of the FPGA are converted into 100MHz after the clock signal of 50MHz of the FPGA is multiplied by a phase-locked loop, and then the signals sent out from the 1553B protocol chip are synchronized by one beat by using the clock of 100MHz of the FPGA.

4. The chip based on the FPGA replacing 1553B external RAM according to claim 3, wherein the RAM used in the FPGA is a single-port RAM.

5. The chip based on the FPGA for replacing the 1553B external RAM according to claim 4, wherein the 1553B protocol chip controls RAMCS _n, RAMOE _n and RAMWR _n signals of the RAM to be input into the FPGA, and signals input by the 1553B protocol chip are firstly beaten into the FPGA to become synchronous signals.

6. The chip of claim 5, wherein the data lines and address lines of said 1553B protocol chip are multiplexed with the FPGA and the RAM and are of the input-output bidirectional type.