CN220711506U - Clamp for testing Ethernet consistency - Google Patents
Clamp for testing Ethernet consistency Download PDFInfo
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- CN220711506U CN220711506U CN202322323838.1U CN202322323838U CN220711506U CN 220711506 U CN220711506 U CN 220711506U CN 202322323838 U CN202322323838 U CN 202322323838U CN 220711506 U CN220711506 U CN 220711506U
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Abstract
The utility model provides a clamp for testing the consistency of Ethernet, which comprises a microprocessor and a network card chip, wherein the microprocessor and the network card chip are both positioned on a printed circuit board; the output end of the microprocessor is connected to the signal input end of the network card chip; the signal output end of the network card chip is connected to a first connector on the printed circuit board; the first connector is in communication connection with a second connector on the device to be tested; the first connector is also connected to the waveform measurement module. The number of the first connectors is 1 or 2; and at least one first connector is connected to the second connector, the 3 rd pin of the first connector is connected to the 3 rd pin of the second connector; the 6 th pin of the first connector is connected to the 6 th pin of the second connector. The utility model adopts a mode that one jig card generates idle mode waveforms to control the equipment to be tested to send out test signals; the register is not required to be modified by the equipment to be tested, so that the working efficiency is improved and the testing cost is reduced.
Description
Technical Field
The utility model belongs to the technical field of network testing devices, and particularly relates to a clamp for testing the consistency of Ethernet.
Background
Consistency testing is widely used in various industries, and is normative as the name implies in the electronics industry. The consistency test of the physical layer is one of the most important uses of oscilloscopes in the last decade, and is always one of the most common nouns in the industry. Physical layer conformance testing originally originated from the USB2.0 standard, and was popularized by the USB-IF association and industry huge engine Intel corporation. Because of the increasing number of hosts (Host) and devices (devices) and hubs (Hub) adopting the USB2.0 standard, compatibility and divergence of physical layers and protocol layers between devices need to be solved, so a unified standardized measurement method is formulated to evaluate signal quality of each Device. The consistency test is similar to the black box test, and usually only focuses on the signal quality at the external interface of the equipment, and the corresponding Logo is marked through the consistency test approved by the association. Today consistency testing has been widely adopted by various large standards and protocol organizations, such as HDMI, displayPort, USB3.x, SATA/SAS, PCIExpress, thunderBolt, etc. It is widely accepted in the industry to employ a unified standard of test signals; a standard connection mode; standard test algorithms and procedures measure whether the signal quality of a product meets the general terms of standard tests, which are based on compliance test specifications CTS (Compliance Test Specification) defined by the respective standards and associations organization. By performing a consistency test on the product, the margin of each index of the signal from the CTS can be quantified in addition to knowing whether the product meets the standard test specification. If the margin is sufficient, this means that the product can be designed for reduced cost, whereas a redesign is required. For system manufacturers, in the presence of fast changing markets and intense competition, reducing the cost of products is a viable forensic. For an upstream chip manufacturer, if a system based on the chip can show very high allowance through consistency test, the system can show the performance of the product, and sufficient confidence and allowance are provided for the product design and development of downstream customers for cost reduction design. The consistency test is therefore of no relevance to the industry as a whole. Another organization in the industry correspondingly introduced the concept of a consistency test on the 10/100/1000BaseT test for evaluating the signal quality of each device. In performing the ethernet CTS evaluation, an important factor is why is the unified test signal, compliance Pattern, why is it necessary to define the unified test signal? Because the tests are performed using different code patterns, the measurement results obtained are also different. For example, the resulting ISI jitter must be different with the 0101 pattern and with the 00110011 pattern. Therefore, in order to unify and standardize measurement, the society and standard organization define a standard test pattern, so that the device to be tested sends out a standard Ethernet test signal, which can be generally realized by modifying register values, but ICs of different manufacturers have different register modifying modes, and the method needs to be executed according to a specific method after confirmation by the corresponding manufacturer; even some ICs do not provide registers for modification, in which case difficulties are encountered in generating standard test signals.
FIG. 1 shows a prior art clamp connection schematic diagram for consistency testing, and is generally processed by externally setting up a router to connect the (Tx) 1,2 pins of the LAN port to the (Rx) 3,6 pins of the DUT port, for the case that hundred megaEthernet test signals cannot be sent by modifying the register. The LAN port is set to work in hundred megaduplex/half duplex mode, sends out idle mode waveform, and the router is used as link partner, so that DUT with auto-negotiation capability configures itself into hundred megamode after detecting the waveform, and starts to return to the same idle mode waveform. The prior art requires router equipment and two wires, and the wires require manual wiring. And some router network card chips cannot send out hundred megaidle mode waveforms after being set to hundred megafull duplex/half duplex modes, so that obvious defects exist.
Disclosure of Invention
In order to solve the technical problems, the utility model provides a clamp for testing the consistency of the Ethernet, which adopts a mode that a clamp generates an idle mode waveform to control equipment to be tested to send out a test signal; no register modification is required for the device under test.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the clamp for testing the Ethernet consistency comprises a microprocessor and a network card chip, wherein the microprocessor and the network card chip are both positioned on a printed circuit board;
the output end of the microprocessor is connected to the signal input end of the network card chip; the signal output end of the network card chip is connected to a first connector on the printed circuit board; the first connector is in communication connection with a second connector on the device to be tested;
the first connector is also connected to a waveform measurement module.
Further, the number of the first connectors is 1 or 2; and at least one first connector is connected to the second connector.
Further, the at least one first connector is connected to the second connector, and specifically further includes: the first connector connected with the second connector is connected with the waveform measuring module.
Furthermore, the waveform measuring equipment adopts an oscilloscope; the first connector, which is connected with the second connector, is connected with an oscilloscope probe.
Furthermore, the microprocessor adopts an MCU chip.
Further, the model of the MCU chip is YF8A051F.
Further, the network card chip adopts an X710 network card chip.
Further, the first connector is an RJ54 connector.
Further, the second connector adopts an RJ54 connector.
Further, pin 3 of the first connector is connected to pin 3 of the second connector; the 6 th pin of the first connector is connected to the 6 th pin of the second connector.
The effects provided in the summary of the utility model are merely effects of embodiments, not all effects of the utility model, and one of the above technical solutions has the following advantages or beneficial effects:
the utility model provides a clamp for testing the consistency of Ethernet, which comprises a microprocessor and a network card chip, wherein the microprocessor and the network card chip are both positioned on a printed circuit board; the output end of the microprocessor is connected to the signal input end of the network card chip; the signal output end of the network card chip is connected to a first connector on the printed circuit board; the first connector is in communication connection with a second connector on the device to be tested; the first connector is also connected to a waveform measurement module. The 3 rd pin of the first connector is connected to the 3 rd pin of the second connector; the 6 th pin of the first connector is connected to the 6 th pin of the second connector. The utility model adopts a mode that one jig card generates idle mode waveforms to control the equipment to be tested to send out test signals; no register modification is required for the device under test.
The fixture for testing the Ethernet consistency simplifies connecting wires and additional equipment, saves time and cost, and improves the efficiency of testing staff.
The clamp for testing the Ethernet consistency can simultaneously control two network ports of a DUT, avoid restarting an interface switching test during testing, improve the working efficiency and reduce the testing cost.
The clamp for testing the Ethernet consistency can be used for verifying signals of different IC chips, so that the testing method is simpler and more uniform.
Drawings
FIG. 1 is a clamp connection schematic diagram of a prior art consistency test;
fig. 2 is a schematic diagram of a fixture connection for ethernet conformance testing according to embodiment 1 of the present utility model.
Detailed Description
In order to clearly illustrate the technical features of the present solution, the present utility model will be described in detail below with reference to the following detailed description and the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different structures of the utility model. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Furthermore, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily obscure the present utility model.
Example 1
The embodiment 1 of the utility model provides a clamp for testing the consistency of Ethernet, which is used for solving the technical problem that extra equipment is required in the prior art, and a router is required in the prior art; two net wires; the 1,2 pins, 3,6 pins of the net wire need to be connected manually. The test fixture is arranged by the MCU and the network card chip, the idle mode waveform is provided for inducing the equipment to be tested to send out standard test signals through the self-made test fixture, and meanwhile signals generated by the equipment to be tested are sent into the oscilloscope to complete the consistency test of the Ethernet, so that the connecting wires and additional equipment are simplified, the time and the cost are saved, and the efficiency of test staff is improved.
Fig. 2 is a schematic diagram of a fixture connection for ethernet conformance testing according to embodiment 1 of the present utility model. The system comprises a microprocessor and a network card chip, wherein the microprocessor and the network card chip are both positioned on a printed circuit board;
the output end of the microprocessor is connected to the signal input end of the network card chip; the signal output end of the network card chip is connected to a first connector on the printed circuit board; the first connector is in communication connection with a second connector on the device to be tested; the first connector is also connected to the waveform measurement module.
The number of the first connectors is 1 or 2; and at least one first connector is connected to the second connector.
The at least one first connector is connected to the second connector specifically further comprises: the first connector connected with the second connector is connected with the waveform measuring module.
The waveform measuring equipment adopts an oscilloscope; the first connector, which is connected with the second connector, is connected with an oscilloscope probe.
The microprocessor adopts an MCU chip, and the model of the MCU chip is YF8A051F.
The network card chip adopts an X710 network card chip.
The first connector is an RJ54 connector. The second connector is an RJ54 connector.
The 3 rd pin of the first connector is connected to the 3 rd pin of the second connector; the 6 th pin of the first connector is connected to the 6 th pin of the second connector.
The specific working process of the clamp for testing the Ethernet consistency comprises the following steps: the MCU chip is connected to the network card chip, and the network card chip is connected to the RJ45 connector. The MCU (YF 8A 051F) chip generates a group of X1 PCIE2.0 signals to the network card chip (X710), the network card chip generates MDI signals to the first connector RJ54, and correct impedance and line control requirements are set for corresponding signal lines according to the requirements of each signal Bus of the chip.
In the application, the MCU works in a 100M full duplex mode and can send out an idle mode waveform; after receiving the idle mode waveform, the device to be tested with auto-negotiation capability configures itself as 100M mode, and starts to return to the idle mode waveform, and for 100M mode, the idle mode waveform is the standard test signal.
And the connection probe introduces the signal sent by the DUT into the oscilloscope to carry out the complex test, thus completing the signal consistency test work of the Ethernet.
The embodiment 1 of the utility model provides a clamp for testing the consistency of Ethernet, which adopts a mode that one clamp generates idle mode waveforms to control equipment to be tested to send out test signals; no register modification is required for the device under test.
The clamp for testing the Ethernet consistency provided by the embodiment 1 of the utility model simplifies connecting wires and additional equipment, saves time and cost, and improves the efficiency of testing staff.
The clamp for testing the consistency of the Ethernet, provided by the embodiment 1 of the utility model, can simultaneously control two network ports of a DUT, avoid restarting the interface replacement test during testing, and improve the working efficiency and the testing cost.
The clamp for testing the Ethernet consistency provided by the embodiment 1 of the utility model can be used for verifying signals of different IC chips, so that the testing method is more concise and unified.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is inherent to. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In addition, the parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of the corresponding technical solutions in the prior art, are not described in detail, so that redundant descriptions are avoided.
While the specific embodiments of the present utility model have been described above with reference to the drawings, the scope of the present utility model is not limited thereto. Other modifications and variations to the present utility model will be apparent to those of skill in the art upon review of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. On the basis of the technical scheme of the utility model, various modifications or variations which can be made by the person skilled in the art without the need of creative efforts are still within the protection scope of the utility model.
Claims (10)
1. The clamp for testing the Ethernet consistency is characterized by comprising a microprocessor and a network card chip, wherein the microprocessor and the network card chip are both positioned on a printed circuit board;
the output end of the microprocessor is connected to the signal input end of the network card chip; the signal output end of the network card chip is connected to a first connector on the printed circuit board; the first connector is in communication connection with a second connector on the device to be tested;
the first connector is also connected to a waveform measurement module.
2. The fixture for ethernet compliance testing according to claim 1, wherein said first connectors are 1 or 2 in number; and at least one first connector is connected to the second connector.
3. The ethernet conformance test fixture of claim 1, wherein said at least one first connector is connected to a second connector further comprising: the first connector connected with the second connector is connected with the waveform measuring module.
4. A clamp for testing the consistency of the Ethernet as recited in claim 3, wherein said waveform measuring module employs an oscilloscope; the first connector, which is connected with the second connector, is connected with an oscilloscope probe.
5. The fixture for testing the consistency of the Ethernet as recited in claim 1, wherein said microprocessor is an MCU chip.
6. The fixture for ethernet compliance testing according to claim 5, wherein said MCU chip is model YF8a051F.
7. The fixture for testing ethernet consistency of claim 1, wherein the network card chip is an X710 network card chip.
8. A clamp for testing ethernet compliance according to claim 3, wherein the first connector is an RJ54 connector.
9. A clamp for testing ethernet compliance according to claim 3, wherein said second connector is an RJ54 connector.
10. The fixture for ethernet compliance testing according to claim 9, wherein pin 3 of said first connector is connected to pin 3 of a second connector; the 6 th pin of the first connector is connected to the 6 th pin of the second connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322323838.1U CN220711506U (en) | 2023-08-29 | 2023-08-29 | Clamp for testing Ethernet consistency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322323838.1U CN220711506U (en) | 2023-08-29 | 2023-08-29 | Clamp for testing Ethernet consistency |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220711506U true CN220711506U (en) | 2024-04-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322323838.1U Active CN220711506U (en) | 2023-08-29 | 2023-08-29 | Clamp for testing Ethernet consistency |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220711506U (en) |
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2023
- 2023-08-29 CN CN202322323838.1U patent/CN220711506U/en active Active
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