CN220651661U - Testing arrangement of FLASH PROM based on ATE - Google Patents
Testing arrangement of FLASH PROM based on ATE Download PDFInfo
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- CN220651661U CN220651661U CN202322428451.2U CN202322428451U CN220651661U CN 220651661 U CN220651661 U CN 220651661U CN 202322428451 U CN202322428451 U CN 202322428451U CN 220651661 U CN220651661 U CN 220651661U
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- 238000012360 testing method Methods 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 230000003287 optical effect Effects 0.000 claims abstract description 8
- 238000011161 development Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000012795 verification Methods 0.000 description 4
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model relates to the technical field of chip testing, in particular to a testing device of FLASH PROM based on ATE, which comprises: the test device comprises a test substrate, wherein the test substrate is provided with a chip connecting seat, the chip connecting seat is adapted with a test chip, and two sides of the test substrate are respectively and fixedly provided with a J2 connector and a J3 connector which are electrically connected with the chip connecting seat; an optical coupler and an FPGA chip are electrically connected between the J2 connector and the chip connecting seat; the chip connecting seat is electrically connected with a resistor and a capacitor; the test substrate is connected with the ATE tester through the J2 connector and the J3 connector, and the J2 connector is provided with an electric energy setting pin, and the electric energy setting pin comprises A1, A2 and A3. The utility model simplifies the test process of SM32PFS48 through the improved test substrate, reduces the development and cost of the test environment, and meets the test requirements of high test speed and precision.
Description
Technical Field
The utility model relates to the technical field of chip testing, in particular to a testing device of FLASH PROM based on ATE.
Background
Flash PROM (Programmable Read-Only Memory) is a nonvolatile Memory with programmable and read-Only features. With the rapid development of computers and electronic devices, the conventional ROM (read only memory) cannot meet the requirements of users, and Flash PROMs are rapidly developed and adapted to FPGA. As Flash PROMs become more complex, so too are the requirements for reliability tests and screening, and the testing requirements for PROMs become more stringent.
Aiming at the problems of expanding the application range of the current Flash PROM product and improving the reliability of the Flash PROM during use, the automatic configuration detection technology is carried out on the Flash PROM based on the ATE design. The development time and cost of the test environment can be reduced, and the test sum ratio is high in test speed and precision.
Disclosure of Invention
The utility model provides a test device of a FLASH PROM based on ATE, which simplifies the test process of SM32PFS48 through an improved test substrate, reduces the development of a test environment and the cost, meets the test and has high test speed and precision.
In order to achieve the above purpose, the present utility model provides the following technical solutions: an ATE-based FLASH PROM test apparatus, comprising: the test device comprises a test substrate, wherein the test substrate is provided with a chip connecting seat, the chip connecting seat is adapted with a test chip, and two sides of the test substrate are respectively and fixedly provided with a J2 connector and a J3 connector which are electrically connected with the chip connecting seat; an optical coupler and an FPGA chip are electrically connected between the J2 connector and the chip connecting seat; the chip connecting seat is electrically connected with a resistor and a capacitor; the test substrate is connected with the ATE tester through the J2 connector and the J3 connector, and the J2 connector is provided with an electric energy setting pin, and the electric energy setting pin comprises A1, A2 and A3.
Preferably, the device further comprises a U2 connector, wherein the U2 connector is arranged on the test substrate and located between the J2 connector and the chip connecting seat, the U2 connector and the J2 connector are electrically connected with the chip connecting seat, and the FPGA chip is mounted on the U2 connector.
Preferably, the optical coupler further comprises a first socket, the first socket is electrically connected with the J2 connector and the chip connecting seat, and the optical coupler is installed on the first socket.
Preferably, the portable electronic device further comprises a second socket and a third socket, wherein the second socket and the third socket are electrically connected with the chip connecting seat, and the resistor and the capacitor are respectively arranged on the second socket and the third socket.
The utility model has the beneficial effects that: the test device simplifies the test process of the SM32PFS48 through the improved test substrate, reduces the development and cost of the test environment, and meets the test requirements and has high test speed and precision.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the overall structure of the present utility model;
FIG. 2 is a partial alignment chart of a test substrate according to the present utility model.
In the figure: 1. testing the substrate; 2. a chip connecting seat; 3. a J2 connector; 4. a J3 connector; 5. an optical coupler; 6. an FPGA chip; 7. a resistor; 8. a capacitor; 9. an electric energy setting pin; 10. u2 connector.
Detailed Description
The following description of the embodiments of the present utility model will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Referring to fig. 1 and 2, a test device for a FLASH PROM based on ATE includes: the test device comprises a test substrate 1, wherein the test substrate 1 is provided with a chip connecting seat 2, the chip connecting seat 2 is adapted with a test chip, and a J2 connector 3 and a J3 connector 4 which are electrically connected with the chip connecting seat 2 are respectively and fixedly arranged on two sides of the test substrate 1; an optocoupler 5 and an FPGA chip 6 are electrically connected between the J2 connector 3 and the chip connecting seat 2; the chip connecting seat 2 is electrically connected with a resistor 7 and a capacitor 8; the test substrate 1 is connected with an ATE tester through the J2 connector 3 and the J3 connector 4, and the J2 connector 3 is provided with a power setting pin 9, and the power setting pin 9 comprises A1, A2 and A3. The device further comprises a U2 connector 10, wherein the U2 connector 10 is arranged on the test substrate 1 and located between the J2 connector 3 and the chip connecting seat 2, the U2 connector 10 and the J2 connector 3 are electrically connected with the chip connecting seat 2, and the FPGA chip 6 is mounted on the U2 connector 10. The optical coupler 5 is mounted on the first socket. The chip module further comprises a second socket and a third socket, wherein the second socket and the third socket are electrically connected with the chip connecting seat 2, and the resistor 7 and the capacitor 8 are respectively arranged on the corresponding second socket and third socket.
In the above arrangement, the test substrate 1 is mounted inside the ATE tester, the SM32PFS48 is mounted on the chip connecting base 2 as a test chip, wherein according to the test requirement of the SM32PFS48, the two optocouplers 5 are AQY EH and are mounted on the first socket, and the 6 resistors 7 and the 6 capacitors 8 meeting the test requirement are respectively mounted on the second socket and the third socket.
In the test process, a first mode, a main string configuration mode, is tested, the mode sets the electrical performance of the electrical energy setting pins 9a1, a2 and a3 on the J2 connector 3 to 000, then the configuration of the FPGA chip 6 and the chip connection seat on the U2 connector 10 is set through the AQY211EH optocoupler 5, and the writing, verification, test, erasure, empty checking and the like of the SM32PFS48 main string configuration mode are completed through program power-up setting.
Next, the second mode is tested again, and from the string configuration mode, the electrical performance of the power setting pins 9a1, a2 and a3 on the J2 connector 3 is set to 111, then the FPGA chip 6 on the U2 connector 10 is set to be configured with the chip connection base through the AQY211EH optocoupler 5, and the writing, verification, test, erasure, blank checking and the like of the SM32PFS48 main string configuration mode are completed through the program power-up setting.
Next, a third mode, a master parallel configuration mode, is tested, the mode sets the electrical performance of the power setting pins 9a1, a2 and a3 on the J2 connector 3 to 100, then the FPGA chip 6 on the U2 connector 10 is set to be configured with the chip connection base through the AQY211EH optocoupler 5, and the writing, verification, test, erasure, empty checking and the like of the SM32PFS48 master string configuration mode are completed through program power-up setting.
Next, a fourth mode is tested again, and a mode is configured, wherein the mode sets the electrical properties of the power setting pins 9a1, a2 and a3 on the J2 connector 3 to 011, then the FPGA chip 6 on the U2 connector 10 is set to be configured with the chip connection base through the AQY211EH optocoupler 5, and the writing, verification, test, erasure, blank checking and the like of the SM32PFS48 main string configuration mode are completed through program power-up setting.
In summary, the test device simplifies the test process of the SM32PFS48 through the improved test substrate 1, reduces the development and cost of the test environment, and meets the test requirements and has high test speed and precision.
The foregoing is merely illustrative of the present utility model, and the present utility model is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.
Claims (4)
1. An ATE-based FLASH PROM test apparatus, comprising:
the test device comprises a test substrate (1), wherein the test substrate (1) is provided with a chip connecting seat (2), the chip connecting seat (2) is adapted with a test chip, and a J2 connector (3) and a J3 connector (4) which are electrically connected with the chip connecting seat (2) are respectively and fixedly arranged on two sides of the test substrate (1);
an optocoupler (5) and an FPGA chip (6) are electrically connected between the J2 connector (3) and the chip connecting seat (2);
the chip connecting seat (2) is electrically connected with a resistor (7) and a capacitor (8);
the test substrate (1) is connected with an ATE tester through the J2 connector (3) and the J3 connector (4), and the J2 connector (3) is provided with an electric energy setting pin (9), and the electric energy setting pin (9) comprises A1, A2 and A3.
2. The ATE-based FLASH PROM test apparatus of claim 1, wherein: the test device comprises a test substrate (1), and is characterized by further comprising a U2 connector (10), wherein the U2 connector (10) is arranged on the test substrate (1) and positioned between the J2 connector (3) and the chip connecting seat (2), the U2 connector (10) and the J2 connector (3) are electrically connected with the chip connecting seat (2), and the FPGA chip (6) is arranged on the U2 connector (10).
3. The ATE-based FLASH PROM test apparatus of claim 1, wherein: the optical coupler comprises a J2 connector (3) and a chip connecting seat (2), and is characterized by further comprising a first socket, wherein the first socket is electrically connected with the J2 connector and the chip connecting seat (2), and the optical coupler (5) is installed on the first socket.
4. The ATE-based FLASH PROM test apparatus of claim 1, wherein: the chip module further comprises a second socket and a third socket, wherein the second socket and the third socket are electrically connected with the chip connecting seat (2), and the resistor (7) and the capacitor (8) are respectively arranged on the corresponding second socket and third socket.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322428451.2U CN220651661U (en) | 2023-09-07 | 2023-09-07 | Testing arrangement of FLASH PROM based on ATE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322428451.2U CN220651661U (en) | 2023-09-07 | 2023-09-07 | Testing arrangement of FLASH PROM based on ATE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220651661U true CN220651661U (en) | 2024-03-22 |
Family
ID=90294086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322428451.2U Active CN220651661U (en) | 2023-09-07 | 2023-09-07 | Testing arrangement of FLASH PROM based on ATE |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220651661U (en) |
-
2023
- 2023-09-07 CN CN202322428451.2U patent/CN220651661U/en active Active
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