CN220627801U - Electronic device - Google Patents

Abstract

An electronic device is disclosed. In some embodiments, the electronic device includes: chip, heat sink and flexible circuit structure. The flexible circuit structure is arranged between the chip and the heat dissipation member, and the flexible circuit structure can be used for providing power to the chip through the passive surface of the chip. In the electronic device, the soft circuit structure is arranged between the chip and the heat dissipation part to provide power for the passive surface of the chip, so that an effective power path for the passive surface of the chip is provided, and the signal and the power are split, so that the design complexity and difficulty of the substrate can be reduced. And the difficulty in laying the circuit can be reduced by adopting the flexible circuit structure.

Description

Electronic device

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to an electronic device.

Background

As the number of I/O (input/output) of a chip increases, the power (power) line and the signal line of the current chip are disposed on the same side of the chip, which results in interference of signals for chip operation and further results in increased complexity and difficulty of substrate design. And, as shown in fig. 1A and 1B, the advanced chip design trend is to encapsulate a plurality of chips 12 (e.g., not less than 4)Mounted on a single substrate 20, for example, 4 chips 12 are encapsulated by molding compound 30 on a single substrate 20. Since a plurality of chips 12 are packaged, the number of I/os over a single substrate 20 increases, and the size of the substrate 20 is typically large (e.g., may be greater than 80×80mm ² ) The complexity and difficulty of the substrate design are also increased.

Therefore, in the prior art, the power line of the chip is designed on the passive surface (also referred to as the back side) of the chip, so as to effectively shunt the signal path and the power path, and reduce the difficulty of designing the substrate. However, in this design, it is necessary to consider the power supply path for external power to the passive surface of the chip, and in particular, in a package structure having a heat sink design and a package structure having a plurality of chips packaged on a single substrate, there is no effective power supply path design for supplying external power to the passive surfaces of the chips.

Disclosure of Invention

In view of the above problems, the present application provides an electronic device having at least a power path for supplying power to a passive surface of a chip, so as to realize signal and power splitting.

The technical scheme of the application is realized as follows:

according to one aspect of the present application, there is provided an electronic device comprising: a chip; a heat sink; and the flexible circuit structure is arranged between the chip and the heat dissipation piece and is used for providing power for the chip through the passive surface of the chip.

In some embodiments, the flexible circuit structure is connected to the heat sink through an adhesive layer.

In some embodiments, a gap is provided between the flexible circuit structure and the heat sink.

In some embodiments, the gap is located at a bend of the heat sink.

In some embodiments, the chip includes a plurality of functional regions, and the flexible circuit structure has a plurality of patterned regions corresponding to the plurality of functional regions.

In some embodiments, the heat sink has a lower surface facing the chip, a portion of the lower surface of the heat sink being exposed from the flexible circuit structure.

In some embodiments, the flexible circuit structure includes a body portion connected to the heat sink and a conductive member to electrically connect the body portion to the chip, wherein the body portion is spaced apart from the chip by the conductive member.

In some embodiments, the electronic device further comprises a substrate carrying the heat spreader and the chip; and a first clamping member electrically connecting the substrate and the heat sink, wherein the first clamping member has a first recess, and a portion of the heat sink is disposed in the first recess.

In some embodiments, the electronic device further includes a second clamping member electrically connecting the chip and the flexible circuit structure, wherein the second clamping member has a second recess, and a portion of the flexible circuit structure is disposed in the second recess.

In some embodiments, the body portion of the flexible circuit structure is spaced apart from the chip by a conductive member and is electrically connected to the chip by a conductive member, the conductive member including a metal post received in the second clamping member.

The beneficial effects of the technical scheme include: the soft circuit structure is arranged between the chip and the radiating piece to provide power for the passive surface of the chip, so that an effective power path for the passive surface of the chip is provided, and the signal and power are split, so that the complexity and difficulty of the design of the substrate can be reduced. And the difficulty in laying the circuit can be reduced by adopting the flexible circuit structure.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1A is a schematic cross-sectional view of a conventional package structure in which a plurality of chips are packaged.

FIG. 1B is a schematic top view of the chips of FIG. 1A on a substrate.

Fig. 2 is a schematic cross-sectional view of an electronic device according to one embodiment of the present application.

Fig. 3A, 4A, 5A, and 6A are schematic cross-sectional views at various steps in forming the electronic device shown in fig. 2, respectively.

Fig. 3B, 4B, 5B, and 6B are schematic top views at various steps of forming the electronic device shown in fig. 2, respectively.

Fig. 7A is a schematic cross-sectional view of a heat sink according to some embodiments.

Fig. 7B is a plan view of the heat sink and circuit structure of fig. 7A.

Fig. 8A is a schematic cross-sectional view of an electronic device according to another embodiment of the present application.

Fig. 8B is a schematic cross-sectional view of the attachment of the flexible circuit structure to the heat sink.

Fig. 8C is a schematic top view of the electronic device of fig. 8A.

Fig. 8D is a plan view of the heat spreader and flexible circuit structure of fig. 8A.

Fig. 9A is a schematic cross-sectional view of an electronic device according to another embodiment.

Fig. 9B is a perspective view of a first clamping member according to some embodiments.

Fig. 9C is a side view of the region S1 in fig. 9A along the direction D1.

Fig. 9D is a partially enlarged schematic view at a region S2 in fig. 9A.

Fig. 10 is a schematic cross-sectional view of an electronic device according to another embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 2 is a schematic cross-sectional view of an electronic device 100 according to one embodiment of the present application. Referring to fig. 2, the electronic device 100 includes a chip 110, a heat sink 120, and a substrate 130, the substrate 130 carrying the heat sink 120 and the chip 110. The chip 110 has a passive face 110b (which may also be referred to as a backside) and an active face 110f (which may also be referred to as a front side). In the present embodiment, the passive surface 110b of the chip 110 faces the heat sink 120, and the active surface 110f faces the substrate 130.

The electronic device 100 further includes a circuit structure 150 disposed between the chip 110 and the heat sink 120, and the circuit structure 150 is configured to provide power to the chip 110 through the passive surface 110b of the chip 110. In some embodiments, the power provided to the passive face 110b of the chip 110 may be from an external power source 139, and the substrate 130 may be electrically connected to the external power source 139 through electrical connections 132 (e.g., solder balls) under the substrate 130. Specifically, the power path Lp for supplying power to the passive surface 110b of the chip 110 reaches the passive surface 110b of the chip 110 from the external power source 139 via the electrical connector 132, the substrate 130, and the circuit structure 150. The active surface 110f of the chip 110 can be used for providing signal I/O, so as to realize signal and power split.

The passive face 110b of the chip 110 is provided with power by providing the circuit structure 150 between the chip 110 and the heat sink 120, thereby providing an efficient power path Lp for providing power to the passive face 110b of the chip 110. In addition, by effectively supplying power to the passive surface 110b of the chip 110, signal and power splitting is realized, so that the complexity and difficulty of the design of the substrate can be reduced.

With continued reference to fig. 2, the heat sink 120 has a lower surface 122 facing the chip 110. The lower surface 122 includes a first partial surface 122a bonded to the substrate 130, a second partial surface 122b recessed away from the substrate 130 relative to the first partial surface 122a, and a third partial surface 122c connecting the first partial surface 122a and the second partial surface 122b. The heat sink 120 includes a cover portion 120a extending laterally over the chip 110, and a support portion 120b extending from an edge of the cover portion 120a toward the substrate 130, so that the heat sink 120 can accommodate the chip 110. The first partial surface 122a is a bottom surface of the supporting portion 120b, and the second partial surface 122b is a bottom surface of the cover portion 120 a.

The circuit structure 150 may include an insulating layer 152 connected to the lower surface 122 of the heat spreader 120, and conductive traces 154 disposed in the insulating layer 152. The insulating layer 152 extending along the heat spreader 120 and the conductive traces 154 therein may be referred to as a body portion of the circuit structure 150. The circuit structure 150 may also include a conductive feature 158 and a conductive feature 159 that electrically connect the conductive traces 154. Conductive feature 158 is electrically connected to passive face 110b of chip 110. The conductive member 158 may be, for example, a bump. Conductive feature 158 may be bonded to contact 119 on passive side 110b of chip 110 by solder 162. The contact 119 may be, for example, a pad. The insulating layer 152 and conductive traces 154 (i.e., body portion) of the circuit structure 150 may be spaced apart from the passive face 110b of the chip 110 at least by conductive features 158. In fig. 2, the insulating layer 152 and the conductive traces 154 of the circuit structure 150 are specifically spaced from the passive side 110b of the chip 110 by solder 162 and contacts 119. The conductive member 159 is bonded to the contact 139 (e.g., a pad) on the substrate 130 by solder 164.

The chip 110 may include a plurality of functional areas 112. In some embodiments, each functional region 112 may be a die (die). The inactive face of each functional region 112 collectively constitutes the inactive face 110b of the chip 110. The plurality of functional areas 112 are encapsulated by molding compound 160. The electronic device 100 further comprises a voltage regulator 172 connected to the circuit structure 150. The voltage regulator 172 may be disposed adjacent to the conductive member 158. The voltage regulator 172 may be used to regulate power and provide the regulated power to the passive side 110b of the chip 110. A voltage regulator 172 may also be disposed on a surface of the substrate 130 to regulate power from the substrate 130, and the regulated power is then transferred to the chip 110 via the circuit structure 150. In some embodiments, the electronic device 100 may further include a passive element 174 connected to the circuit structure 150, and the passive element 174 disposed on the substrate 130, where the passive element 174 may be used as a filtering/voltage stabilizing circuit. In some embodiments, the passive element 174 may be an electronic component such as an inductor or a capacitor.

A protective glue layer 220 may be formed between the second portion surface 122b of the heat spreader 120 and the upper surface of the molding compound 160 and the passive surface 110b of the chip 110 to encapsulate the conductive features 158, solder 162, and contacts 119. The voltage regulator 172 and the passive component 174 connected to the circuit structure 150 are also covered by a protective glue layer 220. A protective glue layer 220 may also be provided between the first partial surface 122a and the substrate 130 to encapsulate the conductive features 159, the solder 164 and the contacts 139.

In the embodiment shown in fig. 2, the active surface 110f of the chip 110 is electrically connected to the first wiring layer 231 under the chip 110. The first wiring layer 231 is electrically connected to the second wiring layer 232 under the first wiring layer 231. The through hole 235 connects the first wiring layer 231 and the second wiring layer 232. The second wiring layer 232 is electrically connected to the underlying substrate 130. An electronic component 281 and a bridge device 282 may be disposed between the first circuit layer 231 and the second circuit layer 232, the electronic component 281 may be connected to the first circuit layer 231 and/or the second circuit layer 232, and the bridge device 282 may be connected to the first circuit layer 281. In some embodiments, the bridge device 282 may be used to bridge the plurality of functional areas 112 of the chip 110.

The space between the chip 110 and the first line layer 231 is filled with an underfill 291, and the underfill 291 may also cover the lower portion of the chip 110. The chip 110 and the underfill 291 are encapsulated by the molding compound 160, and the molding compound 160 is further filled between the first wiring layer 231 and the second wiring layer 232 to encapsulate the through-holes 235, the electronic components 281, and the bridge device 282. The space between the second circuit layer 232 and the substrate 130 is filled with an underfill 292, and the underfill 292 may further encapsulate the sidewalls of the first circuit layer 231, the second circuit layer 232, and the molding compound 160 therebetween. It should be understood that the structure shown in fig. 2 for bonding the chip 110 to the substrate 130 is merely an example, and in other embodiments, the chip 110 may be packaged on the substrate 130 in any suitable manner, which is not limited in this application.

A method of forming the electronic device 100 shown in fig. 2 is described below with reference to fig. 3A to 6B.

As shown with reference to fig. 3A and 3B, a substrate 130 is provided. As described above with reference to fig. 2, the chip 110 is bonded on the substrate 130 through the first wiring layer 231, the second wiring layer 232, and the through-holes 235, and the chip 110 is encapsulated by the molding compound 160. On the substrate 130, a voltage regulator 172 and a passive element 174 are disposed adjacent to each functional region 112, respectively. Wherein the underfill 292 of fig. 3A is not shown in fig. 3B and subsequent fig. 4B, 5B, and 6B for clarity of illustration.

As shown in fig. 3B, the chip 110 may include an array of 4 functional areas 112,4 functional areas 112 arranged in 2 rows and 2 columns. The 4 voltage regulators 172 are correspondingly disposed adjacent to the 4 functional areas 112. A corresponding passive element 174 is provided alongside each voltage regulator 172. In some embodiments, the passive element 174 may also be omitted. It should be understood that the number and layout of functional areas 112 shown in FIG. 3B is merely an example, and that in other embodiments, other numbers of functional areas 112 may be provided and other applicable layouts may be employed.

Each functional area 112 has two outer edges. Taking the functional area 112 at the upper right corner in fig. 3B as an example, the functional area 112 has outer edges e1, e2. The contacts 119 on the functional area 112 comprise a first set of power contacts 119P for connecting power and a first set of ground contacts 119G for grounding, the first set of power contacts 119P and the first set of ground contacts 119G being arranged adjacent to the respective two outer edges e1, e2 of the functional area 112. Along an outer edge e3 of the substrate 130 closest to the outer edge e1, a second set of power contacts 139P is provided, corresponding to the first set of power contacts 119P. The first set of power contacts 119P may be connected to a second set of power contacts 139P on the substrate 130 in a subsequent process. Along an outer edge e4 of the substrate 130 closest to the outer edge e2, a second set of ground contacts 139G is provided, corresponding to the first set of ground contacts 119G. The first ground contact 119G may be connected to a second ground contact 139G on the substrate 130 in a subsequent process.

Referring to fig. 4A and 4B, a patterned protective glue layer 220 is formed to individually encase each of the first set of power contacts 119P, the first set of ground contacts 119G, the second set of power contacts 139P, and the second set of ground contacts 139G. In some embodiments, the material of protective paste layer 220 may be non-conductive paste (NCP, non Conductive Paste), or Epoxy-flux (Epoxy-flux).

Referring to fig. 5A and 5B, a heat conductive layer 260 is laid on an intermediate region of the chip 110 where the contact 119 is not provided. In some embodiments, the material of the thermally conductive layer 260 is a thermally conductive paste, such as TIM (Thermal Interface Material, thermally conductive interface material).

Referring to fig. 6A and 6B, a heat sink 120 is provided, and a circuit structure 150 is provided at a lower surface 122 of the heat sink 120. A thermal compression bonding (TCB, thermal Compression Bonding) process is employed such that the conductive features 159 of the circuit structure 150 are bonded to the contacts 139 on the substrate 130 by solder 164 and the conductive features 158 are bonded to the contacts 119 on the passive side 110b of the chip 110 by solder 162. The protective adhesive layer 220 may help the bonding of each contact 139, 119 with the corresponding conductive member 159, 158 during the thermocompression bonding process, and may also protect the contact from open or short circuit after bonding. Thus, the electronic device 100 is obtained.

In the top view of the electronic device 100 shown in fig. 6B, the contacts 119 of the chip 110 are located in the peripheral region. The heat conductive layer 260 is located in the middle region, and may connect the chip 110 with the heat sink 120 to dissipate heat from the chip 110. The circuit structure 150 (see fig. 6A) bonds the contacts 119 of the chip 110 with the corresponding contacts 139 on the substrate 130. The power contacts (e.g., first set of power contacts 119P) and the ground contacts (e.g., first set of ground contacts 119G) are disposed adjacent different outer edges e1, e2 of the corresponding functional area 112. Specifically, a first set of power contacts 119P on the functional region 112 disposed adjacent to the outer edge e1 is connected to a corresponding second set of power contacts 139P on the substrate 130 via a circuit structure 150 (see fig. 6A), and a first set of ground contacts 119G disposed adjacent to the other outer edge e2 is connected to a corresponding second set of ground contacts 139G on the substrate 130.

Fig. 7A is a schematic cross-sectional view of a heat sink 120 according to some embodiments, wherein a lower surface 122 of the heat sink 120 is disposed upward. Referring to fig. 7A, the circuit structure 150 is conformally disposed at the lower surface 122 of the heat sink 120, i.e., the circuit structure 150 is in continuous physical contact with the lower surface 122 along the lower surface 122 of the heat sink 120. The circuit structure 150 specifically includes an insulating layer 152 in physical contact with the heat spreader 120, and a conductive trace 154 disposed in the insulating layer 152. The conductive trace 154 may electrically connect the conductive feature 158 with the conductive feature 159. Conductive member 158 and conductive member 159 are connected to solder 162 and solder 164, respectively. The voltage regulator 172 is connected to the circuit structure 150. In the present embodiment, the passive element 174 described with reference to fig. 2 is omitted.

Fig. 7B is a plan view of the heat sink 120 and the circuit structure 150 in fig. 7A. Referring to fig. 7B, an insulating layer 152 is laid on a partial region of the lower surface 122 of the heat spreader 120, and conductive traces 154 are disposed in the insulating layer 152, so that the circuit structure 150 has a plurality of patterned regions PS1. The patterned region PS1 may be connected to the corresponding functional region 112 (see, e.g., fig. 2) by the conductive member 158 and the solder 162, and to the substrate 130 (see, e.g., fig. 2) by the conductive member 159 and the solder 164. The layout of the conductive features 158, 159 shown in fig. 7B is merely an example, and in other embodiments, the conductive features 158, 159 may take other suitable layouts to engage the corresponding functional areas 112.

The patterned region PS1 extends inwardly from the corresponding edge of the heat sink 120 to above the corresponding functional region 112 (see fig. 2). In top view, the insulating layer 152 of the circuit structure 150 may cover a peripheral region of the heat spreader 120 (corresponding to the first partial surface 122a shown in fig. 7A). For the insulating layer 152 at the peripheral region, an adhesive layer 270 may be provided at a position where the conductive member 159 is not provided, to be attached with a substrate (see the substrate 130 in fig. 2). A portion of the lower surface 122 of the heat spreader 120 is exposed from the circuit structure 150 without the insulating layer 152. The heat conductive layer 260 is disposed in an intermediate region of the heat sink 120 where the circuit structure 150 is not disposed, so as to connect the heat sink 120 to the passive surface 110b of the chip 110 (see fig. 2).

With continued reference to fig. 2, in the electronic device 100, an insulating layer 152 is laid on the lower surface 122 of the heat spreader 120, and a conductive trace 154 is formed in the insulating layer 152, so as to direct electric power directly above the corresponding functional region 112; the heat spreader 120 is electrically connected to the conductive member 159 and the solder 164 at the connection between the chip 110 and the substrate 130; the chip 110 includes a plurality of functional areas 112 arranged laterally, and the circuit structure 150 for power transmission can be designed by the edge of the heat sink 120 closest to the functional areas 112; the voltage regulator 172 may be connected to the circuit structure 150 and disposed near the chip 110, so as to reduce the distance between the voltage regulator 172 and the chip 110 and increase the voltage and current controllability. The present application provides a structural design that can be used in existing assembly operations to achieve power and signal splitting for the multifunction portion 112. Further, by providing the protective adhesive layer 220, the bonding of each contact 119, 139 with the corresponding conductive member 158, 159 can be facilitated, and the bonding of each contact 119, 139 with the corresponding conductive member 158, 159 can be protected.

Fig. 8A is a schematic cross-sectional view of an electronic device 200 according to another embodiment of the present application. Referring to fig. 8A, the electronic device 200 includes a chip 110, a heat spreader 120, and a flexible circuit structure 850. In some embodiments, the flexible circuit structure 850 may be a flexible circuit board. The flexible circuit structure 850 is disposed between the chip 110 and the heat sink 120, and is used to provide power to the chip 110 through the passive surface 110b of the chip 110. The power reaches the passive surface 110b of the chip 110 from the substrate 130 via the flexible circuit structure 850.

By providing the flexible circuit structure 850 between the chip 110 and the heat sink 120 to provide power to the passive side 110b of the chip 110, an effective power path to the passive side 110b of the chip 110 is provided, signal and power splitting is achieved, and complexity and difficulty of substrate design are reduced. In addition, the flexible circuit structure 850 can reduce the difficulty of circuit layout.

Referring to fig. 8B, the flexible circuit structure 850 may be first formed and then the flexible circuit structure 850 may be attached to the heat sink 120. Since the flexible circuit structure 850 is flexible, the flexible circuit structure 850 may bend during the process of connecting the flexible circuit structure 850 to the heat sink 120. This results in a gap 842 between the flexible circuit structure 850 and the heat spreader 120 in the electronic device 200, as shown in fig. 8A. The gap 842 is located at the bend of the heat sink 120, i.e. where the second part surface 122b meets the third part surface 122c.

With continued reference to fig. 8A, the flexible circuit structure 850 may be connected to the heat spreader 120 through the adhesive layer 870. The adhesive layer 870 may cover the second partial surface 122b of the heat sink 120. The adhesive layer 870 may also cover the first portion surface 122a of the heat sink 120.

The flexible circuit structure 850 may include an insulating layer 852 and conductive traces 854 disposed in the insulating layer 852. The insulating layer 852 and the conductive traces 854 therein may be referred to as a body portion of the flexible circuit structure 850. Flexible circuit structure 850 also includes conductive features 858 and 859 (e.g., bumps) that electrically connect conductive traces 854. Solder 862 bonds conductive feature 858 to contact 119 on passive face 110b of chip 110. The insulating layer 852 and conductive traces 854 (i.e., the body portion) of flexible circuit structure 850 may be separated from the passive side 110b of chip 110 by conductive feature 858, solder 862, and contact 119. The conductive member 859 is bonded to the contact 139 (e.g., a pad) on the substrate 130 by solder 864.

The substrate 130 may have a voltage regulator 172 and a passive component 174 disposed thereon, the voltage regulator 172 and passive component 174 being similar to that described above with reference to fig. 2. In some embodiments, voltage regulators and passive components (not shown) may also be connected near the conductive features 858 of the flexible circuit structure 850.

Fig. 8C is a schematic top view of the electronic device 200 of fig. 8A, wherein the heat spreader 120 and the flexible circuit structure 850 are not shown in the top view for clarity of illustration. Referring to fig. 8C, the chip 110 includes 4 functional areas 112 arranged in 2 rows and 2 columns.

Each functional area 112 has two outer edges. Taking the functional area 112 at the upper right corner in fig. 8C as an example, the functional area 112 has outer edges e1, e2, the contacts 119 on the functional area 112 comprise a first set of power contacts 119P for connecting power and a first set of ground contacts 119G for grounding, the first set of power contacts 119P and the first set of ground contacts 119G being arranged adjacent to the two outer edges e1, e2 of the corresponding functional area 112, respectively. The first set of power contacts 119P may be used to connect to a second set of power contacts 139P on the substrate 130 and the first set of ground contacts 119G may be used to connect to a second set of ground contacts 139G on the substrate 130. The second set of power contacts 139P and the second set of ground contacts 139G are disposed adjacent different edges e3, e4 of the substrate 130, respectively.

Fig. 8D is a plan view of the heat spreader 120 and the flexible circuit structure 850 of fig. 8A. Referring to fig. 8D, the flexible circuit structure 850 has a plurality of patterned areas PS2 corresponding to the plurality of functional areas 112 (see fig. 8C), the conductive member 858 and the solder 862 in each patterned area PS2 are bonded to the corresponding functional area 112 of the chip 110 (see fig. 8C), and the conductive member 859 and the solder 864 are bonded to the substrate 130 (see fig. 8A).

Each patterned region PS2 extends inwardly from one edge of the heat sink 120 to above the functional region 112 adjacent to the edge (see fig. 8A). Since the flexible circuit structure 850 has the patterned region PS2, a portion of the lower surface 122 of the heat spreader 120 can be exposed from the flexible circuit structure 850. Wherein, the portion of the first partial surface 122a exposed from the flexible circuit structure 850 may be provided with an adhesive layer (not shown) to be attached to the substrate 130 (see fig. 8A).

Although not shown in fig. 8D, a heat conductive layer may be provided at an intermediate region of the second partial surface 122b of the heat sink 120 where the flexible circuit structure 850 is not provided. Further, one or more of the patterned areas PS2 may have the voltage regulator 172 described above with reference to fig. 2 disposed therein. Other aspects of the electronic device 200 shown in fig. 8A may be similar to the electronic device 100 shown in fig. 2, and the description will not be repeated here in order to avoid repetition.

Fig. 9A is a schematic cross-sectional view of an electronic device 300 according to another embodiment. Referring to fig. 9A, the substrate 130 and the heat sink 120 are electrically connected to each other through the first clamping member 910. The first clamping member 910 has a first recess 912. A portion of the heat sink 120 is disposed within the first recess 912. A portion of the flexible circuit structure 850 is also disposed in the first recess 912. In this embodiment, the lower portion of the supporting portion 120b of the heat dissipation element 120, the corresponding adhesive layer 870 and a portion of the flexible circuit structure 850 are disposed in the first recess 912. The insulating layer 852 of the flexible circuit structure 850 extends to a surface of the supporting portion 120b facing away from the chip 110, so as to isolate the first clamping member 910 from the heat sink 120 through the insulating layer 852.

Fig. 9B is a perspective view of a first clamp member 910 according to some embodiments. Referring to fig. 9B, the first clamping member 910 may include a bottom wall 902, and side walls 904 connected to opposite sides of the bottom wall 902. The bottom wall 902 and the side wall 904 define a first recess 912. The sidewall 904 may have a curved surface protruding into the first recess 912 to clamp and clamp the flexible circuit structure 850 (see fig. 9A) into the first recess 912. It should be understood that the structure of the first clamping member 910 is schematically shown in fig. 9A, and in practice, the first clamping member 910 may have the structure shown in fig. 9B.

Fig. 9C is a side view of the region S1 in fig. 9A along the direction D1. Referring to fig. 9A and 9C, one end of the conductive trace 854 of the flexible circuit structure 850 has a contact 919 for bonding with the substrate 130. The contacts 919 may be exposed by the insulating layer 852. After the support 120b is placed in the first recess 912, at least a lower portion of the contact 919 is positioned within the first recess 912 and in contact and electrical connection with the first clamping member 910. The first clamping member 910 may be connected to the contact 139 on the substrate 130 by an underlying solder 864. An adhesive layer 270 may be provided between the support 120b and the substrate 130 at a position where the first clamping member 910 is not provided.

Referring again to fig. 9A, the electronic device 300 may further include a second clamping member 920, where the second clamping member 920 electrically connects the passive surface 110b of the chip 110 with the flexible circuit structure 850. The second clamping member 920 may be similar in structure to the first clamping portion 910. Fig. 9D is a partially enlarged schematic view at a region S2 in fig. 9A. Referring to fig. 9D, the second clamping member 920 has a second recess 922. The second clamping member 920 may be similar in structure to the first clamping member 910 described above. The conductive member 858 of the flexible circuit structure 850 is disposed in the second recess 922 and is in contact with and electrically connected to the second clamping member 920. In this embodiment, the conductive member 858 may be a metal post that is received in the second recess 922 of the second clamping member 920. The second clamping member 920 may electrically connect the conductive member 858 to the contact 119 on the passive face 110b by solder 862.

In some embodiments, the bonding process of the heat spreader 120 and the substrate 130 includes: the SMT (Surface Mounted Technology, surface mount technology) process is performed to bond the first clamping member 910 and the second clamping member 920 on the contact 139 of the substrate 130 and the contact 119 of the chip 110 through the solders 864, 862, and then provide the heat spreader 120 and the flexible circuit structure 850 connected together, so as to clamp the conductive members 858, 859 of the flexible circuit structure 850 in the first recess 912 and the second recess 922 of the first clamping member 910 and the second clamping member 920, respectively. By employing the first clamping member 910 and/or the second clamping member 920 for bonding, the bonding reliability is better than that of, for example, the solder bonding method shown in fig. 2, because such clamping members are less prone to problems such as disconnection; in addition, the TCB process (as described with reference to fig. 6A and 6B) for bonding the circuit structure 150 and the substrate 130 may be omitted, and the conductive members 858 and 859 may be clamped in the first recess 912 and the second recess 922, so that the process is easier.

Fig. 10 is a schematic cross-sectional view of an electronic device 400 according to another embodiment of the present application. Referring to fig. 10, a circuit structure 150' is disposed between the chip 110 and the heat sink 120. The circuit structure 150' is similar to the circuit structure 150 described above with reference to fig. 2.

The substrate 130 and the heat sink 120 are electrically connected to each other through the first clamping member 910 in a similar manner to the above description with reference to fig. 9A and 9C, and the description thereof will not be repeated. The insulating layer 152 of the circuit structure 150' also extends onto the surface of the supporting portion 120b facing away from the chip 110, so as to isolate the first clamping member 910 from the heat sink 120 by the insulating layer 152. The lower portion of the supporting portion 120b of the heat dissipation element 120 and the corresponding part of the circuit structure 150' are disposed in the first recess 912. The first clamping member 910 may electrically connect the circuit structure 150' to the contact 139 on the substrate 130 by the underlying solder 164.

The electronic device 400 may further comprise a second clamping member 920 electrically connecting the passive face 110b of the chip 110 with the circuit structure 150'. Specifically, the second clamping member 920 has a second recess 922. The conductive member 158 of the circuit structure 150' is disposed within the second recess 922. The second clamping member 920 may be connected to the contact 119 on the passive side 110b of the chip 110 by the underlying solder 162 to electrically connect the conductive member 158 to the contact 119 on the passive side 110b.

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims (10)

1. An electronic device, comprising:

a chip;

a heat sink; and

the flexible circuit structure is arranged between the chip and the heat dissipation piece and is used for providing power for the chip through the passive surface of the chip.

2. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

the flexible circuit structure is connected to the heat dissipation member through the adhesive layer.

3. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

a gap is formed between the flexible circuit structure and the heat dissipation member.

4. The electronic device of claim 3, wherein the electronic device comprises a plurality of electronic components,

the gap is positioned at the bending part of the heat dissipation piece.

5. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

the chip comprises a plurality of functional areas, and the flexible circuit structure is provided with a plurality of patterning areas corresponding to the functional areas.

6. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

the heat dissipation member has a lower surface facing the chip, and a portion of the lower surface of the heat dissipation member is exposed from the flexible circuit structure.

7. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

the flexible circuit structure comprises a main body part connected with the heat dissipation piece and a conductive component used for electrically connecting the main body part to the chip, wherein the main body part is separated from the chip through the conductive component.

8. The electronic device of claim 1, further comprising:

the substrate carries the heat dissipation piece and the chip; and

the first clamping component is electrically connected with the substrate and the heat dissipation piece, wherein the first clamping component is provided with a first concave part, and a part of the heat dissipation piece is arranged in the first concave part.

9. The electronic device of claim 8, further comprising:

the second clamping component is electrically connected with the chip and the flexible circuit structure, wherein the second clamping component is provided with a second concave part, and a part of the flexible circuit structure is arranged in the second concave part.

10. The electronic device of claim 9, wherein the electronic device comprises a plurality of electronic components,

the main body part of the flexible circuit structure is separated from the chip through a conductive part and is electrically connected with the chip through the conductive part, and the conductive part comprises a metal column accommodated in the second clamping part.