CN220526328U

CN220526328U - Chip system and mobile robot

Info

Publication number: CN220526328U
Application number: CN202320603524.4U
Authority: CN
Inventors: 赖钦伟
Original assignee: Zhuhai Amicro Semiconductor Co Ltd
Current assignee: Zhuhai Amicro Semiconductor Co Ltd
Priority date: 2023-03-24
Filing date: 2023-03-24
Publication date: 2024-02-23
Anticipated expiration: 2033-03-24

Abstract

The utility model discloses a chip system and a mobile robot, wherein the chip system comprises a CPU unit, a bus unit, an address remapping unit, a nonvolatile memory and a volatile memory; the CPU unit decides whether to run codes with the nonvolatile memory or the volatile memory according to whether the chip system is in the first working state or the second working state; the volatile memory is used for carrying codes from the nonvolatile memory to run when the chip system is in a first working state; the nonvolatile memory is used for directly running codes according to the target clock to realize low power consumption when the chip system is in the second working state. The chip system stores and operates codes through two different memories, and switches the operation storage mode through address remapping, so as to solve the problem of executing switching of codes under different working states.

Description

Chip system and mobile robot

Technical Field

The utility model relates to the technical field of chips, in particular to a chip system and a mobile robot.

Background

For an SOC Chip (System on Chip), different operation states are set according to the working requirements, and at least two states are included in the different operation states: an operating state and a standby state. When the SOC chip is in an operating state, various modules are opened, and the frequency of a system clock meets the requirement of normal operation of the SOC chip; when the SOC chip is in a standby state, unnecessary modules are closed, the frequency of a system clock is reduced, and the voltage is reduced, so that the overall power consumption of the SOC chip at the moment is far smaller than that in an operating state, and the effect of saving energy consumption is achieved. Entering a low power standby state is relatively simple for a single memory, e.g. an MCU system. However, in the case of a relatively complex SOC system, particularly an SOC system with such volatile memory as the external memory DDR, it is difficult to realize the SOC system because if the DDR memory is not turned off in a low power standby state, the power consumption is not low, and the energy consumption cannot be effectively saved. Most programs of the SOC chip are in the DDR memory, and if the DDR memory is closed, the operation of most programs is affected; if a daemon is specially made, the daemon runs in a relatively small SRAM memory inside the SOC chip. In this way, two codes need to be maintained, one is the code operated by the DDR memory when the SOC chip works normally, and the other is the code operated by the SRAM memory in the SOC chip when the SOC chip sleeps, so that development complexity is increased.

Disclosure of Invention

In order to solve the problems, the utility model provides a chip system and a mobile robot. The specific technical scheme of the utility model is as follows:

a chip system, the chip system comprising: the CPU unit is used for determining whether to run codes by the nonvolatile memory or the volatile memory according to whether the chip system is in the first working state or the second working state; the volatile memory is used for carrying codes from the nonvolatile memory to run when the chip system is in the first working state; a nonvolatile memory for storing the operation code and operating the code according to the target clock when the chip system is in the second working state; an address remapping unit, configured to switch the running code of the memory in the system-on-chip, and reset the address of the running code; the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the target clock is a system clock of the chip system in standby or dormancy. The chip system stores and operates codes through two different memories, and switches the operation storage mode through address remapping so as to solve the problem of code execution switching under different working states; the chip system utilizes the characteristic that the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code under the target clock, and reduces the power consumption of the chip system in the second working state by adopting the nonvolatile memory operation code under the target clock state, and the same operation code can realize the switching and operation of different working states.

Further, the chip system further comprises a bus unit, wherein the CPU unit is connected with the address remapping unit and the external device through the bus unit, and the bus unit is used for transmitting an electric signal of the external device to the CPU unit or transmitting an electric signal of the CPU unit to the address remapping unit. The CPU unit can receive and transmit information through the bus unit, has a simple structure and effectively reduces the area of the chip system.

Further, when the chip system is switched from the first working state to the second working state, the CPU unit sends enabling signals to the address remapping unit through the bus unit, the address remapping unit closes the volatile memory after receiving the enabling signals, enables the nonvolatile memory, maps the code initial running address of the nonvolatile memory to the storage initial address of the code stored in the nonvolatile memory, then reduces the frequency of a clock of the system, and enables the nonvolatile memory to run the code according to the system clock after the frequency is reduced to realize low power consumption. The running codes are stored in the nonvolatile memory, so that the running codes cannot be lost after the nonvolatile memory is powered down, and the switching of the code addresses is performed in an address mapping mode, so that the switching of the memory can be realized only by one part of the running codes, and the development and maintenance difficulty of the running codes is reduced. And in the second working state, the codes are operated through the nonvolatile memory with lower power consumption, so that the operation power consumption of the chip system in the second working state is reduced.

Further, when the chip system is switched from the second working state to the first working state, the CPU unit sends enabling signals to the address remapping unit through the bus unit, the address remapping unit starts the volatile memory after receiving the enabling signals, and the initial code running address of the volatile memory is mapped to the initial storage address of the code stored in the nonvolatile memory, so that the volatile memory carries the code from the nonvolatile memory to run when the chip system is in the first working state. During normal operation, the volatile memory is used for carrying codes from the nonvolatile memory to operate, so that the response speed of the chip system during the secondary operation after the chip system is interrupted is improved.

A mobile robot comprising the chip system described above. The chip system of the mobile robot stores and operates codes through two different memories, and solves the problem of code execution switching under different working states by switching operation storage modes through address remapping; by utilizing the characteristic that the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code under the target clock, the power consumption of the chip system in the second working state is reduced by adopting the nonvolatile memory operation code under the target clock state, and different working state switching and operation can be realized by one identical operation code. And in the second working state, the codes are operated through the nonvolatile memory with lower power consumption, so that the operation power consumption of the chip system in the second working state is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a chip system according to an embodiment of the utility model.

Fig. 2 is a schematic diagram of an operation flow of the chip system according to an embodiment of the utility model.

Description of the embodiments

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

As used in this application, the term "if" may be interpreted as "when …" or "upon" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

For an SOC Chip (System on Chip), different operation states are set according to the working requirements, and at least two states are included in the different operation states: an operating state and a standby state. When the SOC chip is in an operating state, various modules are opened, and the frequency of a system clock meets the requirement of normal operation of the SOC chip; when the SOC chip is in a standby state, unnecessary modules are closed, the frequency of a system clock is reduced, and the voltage is reduced, so that the overall power consumption of the SOC chip at the moment is far smaller than that in an operating state, and the effect of saving energy consumption is achieved. The first working state is a normal running state of the chip system, the second working state is a standby state or a dormant state of the chip system, the target clock is a system clock of the chip system in standby or dormant state, specific values of frequencies of the system clocks of the chip system in the first working state and the second working state are determined by working frequencies of the CPU units in the first working state and the second working state, various modules work in the first working state, the working frequencies of the CPU units are higher, the frequencies of the system clocks are also higher, unnecessary modules are closed in the second working state, the working frequencies of the CPU units are lower, and the frequencies of the system clocks are also lower.

As shown in fig. 1, a chip system includes a CPU unit (i.e., a CPU in the figure), a bus unit (i.e., a bus in the figure), an address remapping unit, a nonvolatile memory, and a volatile memory, i.e., the nonvolatile memory is a memory 1 in the figure, the volatile memory is a memory 2 in the figure, the CPU unit is connected with the address remapping unit through the bus unit, the CPU unit is connected with an external device through the bus unit, and the external device may be an electronic device using an intelligent chip such as a computer, a mobile phone, a mobile robot, or the like; the address remapping unit is respectively connected with the nonvolatile memory and the volatile memory; the CPU unit decides whether to run codes with the nonvolatile memory or the volatile memory according to whether the chip system is in the first working state or the second working state; the volatile memory is used for carrying codes from the nonvolatile memory to run when the chip system is in a first working state; the nonvolatile memory is used for directly running codes according to a target clock to realize low power consumption when the chip system is in a second working state; the bus unit is used for transmitting the electric signal of the external device to the CPU unit or transmitting the electric signal of the CPU unit to the address remapping unit; the memory is regarded as a black box with an output and an input port, the input quantity is an address, and the output is data stored on the corresponding address; the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the target clock is a system clock of the chip system in standby or dormancy. The chip system stores and operates codes through two different memories, and switches the operation storage mode through address remapping so as to solve the problem of code execution switching under different working states; the chip system utilizes the characteristic that the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code under the target clock, and reduces the power consumption of the chip system in the second working state by adopting the nonvolatile memory operation code under the target clock state, and the same operation code can realize the switching and operation of different working states.

As one embodiment, the chip system further includes a bus unit, where the CPU unit is connected to the address remapping unit and the external device through the bus unit, and the bus unit is configured to transmit an electrical signal of the external device to the CPU unit or transmit an electrical signal of the CPU unit to the address remapping unit. The CPU unit can receive and transmit information through the bus unit, has a simple structure and effectively reduces the area of the chip system. After the CPU unit determines that the chip system is switched in working state, the CPU unit can send a corresponding enabling signal to the memory through the bus unit to enable the corresponding memory. The CPU unit can receive and transmit information through the bus unit, has a simple structure and effectively reduces the area of the chip system.

As one embodiment, when the chip system is switched from the first working state to the second working state, the CPU unit sends enabling to the address remapping unit through the bus unit, the address remapping unit closes the volatile memory after receiving the enabling signal, enables the nonvolatile memory, maps the code initial operation address of the nonvolatile memory to the storage initial address of the operation code stored in the nonvolatile memory, and then reduces the frequency of the clock of the system, so that the nonvolatile memory realizes low power consumption according to the system clock operation code after the frequency reduction. The running codes are stored in the nonvolatile memory, so that the running codes cannot be lost after the nonvolatile memory is powered down, and the switching of the code addresses is performed in an address mapping mode, so that the switching of the memory can be realized only by one part of the running codes, and the development and maintenance difficulty of the running codes is reduced.

As one embodiment, when the chip system is switched from the second working state to the first working state, the CPU unit sends an enabling signal to the address remapping unit through the bus unit, and after receiving the enabling signal, the address remapping unit enables the volatile memory, maps the code initial operation address of the volatile memory to the storage initial address of the code stored in the nonvolatile memory, so that the volatile memory carries the code from the nonvolatile memory to operate when the chip system is in the first working state. During normal operation, the volatile memory is used for carrying codes from the nonvolatile memory to operate, so that the response speed of the chip system during the secondary operation after the chip system is interrupted is improved.

The Memory (Memory) is one of the most important functional units of the single-chip microcomputer, and is a set of a plurality of Memory units, and the Memory (Memory) does not have address information, so to accurately find the Memory unit storing certain information, the CPU (for example, ARM Cortex-M4 kernel) must assign a mutually-distinguished identifier to the Memory unit, and the identifier is what we refer to as address code. For example, in an STM32 Microcontroller (MCU) STM32F407, a plurality of types of Memory are integrated, the same type of Memory is a Memory Block (Block 0 to Block 7), and each Memory is assigned a natural number set represented by 16-system, which has continuous number values and equal number of Memory cells, as an address code of the Memory Block. The correspondence between the natural number set and the Memory Block is a Memory Map, which is sometimes called Address Map. During normal operation, the volatile memory is used for carrying codes from the nonvolatile memory to operate, so that the response speed of the chip system during the secondary operation after the chip system is interrupted is improved. In the second working state, in order to reduce the power consumption of the chip system, the volatile memory is closed, codes and data stored in the volatile memory are lost, in order to improve the response speed of the chip system, the codes are required to be operated through the volatile memory in the first working state of the chip system, so that when the chip system enters the first working state from the second working state, a mapping relation is established between the code storage address of the nonvolatile memory and the code storage address of the volatile memory, the initial address of the operating code of the volatile memory is corresponding to the initial address of the operating code stored in the nonvolatile memory, when the chip system normally works, the chip system accesses the initial address of the operating code of the volatile memory, in fact, the codes in the nonvolatile memory are called by the memory through the storage address corresponding to the codes under the normal working of the chip system, and the purpose of carrying corresponding code operation is achieved. The nonvolatile memory is powered down and cannot lose data, so that the running codes are stored in the nonvolatile memory, when the chip system enters the second working state from the first working state, the chip system closes the volatile memory, reduces a system clock, then enables a code initial running address of the nonvolatile memory to establish a mapping relation with a storage initial address of the running codes stored in the nonvolatile memory, then starts to run from the code initial running address of the nonvolatile memory, and the nonvolatile memory does not need to carry codes from the volatile memory to run.

As one embodiment, the nonvolatile memory is a Flash memory. Nonvolatile memory (NVM) refers to computer memory in which stored data does not disappear after power is turned off. In the nonvolatile memory, whether the data in the dependent memory can be rewritten into a standard at any time when the computer is used can be classified into two main products, namely ROM and Flash memory. Flash memory (english) is a form of electronically erasable programmable read-only memory that allows for multiple erasures or writes in operation. This technology is mainly used for general data storage and data exchange and transmission between computers and other digital products, such as memory cards and U disks.

As one of the embodiments, the volatile memory is a DDR memory or an SRAM memory. RAM (Random Access Memory) is known as a random access memory, which corresponds to a removable memory on a PC for storing and maintaining data. It can be read from and written to at any time, and RAM is typically used as the temporary storage medium (which may be referred to as system memory) for the operating system or other running programs. However, RAM cannot retain data when power is turned off, and if it is required to store data, they must be written to a long-term memory (e.g., hard disk). Because of this, the RAM is sometimes also referred to as "variable memory". RAM memory can be further divided into two major categories, static RAM (SRAM) and dynamic memory (DRAM). DRAM is largely employed as a main memory of a system because of its low price per unit capacity. Ddr=double Data Rate Double Rate, DDR sdram=double Rate synchronous dynamic random access memory, commonly referred to as DDR, where SDRAM is an abbreviation for Synchronous Dynamic Random Access Memory, synchronous dynamic random access memory. While DDR SDRAM is an abbreviation for Double Data Rate SDRAM, which is meant for double rate synchronous dynamic random access memory. DDR memory is developed on the basis of SDRAM memory, and SDRAM production system is still used, so that for memory manufacturers, DDR memory production can be realized by only slightly improving equipment for manufacturing common SDRAM, and cost can be effectively reduced.

A method of operating a chip system for operating the chip system described above, the method comprising the steps of: after receiving the working state instruction through the bus unit, the CPU judges whether the chip system performs working state switching or not; if the chip system is switched in working state, the CPU unit resets the address of the running code through the address remapping unit; if the chip system is switched to a first working state, the volatile memory carries codes from the nonvolatile memory to operate; if the chip system is switched to the second working state, the nonvolatile memory directly operates codes according to a target clock; the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the target clock is a system clock of the chip system in standby or dormancy. The chip system stores and operates codes through two different memories, and switches the operation storage mode through address remapping so as to solve the problem of code execution switching under different working states; by utilizing the characteristic that the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code under the target clock, the power consumption of the chip system in the second working state is reduced by adopting the nonvolatile memory operation code under the target clock state, and different working state switching and operation can be realized by one identical operation code.

As one embodiment, after the CPU unit receives the operation state instruction through the bus unit, it is determined whether the chip system performs operation state switching, including the following steps: after the chip system receives the working state instruction through the bus unit, judging whether the working state instruction is a first working state operation instruction or a second working state operation instruction; the chip system judges whether the chip system needs to switch the working state according to the current working state and the working state instruction; if the chip system is in the first working state at present, the chip system is switched to the second working state after receiving the second working state operation instruction; if the chip system is in the second working state at present, the chip system is switched to the first working state after receiving the operation instruction of the first working state. The chip system determines whether the working state of the chip system needs to be switched according to the working state instruction, so that the chip system can quickly enter different working states, and the practicability is higher. After receiving a first working state operation instruction through a bus unit, the CPU unit judges the current working state of the chip system; if the CPU unit judges that the chip system is in the first working state currently, the chip system does not switch the working state, so that the CPU unit continues to run codes through the volatile memory; if the CPU unit judges that the chip system is in the second working state currently, the chip system is switched to the first working state, the CPU unit wakes up the chip system, and then the volatile memory carries codes from the nonvolatile memory to operate after the chip system enters the first working state. After receiving the second working state operation instruction through the bus unit, the CPU unit judges the current working state of the chip system; if the CPU unit judges that the chip system is in the first working state currently, the chip system is switched to the second working state, the CPU unit configures an address remapping unit to enable the address remapping unit to reestablish a mapping relation between an operation address of a code and a storage address of the code, the frequency of a system clock is reduced, a volatile memory is closed, and the nonvolatile memory directly operates the code according to a target clock; if the CPU unit judges that the chip system is in the second working state currently, the chip system does not switch the working state, so that the CPU unit can directly run codes according to the target clock through the nonvolatile memory to realize low power consumption.

As one embodiment, when the chip system switches from the first working state to the second working state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, the address remapping unit closes the volatile memory after receiving the enable signal, enables the nonvolatile memory, maps the code initial operation address of the nonvolatile memory to the storage initial address of the code stored in the nonvolatile memory, and then reduces the frequency of the clock of the system, so that the nonvolatile memory realizes low-power standby according to the system clock operation code after the frequency reduction, wherein the system clock after the frequency reduction is the system clock of the chip system during standby or dormancy. The running codes are stored in the nonvolatile memory, so that the running codes cannot be lost after the nonvolatile memory is powered down, and the switching of the code addresses is performed in an address mapping mode, so that the switching of the memory can be realized only by one part of the running codes, and the development and maintenance difficulty of the running codes is reduced. And in the second working state, the codes are operated through the nonvolatile memory with lower power consumption, so that the operation power consumption of the chip system in the second working state is reduced.

As one embodiment, the CPU unit determines whether the operation state instruction is a first operation state operation instruction or a second operation state operation instruction, including the steps of: the CPU unit starts timing after receiving information of external equipment; if the CPU unit does not receive the information sent by the external equipment again within the set time, the CPU unit judges that the CPU unit receives a second working state operation instruction and enters a second working state; if the CPU unit receives the information sent by the external equipment again within the set time, the CPU unit clears the timing and restarts the timing; if the CPU unit does not receive the second working state operation instruction, the CPU unit judges that the CPU unit receives the first working state operation instruction. And the chip system enters a second working state when the chip system does not work through a periodical calculation method, so that the running power consumption of the chip system is reduced.

As one embodiment, the chip system detects whether the nonvolatile memory and the volatile memory are normal before working; if the nonvolatile memory and the volatile memory are normal, the chip system works normally; if the nonvolatile memory and the volatile memory are abnormal, the chip system sends out an abnormal working instruction and stops working; if one of the nonvolatile memory and the volatile memory is abnormal, the chip system sends out an abnormal working instruction, and codes are run through the normal memory in the first working state and the second working state. The chip system detects the state of the memory before working, prevents the memory from generating problems, and the chip system cannot work normally. Even if one memory is damaged, the system-on-chip can operate in different operating states.

As one embodiment, the CPU unit may detect whether the volatile memory is normal when running the code using the volatile memory; if the volatile memory is normal, the volatile memory continues to run codes; if the volatile memory is abnormal, the CPU unit sends out abnormal working instructions and switches the nonvolatile memory to run codes. When detecting that the memory in which the code is running is abnormal, the memory is switched to another normal memory to run the code, so that the chip system can work normally.

As one embodiment, the CPU unit may detect whether the nonvolatile memory is normal when running the code using the nonvolatile memory; if the nonvolatile memory is normal, the nonvolatile memory continues to run codes with low power consumption; if the nonvolatile memory is abnormal, the CPU unit sends out an abnormal working instruction, wakes up the volatile memory, and then transfers codes from the nonvolatile memory to the volatile memory so that the volatile memory runs the codes according to the target clock. When detecting that the memory in which the code is running is abnormal, the memory is switched to another normal memory to run the code, so that the chip system can work normally.

Compared with the prior art, the utility model has the beneficial effects that: the chip system stores and operates codes through two different memories, and switches the operation storage mode through address remapping, so that the problem of code execution switching under different working states is solved; when detecting that the memory running the codes is abnormal, switching to another normal memory to run the codes, and ensuring the basic functions; in the target clock state line, the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the power consumption of the chip system in low-power operation is reduced.

It is obvious that the above-mentioned embodiments are only some embodiments of the present utility model, but not all embodiments, and that the technical solutions of the embodiments may be combined with each other. Furthermore, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are used in the embodiments, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience in describing the present utility model and simplifying the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation or be constructed and operated in a specific orientation, and thus should not be construed as limiting the present utility model. If the terms "first," "second," "third," etc. are used in an embodiment to facilitate distinguishing between related features, they are not to be construed as indicating or implying a relative importance, order, or number of technical features.

In addition, in the description of the present utility model, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the utility model as defined by the appended claims and their equivalents, which are to be considered as merely preferred embodiments of the present utility model and not as limitations as these to one skilled in the art will be able to make various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A chip system, the chip system comprising:

the CPU unit is used for determining whether to run codes by the nonvolatile memory or the volatile memory according to whether the chip system is in the first working state or the second working state;

the volatile memory is used for carrying codes from the nonvolatile memory to run when the chip system is in the first working state;

a nonvolatile memory for storing the operation code and operating the code according to the target clock when the chip system is in the second working state;

an address remapping unit, configured to reset an address of an operating code when the system-on-chip switches the memory to operate the code;

the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the target clock is a system clock of the chip system in standby or dormancy.

2. A chip system according to claim 1, characterized in that the chip system further comprises a bus unit, which is connected to the address remapping unit and the external device via the bus unit, the bus unit being arranged to transmit electrical signals of the external device to the CPU unit or to transmit electrical signals of the CPU unit to the address remapping unit.

3. The system on a chip of claim 2, wherein when the system on a chip is switched from the first operating state to the second operating state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, and the address remapping unit closes the volatile memory, enables the nonvolatile memory, maps a code initial operation address of the nonvolatile memory to a storage initial address of a code stored in the nonvolatile memory, and then reduces a frequency of a system clock, so that the nonvolatile memory operates the code according to the reduced frequency system clock.

4. The system on a chip of claim 2, wherein when the system on a chip is switched from the second operating state to the first operating state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, and the address remapping unit enables the volatile memory after receiving the enable signal, maps a code initial operation address of the volatile memory to a storage initial address of a code stored in the nonvolatile memory, and enables the volatile memory to operate by transferring the code from the nonvolatile memory when the system on a chip is in the first operating state.

5. A mobile robot, characterized in that it comprises a chip system according to any one of claims 1 to 4.