CN107608824A - A kind of non-volatile computing device and its method of work - Google Patents
A kind of non-volatile computing device and its method of work Download PDFInfo
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- CN107608824A CN107608824A CN201710777421.9A CN201710777421A CN107608824A CN 107608824 A CN107608824 A CN 107608824A CN 201710777421 A CN201710777421 A CN 201710777421A CN 107608824 A CN107608824 A CN 107608824A
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Abstract
The present invention relates to a kind of non-volatile computing device, including memory cell outside processing unit and piece, the processing unit includes central processing unit and piece internal memory storage unit, described outer memory cell includes nonvolatile semiconductor memory member, and described internal memory storage unit includes nonvolatile semiconductor memory member and volatile memory device.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of non-volatile computing device and its method of work.
Background technology
In general, according to the keeping quality of information, memory can be divided into volatile memory and non-volatile deposited
Reservoir, wherein, the data in volatile memory can disappear after a power failure, such as SRAM or dynamic random storage
Device etc., the data in nonvolatile memory will not disappear after going offline, such as flash memory or hard disk etc..
Under normal circumstances, relative to nonvolatile memory, the read or write speed of volatile memory is fast but expensive, because
In computing device, chip external memory typically uses nonvolatile memory, such as tape, disk or flash memory etc. for this；Deposited on piece
Reservoir typically uses volatile memory, such as caching or internal memory etc..Because data can not preserve after volatile memory power down,
When (exception) power-off occurs in computing device, easily there is loss of data, or the problems such as backup/restoration overlong time.
Therefore, it is necessary to which a kind of can prevent loss of data after power down and backup/restoration time short computing device.
The content of the invention
The present invention provides memory cell outside a kind of non-volatile computing device and its method of work, including processing unit and piece,
The processing unit includes on-chip memory cell, and described outer memory cell includes nonvolatile semiconductor memory member and volatile storage
Device, described internal memory storage unit include nonvolatile semiconductor memory member.
Preferably, the volatile memory device in described outer memory cell and nonvolatile semiconductor memory member are integrated in monokaryon
It is interior.
Preferably, the volatile memory device in described outer memory cell and nonvolatile semiconductor memory member employ stacking
Structure.
Preferably, the processor also includes having non-volatile trigger.
Preferably, non-volatile trigger includes master-slave flip-flop and backup module.
Preferably, the backup module includes ferroelectric condenser.
Preferably, the computing device be additionally included in after computing device power-off be the computing device power supply power supply
Unit.
Preferably, said supply unit includes the electric energy collection module that electric energy can be gathered from the external world.
According to another aspect of the present invention, a kind of method of work using above-mentioned computing device is also provided, including：
The computing device is in the general mode of normal work；
When there is abnormal power-down or triggering sleep signal, the computing device enters backup mode；
After the completion of backup, the computing device enters park mode, and each unit is stopped；
When there is wake-up signal, the computing device enters reforestation practices, treats the data full recovery knot of previous backup
Shu Hou, the computing device reenter general mode；
Wherein, under backup mode, the computing device stores the current data in system to the chip external memory
In non-volatile memory device in；In recovery mode, the computing device will be stored in non-easy in the chip external memory
The data recovery in memory device is lost into system.
According to another aspect of the present invention, a kind of method of work using above-mentioned non-volatile trigger is also provided,
Including：
When there is abnormal power-down or triggering sleep signal in non-volatile trigger in normal mode of operation,
Non-volatile trigger preserves the data in the master-slave flip-flop into the backup module；And
When there is wake-up signal, data recovery that non-volatile trigger will be stored in the backup module
Into the master-slave flip-flop.
Relative to prior art, the present invention achieves following advantageous effects：Non-volatile calculating provided by the invention
Device, employ and store this two-level memory structure outside storage and piece on piece, simplify storage hierarchy；Wherein, storage is adopted on piece
With low energy consumption and the non-volatile memory device of high scalability, piece stores employ non-volatile memory device and volatile storage outside
Device, improve the stability and reliability of system；Meanwhile the present invention replaces traditional flip-flop using non-volatile trigger, realize
Data being locally stored in register stage so that in power down, the data in register will not lose computing device, effectively
The storage safety of data is ensure that, the time loss of data backup is reduced, saves the wakeup time of system.
Brief description of the drawings
Fig. 1 is the structural representation according to the non-volatile computing device of present pre-ferred embodiments.
Fig. 2 is the structural representation of the computing device of another embodiment of the present invention.
Fig. 3 is the structural representation of the computing device of another embodiment of the present invention.
Fig. 4 is the structural representation of non-volatile flip-flop used by computing device shown in Fig. 1.
Fig. 5 is the mode of operation switching flow schematic diagram of the computing device shown in Fig. 1.
Embodiment
In order that the purpose of the present invention, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing, to according to this
The further description provided in the embodiment of invention.
In recent years with the development of memory technology, there are many new nonvolatile storages, its performance has obtained very big
Lifting, either all achieve great progress in non-volatile or energy consumption, or access speed or autgmentability etc., its
In the read or write speed of nonvolatile storage that has can reach nanosecond, it is or even suitable with the read or write speed of DRAM internal memories, and
It is higher than traditional DRAM internal memories more power saving, storage density, also there is resisting radiation interference.
Inventor through research, take full advantage of the characteristics of nonvolatile storage can preserve data for a long time under powering-off state,
Using nonvolatile storage as storage outside the piece memory storage in computing device and piece, and additionally use with non-volatile function
Trigger instead of traditional flip-flop, lost and the problems such as data recovery overlong time to solve computer data.
Fig. 1 is according to the structural representation of the non-volatile computing device of present pre-ferred embodiments, as shown in figure 1, this hair
Bright non-volatile computing device includes processor, chip external memory and other conventional devices, for example, input/output (I/O) is single
First (not shown in figure 1).Wherein, processor includes control unit, ALU and on-chip memory, on-chip memory
Nonvolatile semiconductor memory member is employed (equivalent to the caching of conventional computing devices)；Chip external memory (fills equivalent to traditional calculations
The internal memory and external memory put are combined) employ volatibility device and non-volatile device.
Fig. 2 is chip external memory and the structural representation of other devices of the computing device of one embodiment provided by the invention
Figure, as shown in Fig. 2 the chip external memory includes the nonvolatile memory and volatile memory among being encapsulated in monokaryon.Just
Often during work, processor is communicated through bus with the volatile memory in the chip external memory, when power is off, processor warp
Bus marco by the data backup in volatile memory into nonvolatile memory, so as to it is upper electricity after data recovery.
Fig. 3 is the chip external memory of another embodiment and the structural representation of other devices of computing device provided by the invention
Figure, as shown in figure 3, the chip external memory includes by the way of being stacked using 3D the volatile memory that integrates and non-volatile
Property memory, for example, the bit of two kinds of memory devices can be set using one-to-one mode, to enter computing device
During row data backup, the data of correspondence position can be with simultaneous transmission, so as to realize parallel backup.
In one embodiment of the invention, above-mentioned computing device may also include I/O equipment, and I/O equipment utilizations input is defeated
Outgoing interface is connected with computing device, is the extraneous important component for entering row information with computing device and exchanging, and processor utilizes bus pair
I/O equipment is controlled, such as display, mouse and keyboard etc..
As shown in Figures 2 and 3, in one embodiment of the invention, above-mentioned computing device may also include power supply unit, should
Power supply unit can be system power supply within a period of time after system cut-off, so that processor carries out data backup.The power supply is set
It is standby to use, for example, battery, external power supply or it is other can be from the electric energy collection module of outside collection electric energy (such as solar cell
Plate etc.).
In another embodiment of the present invention, the non-volatile memory device used in above-mentioned computing device, for example, on piece
The nonvolatile storage in non-volatile memory device and chip external memory employed in memory, can be phase transition storage
(phase change memory, PCM), magnetic RAM (Magnetic Random Access Memory, MRAM),
Spin-torque conversion random access memory (Spin Torque Transfer Random Access Memory, STT-RAM), iron
Electric random access memory (Ferroelectric RAM, FeRAM) or resistive random access memory (RRAM) etc..
Fig. 5 is the mode of operation switching flow schematic diagram of the computing device shown in Fig. 1, as shown in figure 5, according to the present invention's
One embodiment, there is provided a kind of method of work of non-volatile computing device, the method for the computing device specifically include following four
Pattern：
General mode：In the normal mode, the power supply normal power supply of computing device, system are in normal mode of operation.
Wherein, the power supply mode of power supply can use such as battery powered, mains-supplied or be gathered using electric energy collection module from the external world
Electric energy etc.；
Backup mode：Under backup mode, by power supply power switching to being powered by power supply unit, system is in computing device
Data backup pattern, i.e., the various data storages performed when power supply is powered are into non-volatile memory device, for example, non-volatile
In trigger, the data in master-slave flip-flop are preserved into its backup module；In chip external memory, volatile deposit will be operated in
Data in memory device are preserved into non-volatile memory device；
Park mode：In the hibernation mode, each unit of computing device is stopped；
Reforestation practices：In recovery mode, computing device is by power-off or power supply unit power switching to being powered by power supply
System recovers data from the last backup mode of range recovery pattern first, i.e., to being stored in this backup mode to non-easy
The various data lost in memory device are reduced, for example, in non-volatile trigger, the data that will be stored in backup module
Recover into master-slave flip-flop；In chip external memory, the data recovery being stored in non-volatile memory device is deposited to volatile
In memory device.
Computing device provided by the invention is generally in the general mode of normal work, when occur abnormal power-down or triggering stop
During dormancy signal, computing device enters backup mode；After the completion of backup, computing device is closed or into park mode, is stopped power supply,
Without any work；When reopening computing device or wake-up signal occur, computing device enters reforestation practices, treats previous
After the data full recovery of backup terminates, computing device reenters general mode.
Fig. 4 is the structural representation of the non-volatile flip-flop of the computing device shown in Fig. 1, as shown in figure 4, above-mentioned processing
Trigger in device employs non-volatile flip-flop, for example, the trigger can be a kind of triggering based on ferroelectric memory
Device (ferroelectricity trigger), the ferroelectricity trigger include the backup with the hypotactic trigger of tradition and with ferroelectric condenser
Module.Wherein, when computing device normal work, using traditional hypotactic trigger, when computing device needs
During backup, the service data in host-guest architecture trigger can be backed up to backup module.
Present invention also offers a kind of data back up method of non-volatile trigger, by taking ferroelectricity trigger as an example, when
When computing device is in above-mentioned general mode, R/W signal is low level, working method and the traditional flip-flop one of ferroelectricity trigger
Cause；When computing device is in backup mode, R/W signal is high level, and pch signals are low level, and ferroelectricity trigger can be carried out
Configure, now Clk signal is in high level, and PL signals produce a high level pulse, can deposit the data in master-slave flip-flop
Storage is in ferroelectric condenser C1 and C2；When computing device is in reforestation practices, it is necessary to perform read operation to backup module, i.e.,
Din signals and Clk signal keep low level, and Pch signals, which produce high level pulse, makes capacitor discharge, and PL signals produce high level
Pulsed drive ferroelectric condenser pair, so that by data recovery into master-slave flip-flop.
Wherein, Din signals are the input signal of trigger, and Pch is charging control signal, and PL is pulse control signal, RW
For mode select signal.
Although described exemplified by the above-described embodiments, employing the trigger based on ferroelectric memory provided by the invention
Computing device with non-volatile trigger and using the trigger, but it will be recognized by one of ordinary skill in the art that
Herein have non-volatile trigger be not limited to include to be based on Ferroelectric Random Access Memory (Ferroelectric RAM,
FeRAM trigger), can also be for example based on spin-torque conversion random access memory (Spin Torque Transfer
Random Access Memory, STT-RAM) trigger or trigger based on resistive random access memory (RRAM) etc. it is a variety of
Type.
Relative to prior art, the non-volatile computing device provided in embodiments of the present invention, it is non-to employ two-stage
Volatile storage structure, it can reduce the time loss of data backup with the safety of effective guarantee service data, save calling out for system
Wake up the time, this storage organization can be that the data storage mechanism of computing device starts a kind of brand-new design concept.
Although the present invention be described by means of preferred embodiments, but the present invention be not limited to it is described here
Embodiment, also include made various changes and change without departing from the present invention.
Claims (10)
1. a kind of non-volatile computing device, including memory cell outside processing unit and piece, the processing unit includes depositing on piece
Storage unit, described outer memory cell include nonvolatile semiconductor memory member and volatile memory device, described internal memory storage unit
Including nonvolatile semiconductor memory member.
2. non-volatile computing device according to claim 1, it is characterised in that volatile in described outer memory cell
Property memory device and nonvolatile semiconductor memory member are integrated in monokaryon.
3. non-volatile computing device according to claim 2, it is characterised in that volatile in described outer memory cell
Property memory device and nonvolatile semiconductor memory member employ stacked structure.
4. non-volatile computing device according to claim 1, it is characterised in that the processor is also included with non-easy
The trigger for the property lost.
5. non-volatile computing device according to claim 4, it is characterised in that non-volatile trigger includes
Master-slave flip-flop and backup module.
6. non-volatile computing device according to claim 5, it is characterised in that the backup module includes ferroelectric capacitor
Device.
7. non-volatile computing device according to claim 1, it is characterised in that the computing device is additionally included in described
It is the power supply unit of the computing device power supply after computing device power-off.
8. non-volatile computing device according to claim 7, it is characterised in that said supply unit includes can be from outer
Boundary gathers the electric energy collection module of electric energy.
9. a kind of method of work of computing device as any one of claim 1 to 8, including：
The computing device is in the general mode of normal work；
When there is abnormal power-down or triggering sleep signal, the computing device enters backup mode；
After the completion of backup, the computing device enters park mode, and each unit is stopped；
When there is wake-up signal, the computing device enters reforestation practices, after the data full recovery of previous backup terminates,
The computing device reenters general mode；
Wherein, under backup mode, the computing device stores the current data in system into the chip external memory
In non-volatile memory device；In recovery mode, the computing device non-volatile is deposited be stored in the chip external memory
Data recovery in memory device is into system.
10. a kind of method of work of non-volatile trigger as any one of claim 4 or 6, including：
It is described when abnormal power-down or triggering sleep signal occurs in non-volatile trigger in normal mode of operation
Non-volatile trigger preserves the data in the master-slave flip-flop into the backup module；And
When there is wake-up signal, non-volatile trigger is by the data recovery being stored in the backup module to institute
State in master-slave flip-flop.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110968258A (en) * | 2018-09-30 | 2020-04-07 | 华为技术有限公司 | Control method and device of storage disk |
| CN111966525A (en) * | 2020-10-23 | 2020-11-20 | 中国人民解放军国防科技大学 | DSP program operation method of satellite-borne navigation equipment and DSP system thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420744B1 (en) * | 1999-11-16 | 2002-07-16 | Samsung Electronics Co., Ltd. | Ferroelectric capacitor and method for fabricating ferroelectric capacitor |
| CN104620232A (en) * | 2012-09-10 | 2015-05-13 | 德克萨斯仪器股份有限公司 | Control of dedicated non-volatile arrays for specific function availability |
| CN104699413A (en) * | 2013-12-09 | 2015-06-10 | 群联电子股份有限公司 | Data management method, memorizer saving device and memorizer control circuit unit |
| CN105144074A (en) * | 2013-04-12 | 2015-12-09 | 微软技术许可有限责任公司 | Block storage using a hybrid memory device |
| CN106126439A (en) * | 2007-07-25 | 2016-11-16 | 技佳科技有限公司 | Variable partition in mixing storage subsystem |
| CN106775476A (en) * | 2016-12-19 | 2017-05-31 | 中国人民解放军理工大学 | Mixing memory system and its management method |
| CN106951392A (en) * | 2013-11-12 | 2017-07-14 | 上海新储集成电路有限公司 | A kind of quick startup low-power consumption computer on-chip system with self-learning function |
-
2017
- 2017-09-01 CN CN201710777421.9A patent/CN107608824B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6420744B1 (en) * | 1999-11-16 | 2002-07-16 | Samsung Electronics Co., Ltd. | Ferroelectric capacitor and method for fabricating ferroelectric capacitor |
| CN106126439A (en) * | 2007-07-25 | 2016-11-16 | 技佳科技有限公司 | Variable partition in mixing storage subsystem |
| CN104620232A (en) * | 2012-09-10 | 2015-05-13 | 德克萨斯仪器股份有限公司 | Control of dedicated non-volatile arrays for specific function availability |
| CN104620192A (en) * | 2012-09-10 | 2015-05-13 | 德克萨斯仪器股份有限公司 | Nonvolatile logic array and power domain segmentation in processing device |
| CN105144074A (en) * | 2013-04-12 | 2015-12-09 | 微软技术许可有限责任公司 | Block storage using a hybrid memory device |
| CN106951392A (en) * | 2013-11-12 | 2017-07-14 | 上海新储集成电路有限公司 | A kind of quick startup low-power consumption computer on-chip system with self-learning function |
| CN104699413A (en) * | 2013-12-09 | 2015-06-10 | 群联电子股份有限公司 | Data management method, memorizer saving device and memorizer control circuit unit |
| CN106775476A (en) * | 2016-12-19 | 2017-05-31 | 中国人民解放军理工大学 | Mixing memory system and its management method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110968258A (en) * | 2018-09-30 | 2020-04-07 | 华为技术有限公司 | Control method and device of storage disk |
| CN110968258B (en) * | 2018-09-30 | 2021-09-07 | 华为技术有限公司 | Control method and device of storage disk |
| CN111966525A (en) * | 2020-10-23 | 2020-11-20 | 中国人民解放军国防科技大学 | DSP program operation method of satellite-borne navigation equipment and DSP system thereof |
| CN111966525B (en) * | 2020-10-23 | 2021-03-26 | 中国人民解放军国防科技大学 | DSP program operation method of satellite-borne navigation equipment and DSP system thereof |
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