CN111966525B - DSP program operation method of satellite-borne navigation equipment and DSP system thereof - Google Patents
DSP program operation method of satellite-borne navigation equipment and DSP system thereof Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The invention discloses a DSP program running method of satellite navigation equipment and a DSP system thereof, which are characterized in that an effective scheme of combining off-chip running with on-chip detection is adopted, a method of fusing multiple means is adopted, and four steps of main code and detection code space distinguishing distribution, on-chip and off-chip program combined loading, on-chip and off-chip storage self-checking and EDAC (electronic design automation) checking of an off-chip SRAM (static random access memory) are comprehensively utilized, so that the problem of weak single-particle resistance of an on-chip RAM of the satellite navigation equipment DSP is solved, and the stability of program running is improved. The invention has good adaptability, is not only suitable for satellite-borne equipment of a navigation system, but also suitable for satellite-borne equipment of a radar and a communication system, is also suitable for partial satellite-borne transmitters, and can enhance the single particle protection capability of the satellite-borne equipment.
Description
Technical Field
The invention relates to the field of satellite-borne navigation equipment, in particular to a DSP program operation method of satellite-borne navigation equipment and a DSP system thereof.
Background
The artificial satellite is an important medium for human exploration and utilization of space resources, DSP is largely used in satellite-borne navigation equipment for signal processing, and the DSP is applied to various satellite-borne equipment such as satellite communication, navigation and radar at present.
The satellite-borne navigation equipment generally uses a DSP as a logic control and operation unit, and the control and algorithm of the satellite-borne navigation equipment are usually integrated into the DSP for completion. The DSP chip adopts a Harvard bus structure with separated programs and data, adopts a special hardware multiplier and uses a pipeline processing technology to realize the purpose of rapidly processing various digital signals.
In the satellite-borne navigation device, considering that the capacity of an internal RAM storage area of a DSP chip is small and the irradiation resistance is weak, an off-chip memory with strong irradiation resistance is usually added outside the chip. The general radiation-resistant total dose of the DSP chip is 1E5 rad, and the anti-single particle latch-up threshold value is 89Mev-cm 2/mg. The radiation-resistant total dose of the common aerospace-grade SRAM chip SMV512K32 is 3E5 rad, the single-particle-resistant latch-up threshold value is 110Mev-cm2/mg, and the radiation-resistant capability of the common aerospace-grade SRAM chip is far stronger than that of a common DSP chip. Therefore, DSP programs typically run primarily off-chip memory space. Meanwhile, the satellite-borne navigation equipment faces the complex electromagnetic environment of the outer space after being launched into the orbit, so that the software has high reliability requirements, and when a DSP external storage device is knocked over by a single particle and fails instantaneously, the DSP external storage device needs to be capable of detecting and attempting to recover. The current DSP cannot solve the problem that the on-chip RAM of the satellite navigation equipment DSP is easy to be knocked over by single particles under a complex electromagnetic environment.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a DSP program operation method of satellite navigation equipment and a DSP system thereof, which can solve the problem that the on-chip RAM of the satellite navigation equipment DSP is easy to be knocked over by single particles under a complex electromagnetic environment.
The DSP program running method of the satellite-borne navigation equipment according to the embodiment of the invention comprises the following steps: distinguishing and distributing main codes and detection codes, carrying out on-chip and off-chip program combined loading, carrying out on-chip and off-chip storage self-checking and carrying out EDAC (electronic design automation) checking on an off-chip SRAM (static random access memory);
and (3) distinguishing and allocating main codes and detection code spaces: placing a main code segment and an important data segment in a DSP program into an off-chip program storage space, and placing an off-chip storage self-checking code into an on-chip storage space;
the method comprises the following steps of carrying out combined loading of an on-chip and an off-chip program, namely setting a loading mode of a DSP as a default to start and execute from an off-chip program storage space, dividing a program into three blocks with continuous address spaces, namely an external program and data block, an internal code block and other data blocks, wherein the external program and the data block comprise main code segments and important data segments, the internal code block comprises an off-chip storage self-checking code segment, and the other data blocks comprise non-important data segments;
after the DSP is electrified and reset, the hardware automatically moves an external program and a secondary moving program in the data block to the initial position of the off-chip program storage space; after the moving is finished, starting to execute a secondary moving program from the off-chip program storage space to carry out secondary moving, wherein the secondary moving program firstly moves all the remaining external program blocks to the appointed position of the off-chip storage space, then moves the internal code blocks to the on-chip code storage area, and finally moves other data blocks to the on-chip data storage area;
power-on off-chip storage self-checking: in the step B1, the second moving program jumps to the off-chip storage self-test code located in the on-chip storage space before executing the second moving to perform the off-chip storage self-test, if the self-test is passed, the second moving is performed, otherwise, the second moving program interrupts the moving process and resets the whole machine;
EDAC verification of off-chip SRAM: the external storage chip is an SRAM chip with an EDAC, and an EDAC verification function is started during initialization.
The DSP of the satellite navigation equipment comprises a DSP chip, and the DSP chip operates the DSP program operation method of the satellite navigation equipment.
The DSP program operation method of the satellite navigation equipment and the DSP system thereof according to the embodiment of the invention at least have the following technical effects: the implementation mode of the invention combines the effective scheme of on-chip detection by off-chip operation, and comprehensively uses four steps of distinguishing and distributing main codes and detection code space, carrying out on-chip and off-chip program combined loading, carrying out on-chip and off-chip storage self-detection, and carrying out EDAC (electronic design automation) verification on an off-chip SRAM (static random access memory). And main codes and important data are distributed to an external SRAM, EDAC verification is added, the single event resistance of the program is enhanced, and stable operation of core functions is guaranteed. The external storage self-check of the upper chip can detect the problems of an external SRAM address line or a data line when the power is on, so that the subsequent program operation is ensured not to have problems, and when the external SRAM has transient problems due to the influence of single particles, the external SRAM is recovered through the reset of the whole machine, so that the reliability is further ensured.
The embodiment of the invention adopts a method of fusing various means, solves the problem of weak single particle resistance of the RAM in the DSP chip of the satellite-borne navigation equipment, improves the stability of program operation, and can realize the on-orbit long-time stable operation of the satellite-borne receiver for more than 2 years. The invention has good adaptability, is not only suitable for satellite-borne equipment of a navigation system, but also suitable for satellite-borne equipment of a radar and a communication system, is also suitable for partial satellite-borne transmitters, and can enhance the single particle protection capability of the satellite-borne equipment.
According to some embodiments of the present invention, the loading mode of the DSP in the off-chip program joint loading is configured by hardware as MAP 0.
According to some embodiments of the present invention, the step of on-chip off-chip program joint loading assigns a second move program to the start of the external program and data block and does not exceed 64 KB.
According to some embodiments of the present invention, the step of moving the internal code block to the on-chip code storage area by the second moving program in the off-chip program combined loading is indirectly completed in a DMA manner.
According to some embodiments of the invention, the step of powering off-chip memory self-test is performed when the off-chip memory self-test function is assigned to the on-chip code memory area at compile time and is performed only at power-on.
According to some embodiments of the invention, the off-chip memory self-test algorithm in the off-chip memory self-test in the step adopts a shift test of 1 to test the data line and the address line with the width of 32 bits respectively.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of allocation of main code and detection code spaces in an embodiment of the present invention;
FIG. 2 is a flowchart illustrating the process of on-chip and off-chip program joint loading according to an embodiment of the present invention;
FIG. 3 is a logic flow diagram of a power-on off-chip memory self-test in an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
A DSP program operation method of satellite-borne navigation equipment comprises the following steps: the method comprises four steps of distinguishing and distributing main codes and detection code spaces, carrying out on-chip and off-chip program combined loading, carrying out on-chip and off-chip storage self-detection and carrying out EDAC (electronic design automation) verification on an off-chip SRAM (static random access memory).
In the embodiment of the invention, a DSP chip with the model number of SMJ320C6701 is taken as an example to describe four steps in detail, and the SMJ320C6701 is an aerospace-level radiation-resistant floating-point DSP processor designed by TI and is a commonly-used digital processing DSP chip in satellite-borne navigation equipment. The highest working frequency can reach 140MHz, and the device is provided with an on-chip code storage area of 64KB and an on-chip data storage area of 64 KB.
A1, distinguishing and allocating main code and detection code spaces: the SMJ320C6701DSP program was developed using the tool Code Composer Studio (CCS) provided by TI, and the Code and data in the program are represented in segments, where the text segment is the Code segment and the rest are the data segments. CCS controls the generation of each code segment through a linker, and provides a 'cmd' file to perform custom distribution on the code segments. The method comprises the steps of utilizing a 'cmd' file provided by a CCS to place important CODE segments and data segments into an external memory, assigning default 'text' main CODE segments and important data segments such as 'bss', 'cinit' to an off-chip storage space, additionally creating 'inner _ text' CODE segments, assigning the 'inner _ text' CODE segments to the on-chip storage space for placing off-chip storage self-check CODEs, and assigning the off-chip storage self-check CODEs to the 'inner _ text' CODE segments by combining with 'CODE _ SECTION' pre-compiling instructions provided by a CCS compiler, so that the main CODEs and the detection CODE spaces are distributed in a distinguishing mode.
Referring to fig. 1, the specific steps of allocating the main code and the detection code space are as follows:
a11: creating a code segment of 'boot' in a 'cmd' file of the CCS, positioning the code segment to the starting position of an off-chip program storage space, and assigning a secondary moving program to the code segment of 'boot';
a12: creating a 'text' code segment in a 'cmd' file of the CCS, positioning the code segment to other positions of an off-chip storage space, and assigning the code to the 'text' code segment by default by a compiler;
a13: creating a CODE segment of 'inner _ text' in a 'cmd' file of the CCS, locating the CODE segment to the start of an on-chip storage CODE space, and assigning a power-on self-test function CODE to the CODE segment of 'inner _ text' through a 'CODE _ separation' pre-compiling instruction;
a14: and positioning default data segments such as ". bss", ". cinit" and the like to an off-chip storage space in the CCS by configuring a compiler memory option.
The main code and the detection code space are allocated in a distinguishing mode and have the following functions: the external SRAM has strong irradiation capability, and simultaneously has EDAC, and the main code and the detection code space are distributed in different modes, so that the program main body and the important data can be prevented from being overturned by single particles by distributing the main body code and the important data to the external SRAM, and the stability is enhanced.
B1, jointly loading the on-chip and off-chip programs: the SMJ320C6701DSP load mode is configured by hardware in a MAP0 manner to default to starting execution from out-program memory space. To simplify the design, the program is divided into three blocks with continuous address space, namely an "external program and data block", which contains important data segments and code segments, an "internal code block", which contains only off-chip store self-test code segments, and an "other data block", which contains only data segments.
In MAP0 mode, the start address is located in off-chip program memory space, and the secondary move program needs to be assigned to the beginning of the "external program and data block" and does not exceed 64 KB. After the DSP is powered on and reset, the hardware automatically moves all the external programs and data blocks from 0x01000000 addresses to the beginning of the off-chip program storage space by 64 KB. And after the moving is finished, starting execution from the off-chip program storage space. When the secondary moving program starts to execute, the self-check of the off-chip storage is executed firstly, after the self-check is passed, all the residual external program blocks are moved to the appointed position of the off-chip storage space, then the internal code blocks are moved to the 64KB on-chip code storage area, and finally the other data blocks are moved to the 64KB on-chip data storage area.
It should be noted that, since the DSP core has no write right to the 64KB on-chip code storage space, when the second move program moves the "internal code block", it needs to be indirectly completed through DMA.
Referring to fig. 2, the specific steps of program block loading are as follows:
b11: DSP hardware automatically moves 64KB of 'external code blocks' from 0x01000000 addresses to off-chip program storage space;
b12: the secondary moving program moves the rest part of the external program block to the position of 0x00010000 of the off-chip storage space;
b13: the secondary moving program moves all the 'internal code blocks' 64KB to the position of the on-chip memory space 0x 01400000;
b14: the second move program moves the program data of "other data block" 64KB to the position of the data space 0x80000000 in the chip.
The combined loading of the on-chip and off-chip programs has the following functions: the method solves the mapping problem of multi-section programs in a MAP0 mode, so that the programs can run in an internal SRAM and an external SRAM simultaneously, and after the loading is finished, the off-chip storage self-check codes and the program main body which are positioned in the on-chip space can run.
C1, self-checking of upper chip external storage: and the secondary moving program jumps to the off-chip storage self-checking code positioned in the off-chip space to carry out off-chip storage self-checking before moving, and carries out secondary moving if the self-checking is passed, otherwise, the secondary moving program interrupts the moving process and resets the whole machine. The power-on off-chip storage self-check is used for carrying out self-check operation on the whole off-chip storage address space, and the off-chip storage self-check can damage off-chip storage contents, so that a self-check function needs to be assigned to an on-chip code storage area during compiling and is only carried out during power-on. The test algorithm uses a simple "shift test of 1" to test the 32Bit wide data and address lines, respectively.
Referring to fig. 3, the specific steps are:
c11: resetting the DSP;
c12: the program of 64KB before hardware transfer, namely the whole secondary transfer program is transferred;
c13: initializing hardware by a secondary moving program;
c14: and carrying out self-checking operation on the whole off-chip storage address space, respectively carrying out '1 displacement test' on the data line and the address line, if the data line and the address line are normal, starting an application program to execute, and otherwise, executing whole machine reset.
The function of the power-on off-chip storage self-check is as follows: the method aims to detect whether an external SRAM has the problem of address lines or data lines before a program main body runs, and if the problem is a single event problem, the problem can be solved by resetting the whole machine, so that a reset strategy is adopted when the problem is detected by power-on self-detection.
D1, EDAC verification of off-chip SRAM: the external storage chip is an SRAM chip with an EDAC, such as SMV512K32, and the EDAC verification function is turned on during initialization.
The role of the EDAC check of the off-chip SRAM is: the EDAC has the function that when the content of the SRAM outside the chip is knocked over by a single particle, the content can be corrected back through an EDAC algorithm, the program running stability can be enhanced, and the RAM inside the chip has no EDAC checking function.
The embodiment of the invention also comprises a DSP chip for operating the method, and the method is also suitable for other types of DSP chips except the SMJ320C 6701.
In summary, the embodiment of the invention designs an effective scheme combining off-chip operation and on-chip detection aiming at the problem that the on-chip RAM of the DSP processor of the satellite-borne navigation equipment is easy to be knocked over by single particles under a complex electromagnetic environment. The scheme comprehensively uses four steps of distinguishing and distributing main codes and detection code spaces, carrying out combined loading of on-chip and off-chip programs, carrying out self-detection on-chip and off-chip storage, and checking EDAC of an off-chip SRAM.
The negative influence of the single event effect on the program operation of the internal memory device of the DSP processor of the satellite navigation equipment can be effectively reduced.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (6)
1. A DSP program operation method of satellite-borne navigation equipment is characterized by comprising the following steps: distinguishing and distributing main codes and detection codes, carrying out on-chip and off-chip program combined loading, carrying out on-chip and off-chip storage self-checking and carrying out EDAC (electronic design automation) checking on an off-chip SRAM (static random access memory);
a1, distinguishing and allocating main code and detection code spaces: placing a main code segment and an important data segment in a DSP program into an off-chip program storage space, and placing an off-chip storage self-checking code into an on-chip storage space;
b1, jointly loading the on-chip and off-chip programs, namely setting the loading mode of the DSP as default to start execution from the off-chip program storage space, dividing the program into three blocks with continuous address spaces, namely an external program and data block, an internal code block and other data blocks, wherein the external program and the data block comprise a main code segment and an important data segment, the internal code block comprises an off-chip storage self-checking code segment, and the other data blocks comprise non-important data segments;
after the DSP is electrified and reset, the hardware automatically moves an external program and a secondary moving program in the data block to the initial position of the off-chip program storage space; after the moving is finished, starting to execute a secondary moving program from the off-chip program storage space to carry out secondary moving, wherein the secondary moving program firstly moves all the remaining external program blocks to the appointed position of the off-chip storage space, then moves the internal code blocks to the on-chip code storage area, and finally moves other data blocks to the on-chip data storage area;
c1, self-checking of upper chip external storage: in the step B1, the second moving program jumps to the off-chip storage self-test code located in the on-chip storage space before executing the second moving to perform the off-chip storage self-test, if the self-test is passed, the second moving is performed, otherwise, the second moving program interrupts the moving process and resets the whole machine;
d1, EDAC verification of off-chip SRAM: the external storage chip is an SRAM chip with an EDAC, and an EDAC checking function is started during initialization;
the off-chip memory self-test algorithm in the step C1 adopts a shift test of 1 to test the data line and the address line with the width of 32 bits respectively, and the specific steps are
C11: resetting the DSP;
c12: the hardware moves the whole secondary moving program;
c13: initializing hardware by a secondary moving program;
c14: and carrying out self-checking operation on the whole off-chip storage address space, respectively carrying out 1-shift test on the data line and the address line, if the test is normal, starting an application program to execute, and otherwise, executing complete machine reset.
2. The DSP program operating method of a satellite navigation device according to claim 1, characterized in that: the loading mode of the DSP in the step B1 is configured in a MAP0 mode through hardware.
3. The DSP program operating method of a satellite navigation device according to claim 1, characterized in that: the step B1 assigns the second move procedure to the start of the external procedure and data block and does not exceed 64 KB.
4. The DSP program operating method of a satellite navigation device according to claim 1, characterized in that: the second moving procedure in step B1 indirectly completes the internal code block moving to the on-chip code storage area by DMA.
5. The DSP program operating method of a satellite navigation device according to claim 1, characterized in that: the off-chip store self-test-time self-test function in said step C1 is specified to be allocated to the on-chip code storage area at compile time and is only performed at power-on.
6. A DSP system of satellite-borne navigation equipment is characterized in that: the method comprises a DSP chip, wherein the DSP chip runs the DSP program running method of the satellite navigation equipment of any one of claims 1 to 5.
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