CN105761756A - Scheme for improving performance and reliability of mass solid state disc by utilizing high-performance non-volatile solid-state memory - Google Patents
Scheme for improving performance and reliability of mass solid state disc by utilizing high-performance non-volatile solid-state memory Download PDFInfo
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- CN105761756A CN105761756A CN201610070016.9A CN201610070016A CN105761756A CN 105761756 A CN105761756 A CN 105761756A CN 201610070016 A CN201610070016 A CN 201610070016A CN 105761756 A CN105761756 A CN 105761756A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- Computer Security & Cryptography (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to a scheme for improving the performance and the reliability of a mass solid state disc by utilizing a high-performance non-volatile solid-state memory, and relates to a design of a solid state disc. The scheme at least comprises a relatively large amount of low-cost solid state mass storage media (such as an NAND Flash), a relatively small amount of high-performance non-volatile solid-state storage media (such as an mRAM), a master controller and a corresponding firmware algorithm. By the design of an optimization algorithm, the advantages of the two types of storage media are effectively utilized, and the shortcomings of the two types of storage media are avoided, so that the overall hybrid solid state disc has the characteristics of high performance, low power consumption, and reliability and durability in complicated and adverse electrical appliance environment.
Description
Technical field
The present invention relates to the design of solid state hard disc and realization, particularly relate to the design of a kind of performance and reliability by the non-volatile solid-state memory of high-performance to improve solid state hard disc.
Background technology
Solid state hard disc is with its intrinsic high-performance, and the advantage of low-power consumption and high reliability just replaces traditional mechanical type hard disk with the powerful impetus.The main flow storage medium of existing solid state hard disc is all based on NANDFlash memorizer.Although NANDFlash has lot of advantages becomes the main flow medium of solid-state mass memory, but it also has some very intractable weakness to make designer have to spend substantial amounts of energy algorithmically to tackle, and need extra hardware spending to make up the harmful effect that these weakness are brought.
The designer being familiar with NANDFlash both knows about, and the drawback of many NANDFlash all originates from one of its fundamental characteristics, and namely NANDFlash memorizer cannot original position be rewritten.In simple terms, NANDFlash must wipe before rewriteeing, and must write in units of the page of some KB sizes and need to wipe in units of bigger block.This makes the another one serious shortcomings of NANDFlash, and namely the very limited amount of write/erase cycle, more prominent.For reducing the impact of above-mentioned two drawback, rewriting the page need to be realized by transposition write new page.This makes again logical page (LPAGE) and physical page lose simple directly corresponding relation, need to be followed the tracks of this relation dynamically changed by mapping table.
Generally all comprising capacity in the design of solid state hard disc relatively small but can the random access memory (DRAM of chip exterior or the SRAM of inside) that rewrites of original place be used for preserving above-mentioned mapping table and being used as quickly temporary, firmware algorithm can attempt to complete to reduce the consume to NANDFlash in this is quickly temporary by operation as much as possible.
Introduce this random access memory (RAM) and bring some new problems, the problem such as including cost, power consumption, complexity, reliability.Wherein power down protection and startup time the two are particularly problematic.This is because along with the increase of hard-disk capacity, mapping table is as well as increase, the time building table when not only powering in RAM also can be very long, affect user to experience, even by the basic standard of industry, and can not preserve when power down in RAM that data required time also can be very long, it is necessary to expensive capacitor extends the continuous electricity time, otherwise very easily cause loss of data so that the reliability of hard disk receives serious impact.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the invention provides a kind of scheme based on the non-volatile random access memory of high-performance (hereinafter referred to as NVRAM), improve above-mentioned various problems.
The technical solution adopted in the present invention is: replaced by the DRAM high-performance NVRAM in traditional design.Current high performance NVRAM is very active as the research and development of next generation computer storage medium.Wherein several novel memory devices (including PhaseChangeMemory-PCM, MegnetoResistiveRAM-mRAM and FerroelectricRAM-FeRAM) get a good chance of thoroughly changing the general layout of storage system.Although the restriction being additionally subjected to integration density and cost as main force's massage storage with these memorizeies is still immature, but its excellent characteristic can be used in the design of solid state hard disc the performance improving system aspects completely.The present invention utilizes two key properties of NVRAM, namely non-volatile and random access nature can improve the readwrite performance of solid-state disk, reliability and cost.
With compared with the scheme of DRAM, the scheme based on NVRAM has the advantage that
1.NVRAM can be used to deposit mapping table as DRAM; and be used to be used as quickly temporary, but owing to NVRAM information after a power failure will not be lost, the external circuit for power down protection can be greatly simplified; reduce system complexity and cost, improve the reliability of system simultaneously.
2. it is stored in the mapping table in NVRAM without rebuilding after a power failure, greatly reduces system reboot time, improve user and experience.
The region data when power down being used as fast reading and writing buffer memory in 3.DRAM may be lost.As this fast cache district realizes in NVRAM, data will not be lost, thus increasing the reliability of system.
4. owing to NVRAM has excellent readwrite performance, and data will not be lost when power down, and this makes it be adapted to do depositing and running space of system firmware code, thus reducing the demand to system SRAM, reduces system cost.
Accompanying drawing explanation
Fig. 1 is the system block diagram contrast with legacy system block diagram of the present invention；
Fig. 2 is the system control process figure of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is further described.
As shown in mechanism map 1, the present invention is replaced by NVRAM in the present invention with the DRAM that main difference is that in traditional design of traditional design, and power-down protection circuit required in traditional design is omitted in the present invention.Due to the non-volatile characteristic of NVRAM, being aided with in firmware corresponding control program, this simplification design will be better than traditional scheme at nearly all aspect of performance (including read or write speed, power consumption, reliability, cost and complexity etc.).
Simplify control flow as shown in Figure 2.In systems in operation process, imminent power loss event triggers an interrupt signal, and this signal will make system enter power down protection program.The main task of this program is to be stored in NVRAM by the low volume data in SRAM and internal register then relevant for system parts to be placed in write-protect pattern.
After system powers on again, by entered environment detection and the program of reply.The main task of this program is to ensure that power supply enters steady statue, then by the environment recovery before power down the breakpoint succession normal operating before returning to power down.
Claims (3)
1. the design of a high-performance high reliability solid state hard disc comprises the control algolithm that at least one main controller runs, one or more solid storage medium unit (such as NANDFlash chip), one or more for depositing the logic area code random access memory to the mapping table of physics area code, and the random access memory in fast reading and writing working area, it is characterised in that this random access memory is realized by NVRAM.
2. solid state hard disc design according to claim 1, it is characterized in that: described NVRAM is MegnetoResistiveRAM (mRAM), or PhaseChangeMemory (PCM), or FerroelectricRAM (FeRAM).
3. solid state hard disc design according to claim 1, it is characterised in that: environmental variable is stored in NVRAM and then system is placed in write-protect pattern after power down triggering signal being detected by described control algolithm.Described algorithm recovers environmental variable after re-powering and carries out normal operating from the breakpoint succession before power down.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610070016.9A CN105761756A (en) | 2016-02-01 | 2016-02-01 | Scheme for improving performance and reliability of mass solid state disc by utilizing high-performance non-volatile solid-state memory |
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| CN201610070016.9A CN105761756A (en) | 2016-02-01 | 2016-02-01 | Scheme for improving performance and reliability of mass solid state disc by utilizing high-performance non-volatile solid-state memory |
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| CN105761756A true CN105761756A (en) | 2016-07-13 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107832018A (en) * | 2017-11-22 | 2018-03-23 | 深圳忆联信息系统有限公司 | A kind of RAID implementation and SSD |
| TWI673722B (en) * | 2017-05-30 | 2019-10-01 | 美商司固科技公司 | Data storage device with rewritable in-place memory |
| CN108647157B (en) * | 2018-03-14 | 2021-10-01 | 深圳忆联信息系统有限公司 | Mapping management method based on phase change memory and solid state disk |
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| CN102662802A (en) * | 2012-05-08 | 2012-09-12 | 无锡云动科技发展有限公司 | Full-system power failure recovery method and equipment based on nonvolatile memory |
| CN103049397A (en) * | 2012-12-20 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Method and system for internal cache management of solid state disk based on novel memory |
| CN103324578A (en) * | 2013-06-20 | 2013-09-25 | 深圳市瑞耐斯技术有限公司 | NAND flash memory device and random writing method thereof |
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2016
- 2016-02-01 CN CN201610070016.9A patent/CN105761756A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101122865A (en) * | 2007-04-26 | 2008-02-13 | 晶天电子（深圳）有限公司 | Computer mainboard quick suspending and recovery device using phase-change memory |
| CN102662802A (en) * | 2012-05-08 | 2012-09-12 | 无锡云动科技发展有限公司 | Full-system power failure recovery method and equipment based on nonvolatile memory |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI673722B (en) * | 2017-05-30 | 2019-10-01 | 美商司固科技公司 | Data storage device with rewritable in-place memory |
| US10559376B2 (en) | 2017-05-30 | 2020-02-11 | Seagate Technology Llc | Data storage device with rewriteable in-place memory |
| CN107832018A (en) * | 2017-11-22 | 2018-03-23 | 深圳忆联信息系统有限公司 | A kind of RAID implementation and SSD |
| CN108647157B (en) * | 2018-03-14 | 2021-10-01 | 深圳忆联信息系统有限公司 | Mapping management method based on phase change memory and solid state disk |
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