CN220382087U - Chip passivation layer protection copper particle and semiconductor high-power device lamination - Google Patents
Chip passivation layer protection copper particle and semiconductor high-power device lamination Download PDFInfo
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- CN220382087U CN220382087U CN202321574392.3U CN202321574392U CN220382087U CN 220382087 U CN220382087 U CN 220382087U CN 202321574392 U CN202321574392 U CN 202321574392U CN 220382087 U CN220382087 U CN 220382087U
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- copper particle
- chip
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- particle body
- face
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 100
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 100
- 239000010949 copper Substances 0.000 title claims abstract description 100
- 239000002245 particle Substances 0.000 title claims abstract description 85
- 238000002161 passivation Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000003475 lamination Methods 0.000 title claims description 12
- 238000003466 welding Methods 0.000 claims abstract description 64
- 238000005476 soldering Methods 0.000 claims description 8
- 241000276425 Xiphophorus maculatus Species 0.000 claims description 2
- 239000008188 pellet Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 13
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000012858 packaging process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000008187 granular material Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 3
- 239000011324 bead Substances 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a chip passivation layer protection copper particle, which belongs to the technical field of semiconductors and comprises a columnar copper particle body, wherein the upper end face and the lower end face of the copper particle body are both welding surfaces, a circle of plate-shaped bulges are arranged on the side face of the copper particle body, and the thickness of the bulges is not more than one third of the thickness of the copper particle body. The chip is provided with a protection ring, the inside of the protection ring is provided with a welding area, and the welding area on the lower end face of the chip is welded with the welding face on the upper end of the copper particle body. Through bellied design, the copper grain body is transversely the same with the chip, has better locate function in the encapsulation in-process, can effectively reduce copper grain body off normal position and lead to the chip to become invalid when the welding, can solve the problem that conventional copper grain location offset leads to the product uniformity poor and the product stress increase that the slope leads to and become invalid.
Description
Technical Field
The utility model belongs to the technical field of semiconductors, and particularly relates to a chip passivation layer protection copper particle and a semiconductor high-power device lamination.
Background
The power semiconductor device is mainly applied to the field of electric energy/power processing as a core device, is mainly used for electric energy conversion and circuit control of electric equipment, and is especially a communication bridge between weak current control and strong current operation, and the power semiconductor device mainly has the functions of frequency conversion, voltage transformation, current transformation, power amplification and power management and plays a key role in normal operation of the equipment. Meanwhile, the power semiconductor device has a green energy-saving function, is widely applied to almost all electronic manufacturing industries, and is currently developing from the traditional industrial manufacturing and 4C industries to the fields of new energy, electric locomotives, smart grids and the like.
The chip passivation layer protection copper particle is usually used with the lamination cooperation of the chip, can effectively improve the heat dissipation function of the chip and increase chip life and fatigue resistance, and the design of the traditional chip passivation layer protection copper particle is usually two kinds: the first is that the lateral dimension of the chip passivation layer protection copper particle is the same as that of the chip, and the chip failure, yield loss, reliability abnormality and other problems caused by the overflow of solder to the protection ring position are very easy to occur in the design during welding; the second design is that the lateral dimension of the chip passivation layer protection copper particle is an inscribed dimension (a protection ring inner area), and the design can not realize the accurate positioning of the welding position of the chip passivation layer protection copper particle during packaging, and simultaneously sacrifices the heat dissipation function of the chip passivation layer protection copper particle. Therefore, a chip passivation layer needs to be designed for protecting copper particles and semiconductor high-power device lamination.
It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art.
Disclosure of Invention
The inventor discovers through research that the existing chip passivation layer can not give consideration to the accurate positioning and heat dissipation functions of the welding position when packaging copper particles.
In view of at least one of the above technical problems, the present disclosure provides a chip passivation layer for protecting copper particles and a lamination of a semiconductor high-power device, which comprises the following specific technical schemes:
the utility model provides a chip passivation layer protection copper grain, includes columnar copper grain body, the up end and the lower terminal surface of copper grain body are the welding face, the side round of copper grain body is equipped with platelike arch, bellied thickness is not more than copper grain body thickness's third.
In some embodiments of the disclosure, the welding face is planar.
In some embodiments of the present disclosure, at least one of the welding surfaces of the copper particle body is provided with a channel groove.
In some embodiments of the present disclosure, the copper particle body thickness is 0.3-1 mm, and the depth of the trench groove is no more than one tenth of the copper particle body thickness.
In some embodiments of the disclosure, the channel grooves are grid grooves uniformly distributed on the welding surface.
In some embodiments of the present disclosure, a distance between the welding surface of the upper end of the copper particle body and the upper end surface of the protrusion is not less than 0.05mm, and a distance between the welding surface of the lower end of the copper particle body and the lower end surface of the protrusion is not less than 0.05mm.
The utility model provides a high-power device lamination of semiconductor, includes the group of pieces, the group of pieces includes chip and foretell chip passivation layer protection copper granule, the chip border is equipped with the protection ring, the inside welding area that establishes of protection ring, through the welding area of terminal surface under the chip with the welding face welding of copper granule body upper end.
In some embodiments of the present disclosure, a plurality of the sheet sets are included in a stacked arrangement.
In some embodiments of the disclosure, the uppermost chip is soldered with one of the copper particle bodies through a soldering region of an upper end face thereof, the soldering region being soldered with a soldering face of a lower end face of the copper particle body.
In some embodiments of the present disclosure, the protrusion is congruent with the width of the guard ring, and the bonding surface is congruent with the bonding region shape.
Compared with the prior art, the utility model has the following beneficial effects:
through the design of the bulge, the copper particle body and the chip have the same transverse size, have a good positioning function in the packaging process, can effectively reduce the chip failure caused by the deviation of copper particles during welding, can solve the problems of poor product consistency caused by the deviation of the positioning of the conventional copper particle body and failure caused by the increase of product stress caused by the inclination, effectively improve the product performance, have high positioning accuracy, improve the production efficiency and reduce the pollution to products in the production process;
the contact between the special-shaped copper particle welding surface and the chip can be adjusted, and a safe space is properly reserved between the special-shaped copper particle welding surface and the chip welding area, the bump can avoid a chip protection ring, and the problems of chip failure, yield loss, reliability abnormality and the like caused by overflow of solder to the protection ring position in the packaging process are avoided;
through the design of the bulge, the packaging yield is improved, the bad production caused by tin beads/tin whiskers is reduced, and the effect on the bidirectional product is more obvious.
Drawings
FIG. 1 is a schematic side view of the copper pellet body of example 1 in the structure of the present utility model;
fig. 2 is a schematic side view of a semiconductor high power device stack of example 3 in accordance with the inventive arrangements;
FIG. 3 is a schematic perspective view of FIG. 2;
the reference numerals in the figures illustrate: 1. a copper particle body; 11. a protrusion; 2. a chip; 21. a protective ring; 3. and (5) welding the sheet.
Detailed Description
For a better understanding of the objects, structures and functions of the present utility model, reference should be made to the accompanying drawings in which embodiments of the utility model are shown, and in which it is apparent that some, but not all embodiments of the utility model are illustrated.
The component parts themselves are numbered herein only to distinguish between the stated objects and do not have any sequential or technical meaning. In this disclosure, the term "coupled" includes both direct and indirect, "as used herein, unless specifically indicated otherwise. In the description of the present application, it should be understood that the azimuth or positional relationship indicated by the azimuth terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the azimuth or positional relationship shown in the drawings, are for convenience of description only, and do not indicate or imply that the apparatus or unit referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present application.
As shown in fig. 1 to 3 of the drawings, a chip passivation layer protection copper particle is designed, and comprises a columnar copper particle body 1, wherein the upper end face and the lower end face of the copper particle body 1 are both welding surfaces, a circle of platy bulges 11 are arranged on the side face of the copper particle body 1, and the thickness of the bulges 11 is not more than one third of the thickness of the copper particle body 1.
Still design a high-power device lamination of semiconductor, including the group of pieces, the group of pieces include chip 2 with chip passivation layer protection copper granule, chip 2 border is equipped with guard ring 21, guard ring 21 inside is established as the welded zone, through the welded zone of the terminal surface under the chip 2 with the welding face welding of copper granule body 1 upper end.
Through the design of the bulge 11, the copper particle body 1 and the chip 2 have the same transverse appearance size, have a good positioning function in the packaging process, can effectively reduce the chip failure caused by the deviation of the copper particle body 1 during welding, can solve the problems of poor product consistency caused by the conventional copper particle positioning deviation and failure caused by the increase of product stress caused by inclination, effectively improve the product performance, have high positioning accuracy, improve the production efficiency and reduce the pollution caused by repeated touching of the product due to the positioning in the production process; the contact between the special-shaped copper particle welding surface and the chip can be adjusted, and a safe space is properly reserved between the special-shaped copper particle welding surface and the chip welding area, the protrusion 11 can avoid the protection ring 21 of the chip 2, and the problems of chip 2 failure, yield loss, abnormal reliability and the like caused by overflow of solder to the position of the protection ring 21 in the packaging process are avoided; through the design of the bulge 11, the packaging yield is improved, the bad generation caused by tin beads/tin whiskers is reduced, and the effect on the bidirectional product is more obvious.
In the above embodiments, three embodiments are listed to implement the above technical solutions:
as shown in fig. 1, a first embodiment discloses a chip passivation layer protection copper particle, which comprises a columnar copper particle body 1, wherein the upper end surface and the lower end surface of the copper particle body 1 are both welding surfaces, a circle of plate-shaped protrusions 11 are arranged on the side surface of the copper particle body 1, and the thickness of each protrusion 11 is not more than one third of the thickness of the copper particle body 1 so as to properly leave a safety space;
wherein the welding surface is a plane; the thickness of the copper particle body 1 is 1mm, the distance between the welding surface at the upper end of the copper particle body 1 and the upper end face of the bulge 11 is not less than 0.05mm, the distance between the welding surface at the lower end of the copper particle body 1 and the lower end face of the bulge 11 is not less than 0.05mm, the welding surface of the special-shaped copper particle is in contact with a chip, the welding surface of the special-shaped copper particle is adjustable and is matched with the weldable area of the chip, a safe space is properly reserved between the welding surface of the special-shaped copper particle and the weldable area of the chip, the bulge 11 can avoid the protection ring 21 of the chip 2, and the problems of chip 2 failure, yield loss, reliability abnormality and the like caused by overflow of welding materials to the position of the protection ring 21 in the packaging process are completely eradicated.
The chip 2 is provided with a protection ring 21 in a circumferential circle, a welding area is arranged inside the protection ring 21, and welding is completed by arranging a welding lug 3 and solder paste on a welding area of the lower end face of the chip 2 and a welding face of the upper end of the copper particle body 1
The width of the protrusion 11 is identical to that of the guard ring 21, and the shape of the welding surface is identical to that of the welding area, so that the edge of the copper particle body 1 is not retracted into the chip 2, and positioning is facilitated.
Through the design of the bulge 11, the copper particle body 1 and the chip 2 have the same transverse appearance size, have a good positioning function in the packaging process, can effectively reduce the chip failure caused by the deviation of the copper particle body 1 during welding, can solve the problems of poor product consistency caused by the conventional copper particle positioning deviation and failure caused by the increase of product stress caused by inclination, effectively improve the product performance, have high positioning accuracy, improve the production efficiency and reduce the pollution caused by repeated touching of the product due to the positioning in the production process; the contact between the special-shaped copper particle welding surface and the chip can be adjusted, and a safe space is properly reserved between the special-shaped copper particle welding surface and the chip welding area, the protrusion 11 can avoid the protection ring 21 of the chip 2, and the problems of chip 2 failure, yield loss, abnormal reliability and the like caused by overflow of solder to the position of the protection ring 21 in the packaging process are avoided; through the design of the bulge 11, the packaging yield is improved, the bad generation caused by tin beads/tin whiskers is reduced, and the effect on the bidirectional product is more obvious.
The second embodiment discloses a chip passivation layer protection copper particle, and the difference between this embodiment and the first embodiment is that at least one welding surface of the copper particle body 1 is provided with a channel groove, the channel groove is an annular groove, the thickness of the copper particle body 1 is 1mm, and the depth of the channel groove is 0.1mm, so as to strengthen the welding effect.
The first embodiment is different from the first embodiment in that the lamination comprises a plurality of laminated sheet groups, and the sizes of the sheet groups are consistent.
As shown in fig. 2 to fig. 3, a third embodiment discloses a chip passivation layer for protecting copper particles, and the difference between the present embodiment and the second embodiment is that the channel grooves are grid grooves uniformly distributed on the welding surface; the thickness of the copper particle body 1 is 0.6mm, and the depth of the channel groove is 0.01mm; to enhance the welding effect.
The difference between the embodiment and the second embodiment is that the uppermost chip 2 is welded with the copper particle body 1 through a welding area on the upper end surface of the chip, and the welding area is welded with a welding surface on the lower end surface of the copper particle body 1; through the design of similar sandwich structure, solve the technical difficulty of the high-power device lamination technology of semiconductor, it is higher to make encapsulation precision through copper granule body 1 and chip 2 join in marriage in the sandwich mode, and chip 2 welding area increases, and the heat dispersion is better, and product life and uniformity obtain further promotion.
It will be understood that the utility model has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the utility model. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the utility model without departing from the essential scope thereof. Therefore, it is intended that the utility model not be limited to the particular embodiment disclosed, but that the utility model will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. The utility model provides a chip passivation layer protection copper particle which characterized in that: the copper particle welding device comprises a columnar copper particle body (1), wherein the upper end face and the lower end face of the copper particle body (1) are both welding faces, a platy bulge (11) is arranged on one circle of the side face of the copper particle body (1), and the thickness of the bulge (11) is not more than one third of the thickness of the copper particle body (1).
2. The die passivation layer protective copper pellet of claim 1, wherein the bonding surface is planar.
3. Chip passivation layer protection copper particle according to claim 1, characterized in that at least one soldering surface of the copper particle body (1) is provided with a trench groove.
4. A chip passivation layer protection copper particle according to claim 3, characterized in that the thickness of the copper particle body (1) is 0.3-1 mm, and the depth of the channel groove is not more than one tenth of the thickness of the copper particle body (1).
5. The chip passivation layer protection copper particle of claim 4, wherein the trench grooves are grid grooves uniformly distributed on the soldering surface.
6. The chip passivation layer protection copper particle according to claim 1, wherein a distance between a welding surface of an upper end of the copper particle body (1) and an upper end surface of the bump (11) is not less than 0.05mm, and a distance between a welding surface of a lower end of the copper particle body (1) and a lower end surface of the bump (11) is not less than 0.05mm.
7. The high-power semiconductor device lamination is characterized by comprising a sheet group, wherein the sheet group comprises a chip (2) and the chip passivation layer for protecting copper particles according to any one of claims 1-6, a protection ring (21) is arranged on the periphery of the chip (2), a welding area is arranged inside the protection ring (21), and the welding area on the lower end face of the chip (2) is welded with the welding face on the upper end of the copper particle body (1).
8. The semiconductor high power device stack of claim 7, comprising a plurality of said die stacks stacked.
9. The semiconductor high-power device lamination according to claim 7 or 8, characterized in that the uppermost chip (2) is soldered with one copper particle body (1) through a soldering land of its upper end face, which soldering land is soldered with a soldering face of the lower end face of the copper particle body (1).
10. The semiconductor high power device laminate of claim 9, wherein the bump (11) conforms to the width of the guard ring (21), and the bonding surface is congruent with the bonding pad shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321574392.3U CN220382087U (en) | 2023-06-20 | 2023-06-20 | Chip passivation layer protection copper particle and semiconductor high-power device lamination |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321574392.3U CN220382087U (en) | 2023-06-20 | 2023-06-20 | Chip passivation layer protection copper particle and semiconductor high-power device lamination |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220382087U true CN220382087U (en) | 2024-01-23 |
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ID=89566379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321574392.3U Active CN220382087U (en) | 2023-06-20 | 2023-06-20 | Chip passivation layer protection copper particle and semiconductor high-power device lamination |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220382087U (en) |
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2023
- 2023-06-20 CN CN202321574392.3U patent/CN220382087U/en active Active
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