CN220367915U

CN220367915U - Substrate and packaging structure

Info

Publication number: CN220367915U
Application number: CN202321475761.3U
Authority: CN
Inventors: 吕展航; 王意坚; 葛婷婷
Original assignee: Smarter Microelectronics Shanghai Co Ltd
Current assignee: Smarter Microelectronics Shanghai Co Ltd
Priority date: 2023-06-09
Filing date: 2023-06-09
Publication date: 2024-01-19
Anticipated expiration: 2033-06-09

Abstract

The embodiment of the application provides a substrate and a packaging structure, wherein the substrate comprises: a substrate; a wiring layer on the substrate; the circuit layer comprises a circuit structure and a cutting structure, wherein the circuit structure is positioned in the packaging area, and the cutting structure is formed by cutting auxiliary cutting strips along cutting lines; wherein the auxiliary cutting strip is positioned in the cutting area and extends to the packaging area; the cutting area extends along the packaging area, a cutting channel is formed at the adjacent position of the packaging area and the cutting area, and the auxiliary cutting strip is positioned at the part of the cutting channel, which is discontinuous.

Description

Substrate and packaging structure

Technical Field

The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a substrate and a package structure.

Background

Conformal shielding (Conformal shielding) commonly used in electromagnetic interference (Electro Magnetic Interference, EMI) shielding can be implemented by electroplating, sputtering or spraying, and is widely used as a new electromagnetic interference shielding technology for electronic packages such as radio frequency and storage. The thin metal layer is formed on the surface of the package, so that the internal device is shielded from external interference, and the device and the circuit are shielded from external interference. In order to achieve a better shielding effect, a closed metal cover can be formed, copper needs to be paved on a cutting path when the packaging substrate is designed, exposed metal is ensured to be arranged on the side face of the packaging after cutting, and the shielding cover is formed through electroplating, sputtering or spraying and the like.

In the existing design and manufacturing technology of the EMI shielding substrate, when a single chip is cut by the packaging substrate, the metal copper has good ductility, so that the phenomenon of burrs is caused after cutting and the problem of layering of a metal layer is caused by pulling the copper layer.

Disclosure of Invention

The embodiment of the application provides a substrate and a packaging structure.

The technical scheme of the application is realized as follows:

in a first aspect, embodiments of the present application provide a substrate, the substrate including: a substrate; a wiring layer on the substrate; the circuit layer comprises a circuit structure and a cutting structure, wherein the circuit structure is positioned in the packaging area, and the cutting structure is formed by cutting auxiliary cutting strips along cutting lines; wherein the auxiliary cutting strip is positioned in the cutting area and extends to the packaging area; the cutting area extends along the packaging area, a cutting channel is formed at the adjacent position of the packaging area and the cutting area, and the auxiliary cutting strip is positioned at the part of the cutting channel, which is discontinuous.

In a second aspect, embodiments of the present application provide a package structure, including: a substrate; a circuit module disposed on the substrate; wherein the circuit module is electrically connected with the substrate.

In this embodiment of the application, supplementary cutting strip is located the part discontinuity of cutting way, so, on the one hand, can change the area of copper on the cutting way, so, can effectively improve the burr that cuts the copper and lead to the phenomenon of layering with pulling copper. In addition, the area of copper on the cutting path is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the aspects of the present application.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic implementation flow chart of a method for forming a substrate according to an embodiment of the present application;

fig. 2 is a schematic structural diagram illustrating a process of forming a substrate according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram II of a substrate forming process according to an embodiment of the present application;

fig. 4 is a schematic structural diagram III of a process of forming a substrate according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a forming process of a substrate according to an embodiment of the present application;

fig. 6 is a schematic diagram of a forming process of a substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram sixth illustrating a process of forming a substrate according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram seven of a substrate forming process according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram eight of a process of forming a substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram nine of a process of forming a substrate according to an embodiment of the present application;

fig. 11 is a schematic structural view of a forming process of a substrate according to an embodiment of the present application;

fig. 12 is a schematic diagram eleven of a structure of a substrate forming process according to an embodiment of the present application;

fig. 13 is a schematic diagram showing a formation process of a substrate according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram thirteenth illustrating a process of forming a substrate according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram fourteen of a substrate forming process according to an embodiment of the present disclosure;

fig. 16 is a schematic diagram fifteen of a forming process of a substrate according to an embodiment of the present application;

fig. 17 is a schematic structural diagram sixteen illustrating a process of forming a substrate according to an embodiment of the present disclosure;

fig. 18 is a schematic structural diagram seventeen of a process of forming a substrate according to an embodiment of the present disclosure;

fig. 19 is a schematic structural diagram eighteenth illustrating a process of forming a substrate according to an embodiment of the present disclosure;

fig. 20 is a schematic structural diagram nineteenth of a forming process of a substrate according to an embodiment of the present application;

fig. 21 is a schematic diagram twenty of a process of forming a substrate according to an embodiment of the present disclosure;

fig. 22 is a schematic implementation flow chart of a method for forming a package structure according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of a substrate according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

To facilitate an understanding of the embodiments of the present application, the following is a brief description of the related art referred to in the present application.

The conformal shielding is to completely integrate the shielding layer and the package together, the module has a shielding function, and after the chip is mounted on the substrate, no shielding cover is needed, so that no extra equipment space is occupied.

The electroplating process is to plate some metal surfaces with some other metal or alloy layers by means of electrolysis to form one metal film to the surface of the metal or other metal product to prevent oxidation, raise the wear resistance, conductivity, reflectivity, corrosion resistance, etc.

The sputtering process is to bombard the solid surface with particles (ions or neutral atoms, molecules) of a certain energy, so that the atoms or molecules near the solid surface obtain enough energy to finally escape from the solid surface.

The spraying process is a coating method in which spray gun or disk atomizer is used to disperse uniform and fine droplets by pressure or centrifugal force and apply the droplets to the surface of the object to be coated.

The technology of packaging substrates is divided into a core substrate (core) and a coreless substrate (coreless), and since the coreless substrate has a reduced electrical transmission path, the inductance of a power supply system loop can be reduced, the transmission characteristics, particularly the frequency characteristics, can be improved, and the higher integration level can be widely applied to radio frequency products. The novel coreless packaging substrate is manufactured into an interlayer conductive structure-copper column mainly through a bottom-up electrodeposition technology. It uses only an insulating layer and a copper layer, and then realizes high-density wiring by a half-additive lamination process.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

An embodiment of the present application provides a method for forming a substrate, referring to fig. 1, the method may include steps S101 to S103, where:

step S101, providing a substrate;

here, a nucleated substrate or a coreless substrate may be formed based on the base. The substrate of the substrate with the core is equivalent to that metal copper is deposited on the upper surface and the lower surface of one core at the same time, and the subsequent substrate forming process does not need to split plates; the base of the coreless substrate corresponds to a layer of metallic copper, and the substrate needs to be separated in the subsequent process of forming the substrate. The electrical transmission path of the coreless substrate is small, so that the inductance of a power system loop can be reduced, and the frequency characteristic is improved. In practice, the substrate may have two sides, namely a first side and a second side opposite the first side.

Step S102, forming a metal layer on the substrate; the metal layer comprises a packaging region and a cutting region extending along the packaging region, wherein cutting channels are formed at adjacent positions of the packaging region and the cutting region, and the cutting channels are used for cutting;

here, the metal layer may be formed on the first side and/or the second side of the substrate. The metal layer may include one layer, two layers or even multiple layers, and the number of layers of the metal layer is not limited in the embodiment of the present application.

Referring to fig. 2, a metal layer is illustrated as an example of a metal layer 101 formed by electroplating or depositing a conductive material on the first and second sides of the substrate 100.

In this embodiment of the present application, the metal layer mainly plays a role in conducting electricity, and the material of the metal layer may be conductive metal such as copper. In practice, the conductive material may be electroplated or deposited on the substrate by an electroplating or deposition process to form at least one metal layer.

Referring to fig. 3, the metal layer includes a package region 100a and a dicing region 100b extending along the package region 100a, and dicing streets 100c are formed adjacent to the package region 100a and the dicing region 100b, the dicing streets 100c being used for dicing. As can be seen from fig. 3, a dicing channel 100c extending in a horizontal or vertical direction is provided between the adjacent package regions 100a and dicing regions 100b, and a dicing channel 100c is provided at the junction of each dicing region 100b and the package region 100 a.

It should be noted that, the packaging area may be an area where a chip is subsequently mounted, the cutting area is an area where a plurality of packaging areas are connected, and in the subsequent process, a packaging structure is cut to remove the cutting area to obtain a plurality of packaging units with the packaging areas; the dicing lanes may also be referred to as dicing lines for dicing along the dicing lines to obtain a plurality of package units. Each cutting zone may be provided with one or two cutting lanes as desired.

Step S103, forming auxiliary cutting strips in the metal layer; wherein the auxiliary cutting strip is positioned in the cutting area and extends to the packaging area, and the part of the auxiliary cutting strip positioned in the cutting channel is discontinuous.

Referring to fig. 2, the metal layer 101 is etched to form auxiliary cutting bars 101a as shown in fig. 4, wherein the right drawing in fig. 4 is a partial top view of the left drawing. Referring to the right view of fig. 4, the auxiliary dicing bar 101a is located within the dicing area 100b, extends to the packaging area, and the portion of the auxiliary dicing bar 101a located in the dicing street 100c is discontinuous.

It should be noted that the partial discontinuity of the auxiliary cutting bar located in the cutting path means that the auxiliary cutting bar does not completely cover the cutting path, and exposes a portion of the cutting path. In practice, the auxiliary cutting bars can be saw-toothed, so that the area of cutting path metal such as copper can be reduced, and the phenomenon of layering caused by burrs and pulling copper caused by cutting copper can be effectively improved.

In some embodiments, the implementation of step S103 "forming auxiliary cutting bars in the metal layer" may include the following steps S1031 and S1032:

step S1031: forming a preset film layer on the metal layer;

referring to fig. 5, a polymer compound material is deposited on a metal layer 101 to form a predetermined film 102.

Here, the preset film layer may be a dry film of a polymer material, which can be polymerized to form a stable substance attached to the surface of the metal layer after irradiation of ultraviolet rays, thereby achieving the function of blocking electroplating and etching.

In some embodiments, three metal layers are used as an example, where a patterned pre-set film is formed on a substrate when a first metal layer is formed, a patterned pre-set film is formed on a first metal layer (i.e., a previous metal layer) when a second metal layer is formed, and a patterned pre-set film is formed on a second metal layer (i.e., a previous metal layer) when a third metal layer is formed. In the case where the metal layer includes other layers, similar to the above case, a description thereof will be omitted.

Step S1032: and etching the metal layer forming the preset film layer to form the auxiliary cutting strip.

Referring to fig. 5, the metal layer 101 may be etched using a dry etching process, a wet etching process, or a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP), and then the preset film layer 102 is removed to form the auxiliary dicing bars 101a as shown in fig. 4.

The etching gas used in the dry etching process may include at least one of: trifluoromethane (CHF) ₃ ) Carbon tetrafluoride (CF) ₄ ) Hydrogen bromide (HBr), chlorine (Cl) ₂ ). In other embodiments, the etching gas may also include other fluorocarbon-based gases, such as difluoromethane (CH) ₂ F ₂ ) Octafluoropropane (C) ₃ F ₈ ) Perfluorobutadiene (C) ₄ F ₆ ) Octafluorocyclobutane (C) ₄ F ₈ ) And octafluorocyclopentene (C) ₅ F ₈ ) One or more of them. The etching solution employed in the wet etching process may include a dilute hydrofluoric acid solution.

In some embodiments, the auxiliary cutting bar is a toothed structure.

In some embodiments, the tooth-like structures comprise triangles and/or rectangles.

Referring to the right view of fig. 4, the auxiliary cutting bars 101a are uniformly distributed in the cutting zone 100b in a triangular and rectangular tooth-like structure, and the shape of the auxiliary cutting bars of each layer is substantially the same. Here, the tooth-like structure of supplementary cutting strip can reduce the area of copper on the cutting path to can reduce the wearing and tearing of cutting stage property, extension cutting tool's life can also effectively improve the burr that cuts the copper and pull copper and lead to the problem of layering.

In the embodiment of the application, first, a substrate is provided; then, forming a metal layer on the substrate; the metal layer comprises a packaging region and a cutting region extending along the packaging region, wherein cutting channels are formed at adjacent positions of the packaging region and the cutting region, and the cutting channels are used for cutting; finally, forming auxiliary cutting strips in the metal layer; wherein the auxiliary cutting strip is positioned in the cutting area and extends to the packaging area, and the part of the auxiliary cutting strip positioned in the cutting channel is discontinuous. It can be seen that the auxiliary cutting bar is located in a partial discontinuity of the cutting path. It can be seen that the embodiment of the application changes the shape of the auxiliary cutting strip in the cutting area, so that the area of copper on the cutting channel is changed, and the phenomenon of layering caused by burrs and pulling copper brought by cutting copper can be effectively improved. In addition, the area of copper on the cutting path is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged. The embodiment of the application also has the advantages of no increase of production flow, no increase of cost, simpleness and effectiveness and the like.

In some embodiments, the method further comprises: and forming a circuit structure in the metal layer to form a circuit layer.

Referring to fig. 2, the metal layer 101 may be etched using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form a line structure 101b as shown in fig. 6 to form a line layer 11. The number and shape of the line structures 101b in the line layer 11 may be more than one, and the shape of the line structures 101b may be more than one. As can be seen from fig. 6, the surface of the wiring layer 11 has a plurality of different wiring structures 101b and a plurality of conductive vias 101c.

After the metal layer is etched to form the auxiliary cutting bars and the circuit structure, the remaining metal layer forms the circuit layer. That is, the circuit layer includes at least the auxiliary cutting bars and the circuit structure.

In some embodiments, the line structures are formed simultaneously with the auxiliary dicing bars; alternatively, the auxiliary dicing bars may be formed after the wiring structure is formed.

In the implementation process, the formation of the circuit structure and the auxiliary cutting strip can comprise the following two cases:

first case: after etching the metal layer, forming a circuit structure and auxiliary cutting strips at the same time;

second case: firstly, etching the metal layer to form a circuit structure, and then, etching the metal layer to form the circuit structure to form auxiliary cutting strips.

In some embodiments, the substrate includes two circuit layers thereon, and after forming the first circuit layer, the method further includes the following steps S201 and S202:

step S201, forming a first dielectric layer on the first circuit layer;

here, the wiring layer includes auxiliary dicing bars and wiring structures. Taking two circuit layers as an example, the first dielectric layer may be formed by depositing the material of the dielectric layer of the fiberglass cloth impregnated with the resin on the first circuit layer by any suitable deposition process (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.).

And step S202, forming a second circuit layer on the first dielectric layer.

Here, first, a metal layer may be formed by electroplating or depositing a conductive material on the first dielectric layer through an electroplating or deposition process; then, the metal layer is etched to form a circuit layer.

In some embodiments, after step S103 "forming the auxiliary cutting bar", the method further includes the following steps S301 and S302:

step S301, thinning the auxiliary cutting strip;

here, the auxiliary cutting bar may be etched by a dry etching process, a wet etching process, or a chemical mechanical polishing process to achieve thinning of the auxiliary cutting bar. Therefore, the thickness of the auxiliary cutting strip can be reduced, the copper content in the auxiliary cutting strip is reduced, and the phenomenon of layering caused by burrs from copper strip cutting and copper pulling can be further improved.

And step S302, filling a second dielectric layer on the thinned auxiliary cutting strip.

Here, filling the thinned auxiliary cutting strip with the second dielectric layer is to fill the thinned area with the second dielectric layer, and the material of the second dielectric layer may be glass fiber cloth impregnated with resin. In practice, the second dielectric layer may be formed by any suitable deposition process (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.).

In the implementation, the medium layers can be filled together at the positions of saw teeth and the like of the auxiliary cutting strips, so that the edge of the substrate can be a straight line, and the processing is convenient.

The dielectric layers in the same layer are formed together. That is, when implementing, the first circuit layer may be formed first, then the auxiliary cutting bar in the first circuit layer is thinned, and finally, the dielectric layer is formed on the thinned area and the first circuit layer, where the dielectric layer includes the first dielectric layer and the second dielectric layer.

The embodiment of the present application provides a method for forming a substrate, and the method for forming a substrate is described in detail below with reference to fig. 7 to 21:

referring to fig. 7, a substrate is provided; the substrate comprises a double-layer thin copper carrier (Double Thin copper Foil, DTF) 100, the first and second sides of the double-layer thin copper carrier (i.e. substrate) 100 each comprise a first copper foil layer 10 and a second copper foil layer 12 in sequence, and the second copper foil layer 12 is located on the surface of the first copper foil layer 10. In practice, the thickness of the first copper foil layer 10 may be greater than the thickness of the second copper foil layer 12, for example, the thickness of the first copper foil layer 10 may be 18 micrometers (μm) and the thickness of the second copper foil layer 12 may be 3 μm.

Referring to fig. 8, the surface of the second copper foil layer 12 is covered with a first dry film, and the first dry film is selectively exposed and developed to form a patterned first dry film 121, and a partial region of the second copper foil layer 12 is exposed at intervals; a metal is plated on the exposed area of the second copper foil layer 12 to form a first circuit layer 111.

Here, the patterned first dry film 121 is a predetermined film layer formed on the metal layer.

Referring to fig. 9, a second dry film is coated on the first circuit layer 111 and the patterned first dry film 121, and selectively exposed and developed; forming a patterned second dry film 411 and exposing a partial region of the first circuit layer 111 at intervals; an interconnect layer 311 is formed by electroplating metal on the exposed areas of the first wiring layer 111.

The patterned first dry film 121 and the patterned second dry film 411 are removed, and after the patterned first dry film 121 and the patterned second dry film 411 are removed, a structure as shown in fig. 10 is formed.

Referring to fig. 11, a dielectric material is deposited on the surface of the exposed second copper foil layer 12 to form a first dielectric layer 500, and a seed material is sputtered on the first dielectric layer 500 to form a first seed layer 600 as shown in fig. 12; wherein the sputtering seed material is titanium or copper.

Referring to fig. 13, a third dry film is coated on the first seed layer 600, and selectively exposed and developed; forming a patterned third dry film 511, and exposing a partial region of the first seed layer 600 at intervals; a second wiring layer 211 is formed by electroplating a metal on the exposed region of the first seed layer 600, wherein the first wiring layer 111 and the second wiring layer 211 are formed in the same method.

With continued reference to fig. 13, a protective film 700 is coated on the second wiring layer 211 and the patterned third dry film 511, and the first copper foil layer 10 is separated from the second copper foil layer 12 to obtain two identical substrates. Here, the protective film may be a protective dry film, and the protective film may protect the circuit layer during the process of dividing the board. When the board is split, the layering position is identified from one corner of the carrier plate by using the fish wire, the first copper foil layer 10 and the second copper foil layer 12 are separated at a constant speed by the force of the wire, and the effect that the board cannot warp can be achieved only by controlling the wire, the force and the direction.

With continued reference to fig. 13, the patterned third dry film 511 and the protective film 700 are removed.

Referring to fig. 14, the fourth dry film is covered on the exposed surfaces of the first seed layer 600, the second copper foil layer 12 and the second circuit layer 211, and is selectively exposed and developed to form a patterned fourth dry film 611, and the second copper foil layer 12 and a partial region of the second circuit layer 211 are exposed at intervals; metal is plated on the exposed areas of the second copper foil layer 12 and the second wiring layer 211, and the conductive posts 42 and 43 are formed at the same time.

Referring to fig. 14, after removing the patterned fourth dry film 611, the first seed layer 600 and the second copper foil layer 12 are etched, resulting in the structure shown in fig. 15; the shape and size of the etched first seed layer 600a are the same as those of the second circuit layer 211, and the shape and size of the etched second copper foil layer 12a are the same as those of the first circuit layer 111.

Referring to fig. 16, an insulating material is filled between the first line layer 111 and the second line layer 211 to form an insulating layer 800. The material of the insulating layer 800 may be the same as that of the first dielectric layer.

Referring to fig. 17, a seed material is sputtered on the insulating layer 800 to form a second seed layer 620; wherein the sputtering seed material is titanium or copper.

Referring to fig. 18, a fifth dry film is covered on the second seed layer 620, and selectively exposed and developed; forming a patterned fifth dry film 711 and exposing a partial region of the second seed layer 620 at intervals; a third wiring layer 410 as shown in fig. 19 is formed by electroplating metal on the exposed area of the second seed layer 620.

Referring to fig. 19, after removing the patterned fifth dry film 711, the second seed layer 620 is etched, forming an etched second seed layer 621 as shown in fig. 20.

Referring to fig. 21, an ink layer 900 is selectively covered on the third line layer 410, and a region not covered with the ink layer is surface-treated to form a surface-treated layer 911. In implementation, an ink layer 900 is formed in the gap of the third circuit layer 410 at the top layer, where the ink layer may be a Solder Mask (SM) layer, and the Solder Mask may cover all the places where soldering is not needed, protect the circuit, and prevent tin connection during soldering; in addition, the solder resist ink has a leveling effect. Forming a surface treatment layer 911 on the area of the topmost third circuit layer 410, which is not covered by the ink layer, by surface treatment; wherein, the surface treatment is carried out on the topmost circuit layer by adopting chemical nickel plating palladium immersion gold (Electroless Nickel Electroless Palladium Immersion Gold, ENEPIG), electro-plating gold, nickel plating gold, chemical nickel immersion gold or tinning, so that the surface with excellent and high reliability can be obtained.

Note that fig. 16 to 21 do not show the etched second copper foil layer 12a between the conductive post 43 and the first wiring layer 111. In practice, the etched second copper foil layer 12a may be included between the conductive post 43 and the first circuit layer 111.

An embodiment of the present application provides a method for forming a package structure, referring to fig. 22, the method includes the following steps S2201 and S2202:

step S2201, providing a substrate;

wherein the substrate is formed by the method in the above embodiments;

and step S2202, arranging a chip on the surface of the packaging area of the substrate, wherein the chip is electrically connected with the substrate.

Here, the chip may be an integrated circuit chip, such as a NAND Flash Memory chip, a nors Flash chip, a dynamic random access Memory (Dynamic Random Access Memory, DRAM) chip, a static random access Memory (Static Random Access Memory, SRAM) chip, a Phase-Change Memory (PCM) chip, a ferroelectric Memory chip, a magneto-resistive Memory chip, or a resistive Memory chip.

In some embodiments, the size of the package regions is pre-designed, and one package region may be provided with 1, 2, or more chips, i.e., one package structure may include 1, 2, or more chips. The plurality of chips may be disposed on the surface of the substrate package region in a direction perpendicular to the thickness direction of the substrate, or sequentially disposed on the surface of the substrate.

In the embodiment of the application, the chip may be obtained through the following steps:

1. attaching a film (pointing) on the front surface of the wafer for protecting a circuit formed on the surface of the wafer;

2. grinding (Wafer backgriding) the back of the wafer to a suitable thickness;

3. a die bonding (mounting), specifically, a wafer is attached to a dicing saw;

4. cutting a wafer into small Die to obtain chips;

5. and (5) visual inspection of the chip, and removing the chip with the appearance defect.

In this embodiment, the process of disposing the chip on the surface of the package region of the substrate may include the following steps:

1. adopting surface mounting technology (Surface Mounted Technology, SMT) to carry out the mounting;

2. flip chip Attach (flip chip Attach); specifically, dipping a chip in soldering flux, and performing flip-chip mounting;

3. reflow (Reflow) to melt the solder balls of the flip chip and firmly bond the solder balls with the substrate pads;

4. defluxing (Delete Flux) because Flux residue can affect subsequent bondability with the molding compound;

5. an optical automatic inspection (Automatically Optical Inspection, AOI) specifically, a method of inspecting an inner layer line for short-circuit or open-circuit residual copper by irradiating the substrate with a halogen lamp;

6. plasma cleaning (Plasma) can effectively remove contaminants that may be present on the substrate surface;

7. pre-baking (Prebake) the substrate so that the heated substrate can be better combined with a subsequent plastic package material;

8. plastic packaging (Molding), specifically, plastic packaging the substrate by using a plastic packaging material;

9. solidifying (Cure) to make the plastic package material reach a certain hardness, so that the tin ball of the flip chip is melted and firmly welded with the bonding pad of the substrate;

10. printing (Marking), specifically printing production lot, name, date, etc. on the substrate surface.

In some embodiments, the method of forming a package structure may further include step S2203 and step S2204, wherein:

step S2203, cutting the substrate along the scribe line to obtain a packaging unit;

in step S2204, a shielding layer covering the encapsulation unit is formed through an electroplating, sputtering or spraying process.

The material of the shielding layer can be conductive rubber or conductive silica gel, wherein the conductive rubber is a rubber strip containing metal filler, has high conductivity, electromagnetic shielding, moisture resistance, sealing and other performances, and uniformly distributes conductive particles such as silver plating, aluminum plating, silver plating and the like in the silicon rubber, and enables the conductive particles to be contacted under the action of pressure so as to achieve good conductivity; the conductive silica gel is a pasty material, has good electrolytic corrosion resistance and shielding effectiveness, and is more suitable for being used in severe environments such as long-term heat, cold, humidity, ultraviolet rays, ozone and the like.

In the embodiment of the application, the qualified packaging unit with the shielding layer can be obtained through the following steps:

1. cutting the substrate along the cutting path by using a cutting technology (Saw) to obtain independent packaging units;

2. electromagnetic interference, specifically, forming a shielding layer covering the packaging unit through electroplating, sputtering or spraying technology;

3. a quality control Gate (QC Gate), specifically for checking the quality of each package unit;

4. final visual inspection (Finished Visual Inspection, FVI), specifically visual inspection of the substrate using a magnifying glass;

5. and testing (Test), specifically, conducting circuit conduction inspection on the substrate through a testing jig.

Embodiments of the present application provide a substrate, referring to fig. 3, fig. 4 and fig. 23 simultaneously, the substrate includes: a substrate 100; a wiring layer 11 on the substrate 100; the circuit layer 11 includes a circuit structure 101b located in the package region 100a and a cutting structure 100d, the cutting structure 100d being formed by cutting the auxiliary cutting bar 101a along the dicing street 100 c; wherein the auxiliary dicing bar 101a is located in the dicing area 100b and extends to the packaging area 100a; the dicing area 100b extends along the packaging area 100a, a dicing channel 100c is formed adjacent to the packaging area 100a and the dicing area 100b, and the portion of the auxiliary dicing bar 101a located in the dicing channel 100c is discontinuous.

In this embodiment, the auxiliary cutting bar is located at a part of the cutting path, where the part is discontinuous, and the auxiliary cutting bar located on the cutting area is in a tooth structure. Therefore, on one hand, the area of copper on the cutting path can be changed, so that the abrasion of cutting props is reduced, and the service life of the cutting tool is prolonged; on the other hand, the problem of delamination caused by burrs and pulling copper caused by copper cutting can be effectively solved.

In some embodiments, referring to fig. 23, the cutting structure 100d is a tooth structure comprising a recess 100e.

In some embodiments, the substrate further comprises: and the first dielectric layer is arranged on the circuit layer.

In some embodiments, the circuit layers 11 are multiple layers, and referring to fig. 23, at least one of the circuit layers 11 has a dicing structure 100d; the depressions 100e of the circuit layer 11 of any two layers of the circuit layers 11 are staggered or aligned. Under the condition that the depressions of any two layers of the multi-layer circuit layers are aligned, the problems of burrs or layering and the like on the side face of the substrate can be reduced.

In some embodiments, a thickness of the wire structure located within the encapsulation region is greater than a thickness of the dicing structure. The substrate further includes: a second dielectric layer on the cutting structure; the top surface of the second dielectric layer is flush with the top surface of the line structure.

Here, the thickness of the circuit structure is greater than that of the cutting structure, and the shape of the auxiliary cutting strip in the cutting area is changed, so that the area of copper on the cutting channel is changed, and the phenomenon that burrs brought by cutting copper and copper is pulled to cause layering can be effectively improved. In addition, the area of copper on the cutting path is reduced, so that the abrasion of cutting props can be reduced, and the service life of the cutting tool is prolonged. In implementation, the thinned auxiliary cutting strips are filled with a second dielectric layer, so that the top surface of the second dielectric layer is flush with the top surface of the circuit structure.

In some embodiments, the substrate further comprises: and the third dielectric layer is filled in the concave. Thus, the edge of the substrate can be straight, and the processing is convenient.

In some embodiments, referring to fig. 20, the substrate further comprises: an interconnect layer 311 connecting adjacent two of the wiring layers (e.g., the first wiring layer 111 and the second wiring layer 211).

The embodiment of the application provides a packaging structure, which comprises: a substrate, which may be formed by the method in the above embodiment; a circuit module disposed on the substrate; wherein the circuit module is electrically connected with the substrate.

Here, the circuit module includes a chip.

In some embodiments, the structure further comprises: a fourth dielectric layer wrapping the circuit module and covering the surface of the substrate; and the shielding layer wraps the fourth dielectric layer and the side wall of the substrate and is electrically connected with the exposed part of the circuit layer.

In the embodiment of the application, the substrate is formed by adopting the provided base, so that on one hand, burrs from copper strips can be cut and layering caused by copper pulling can be improved when a single packaging unit is formed by cutting, and the effect of the shielding layer can be improved; on the other hand, the abrasion of the cutting prop can be reduced, and the service life of the cutting tool is prolonged.

In several embodiments provided herein, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of the units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Features disclosed in several method or structural embodiments provided in the present application may be combined arbitrarily without any conflict to obtain new method embodiments or structural embodiments.

The foregoing is merely some implementations of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any person skilled in the art may easily think about changes or substitutions within the technical scope of the embodiments of the present application, and the changes or substitutions are intended to be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. A substrate, the substrate comprising:

a substrate;

a wiring layer on the substrate; the circuit layer comprises a circuit structure and a cutting structure, wherein the circuit structure is positioned in the packaging area, and the cutting structure is formed by cutting auxiliary cutting strips along cutting lines;

wherein the auxiliary cutting strip is positioned in the cutting area and extends to the packaging area; the cutting area extends along the packaging area, a cutting channel is formed at the adjacent position of the packaging area and the cutting area, and the auxiliary cutting strip is positioned at the part of the cutting channel, which is discontinuous.

2. The substrate of claim 1, wherein the cutting structures are tooth structures.

3. The substrate according to claim 2, wherein the teeth comprise triangular and/or rectangular shapes.

4. A substrate according to any one of claims 1 to 3, further comprising:

and the first dielectric layer is arranged on the circuit layer.

5. The substrate of claim 4, wherein the wiring layers are multi-layered, at least one of the wiring layers having a dicing structure; the circuit layers are arranged in a staggered manner or aligned manner, wherein the depressions of any two layers of the circuit layers are arranged in a staggered manner.

6. A substrate according to any one of claims 1 to 3, wherein the thickness of the wiring structure located within the encapsulation area is greater than the thickness of the dicing structure;

the substrate further includes: a second dielectric layer on the cutting structure; the top surface of the second dielectric layer is flush with the top surface of the line structure.

7. The substrate of claim 5, further comprising: and the third dielectric layer is filled in the concave.

8. The substrate of claim 5, further comprising: and the interconnection layer is used for connecting the two adjacent circuit layers.

9. A package structure, the package structure comprising:

the substrate as claimed in any one of claims 1 to 8;

a circuit module disposed on the substrate; wherein the circuit module is electrically connected with the substrate.

10. The structure of claim 9, wherein the structure further comprises:

a fourth dielectric layer wrapping the circuit module and covering the surface of the substrate;

and the shielding layer wraps the fourth dielectric layer and the side wall of the substrate and is electrically connected with the exposed part of the circuit layer.