CN220207708U - Synthesizer of ADC test system signal source - Google Patents

Abstract

The utility model provides a synthesizer of ADC test system signal source, comprising: the MCU processor is used for receiving the waveform quantized data issued by the PC and transferring the waveform quantized data into the SDRAM; the DDS signal synthesizer is used for directly synthesizing the digital signals of the signal source, accumulating the phase increment by taking the frequency control word K as a step according to different frequency requirements, and reading waveform data in the SDRAM by taking the accumulated phase value as an address code through the MCU; the signal amplifying and conditioning module amplifies and filters the signal output by the DDS signal synthesizer to convert the signal into a waveform signal meeting the ADC test requirement; the DDS signal synthesizer is respectively connected with the MCU processor and the signal amplifying and conditioning module, and the DDS signal synthesizer is adopted to realize the output of a high-precision signal source, so that the problem that expensive high-precision signal source equipment is required to be purchased outsourced in a multichannel high-precision ADC test system is avoided.

Description

Synthesizer of ADC test system signal source

Technical Field

The utility model relates to the technical field of waveform signal generators, in particular to a synthesizer of an ADC test system signal source.

Background

Currently, a waveform generator is an analog signal generator, and when hardware is debugged, signals are often required to be added to observe whether a circuit works normally. For high-precision analog-to-digital converter testing, the "purity" of an input signal affects the performance of digital output, namely, coupling noise in the input signal is converted into digital noise of the output signal, if the input signal has too much noise and distortion, the actual performance of an ADC is covered by testing conditions, and a signal source of the existing ADC testing system is a "function generator", which has the defect that the precision of an output waveform signal is lower, the requirement of the precision of a multichannel high-precision ADC testing system cannot be met, or special testing equipment with high precision is required to be purchased at high price, so that the testing cost is increased.

Disclosure of Invention

The utility model provides a synthesizer of an ADC test system signal source, which is used for solving the problem of low accuracy of waveform signals output by the prior ADC test system signal source device.

The specific scheme is as follows:

a synthesizer for an ADC test system signal source, comprising:

SDRAM, synchronous dynamic random access memory;

the MCU processor is used for receiving the waveform quantized data and storing the waveform quantized data into the SDRAM;

the DDS signal synthesizer is used for directly synthesizing the digital signals of the signal source, accumulating the phase increment by taking the frequency control word K as a step according to different frequency requirements, and reading waveform data stored in the SDRAM by taking the accumulated phase value as an address code through the MCU processor;

the signal amplifying and conditioning module is connected with the DDS signal synthesizer and is used for converting the signal output by the DDS signal synthesizer into a waveform signal meeting the ADC test requirement through amplifying and filtering;

the control module is used for receiving the data of the MCU processor and controlling the DDS signal synthesizer to output waveform data;

the control module, the DDS signal synthesizer and the SDRAM are respectively connected with the MCU processor.

Preferably, the control module comprises an N-bit phase accumulator, a sine lookup table ROM, a digital-to-analog converter DAC and a low pass filter LPF which are connected in sequence;

the N-bit phase accumulator is connected with the MCU processor.

Preferably, the output end of the MCU processor is also provided with a system clock FCLK and an amplitude control DAC;

the input end of the system clock FCLK is connected with the MCU processor, and the output end of the system clock FCLK is respectively connected with the N-bit phase accumulator, the sine lookup table ROM and the digital-to-analog converter DAC;

the amplitude control DAC is respectively connected with the MCU processor and the digital-to-analog converter DAC.

Preferably, the amplitude control DAC is a 12-bit DAC cell having a latch function.

Preferably, the system clock FCLK is a high-stability crystal oscillator.

Preferably, the number of bits S of the discretized waveform signal output by the sine lookup table ROM adopts a linear interpolation method.

Preferably, the number of bits truncated by the N-bit phase accumulator is equal to the difference between the number of N-bit phase accumulator bits and the number of bits the N-bit phase accumulator actually addresses the sine lookup table ROM.

Preferably, the system also comprises a display and a PC;

the display and the PC are respectively connected with the MCU processor;

the MCU processor receives waveform quantized data issued by the PC and transfers the waveform quantized data to the SDRAM.

Compared with the prior art, the beneficial effect of this application lies in:

the DDS signal synthesizer is adopted to realize the output of the high-precision signal source, so that the problem that expensive high-precision signal source equipment is required to be purchased in a multi-channel high-precision ADC test system is avoided;

according to the method, the amplitude control DAC module is additionally arranged in the DDS signal synthesizer, so that the amplitude precision of the output waveform signal is improved by more than 10 times; the number of bits of the sine signals output by the sine lookup table ROM adopts a linear interpolation method, so that the output precision of the waveform generator is improved by more than two times, and the method can be suitable for higher test requirements.

Drawings

The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the embodiments of the utility model, serve to explain the utility model. In the drawings:

FIG. 1 is a schematic diagram of a synthesizing device of an ADC test system signal source according to an embodiment of the present utility model;

fig. 2 is a schematic diagram of DDS signal processing in a synthesizer of an ADC test system signal source according to an embodiment of the utility model;

FIG. 3 is a waveform diagram of an output signal of a synthesizing device of an ADC test system signal source according to an embodiment of the present utility model;

the system comprises a 1-signal amplifying and conditioning module, a 2-DDS signal synthesizer, a 3-MCU processor, a 4-PC, a 5-display, a 6-SDRAM and a 7-control module.

Detailed Description

The preferred embodiments of the present utility model will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present utility model only, and are not intended to limit the present utility model.

A synthesizer for signal sources of an ADC test system according to fig. 1-3, comprising:

SDRAM6, synchronous dynamic random access memory;

the MCU processor 3 is used for receiving the waveform quantized data and storing the waveform quantized data into the SDRAM6;

the DDS signal synthesizer 2 is used for directly synthesizing the digital signals of the signal sources, accumulating the phase increment by taking the frequency control word K as a step according to different frequency requirements, and reading waveform data stored in the SDRAM6 by taking the accumulated phase value as an address code through the MCU processor 3;

the signal amplifying and conditioning module 1 is connected with the DDS signal synthesizer 2, and amplifies and filters the signal output by the DDS signal synthesizer 2 to convert the signal into a waveform signal meeting the ADC test requirement;

the control module 7 is used for receiving the data of the MCU processor 3 and controlling the DDS signal synthesizer 2 to output waveform data;

the control module 7, the DDS signal synthesizer 2 and the SDRAM6 are respectively connected with the MCU processor 3.

Further, the control module 7 includes an N-bit phase accumulator, a sine lookup table ROM, a digital-to-analog converter DAC, and a low pass filter LPF, which are sequentially connected;

the N-bit phase accumulator is connected with the MCU processor 3.

Further, the output end of the MCU processor 3 is also provided with a system clock FCLK and an amplitude control DAC;

the input end of the system clock FCLK is connected with the MCU processor 3, and the output end of the system clock FCLK is respectively connected with the N-bit phase accumulator, the sine lookup table ROM and the digital-to-analog converter DAC;

the amplitude control DAC is respectively connected with the MCU processor 3 and the digital-analog converter DAC.

Further, the amplitude control DAC is a 12-bit DAC unit with a latch function.

Further, the system clock FCLK is a high-stability crystal oscillator.

Further, the bit number S of the discretization waveform signal output by the sine lookup table ROM adopts a linear interpolation method.

Further, the number of bits truncated by the N-bit phase accumulator is equal to the difference between the number of N-bit phase accumulator bits and the number of bits the N-bit phase accumulator actually addresses the sine lookup table ROM.

Further, the device also comprises a display 5 and a PC 4;

the display 5 and the PC 4 are respectively connected with the MCU processor 3;

the MCU processor 3 receives the waveform quantized data issued by the PC 4 and transfers the waveform quantized data to the SDRAM6.

It should be noted that:

in the present application:

the PC 4 issues waveform quantized data.

The MCU processor 3 is mainly used for receiving waveform quantized data issued by the PC, transferring the waveform quantized data into the SDRAM6, and controlling the working state and the operation parameters of the DDS signal synthesizer at the same time so as to output waveforms required by testing.

The key is used for setting parameters of the output waveform signals.

The LCD display 5 displays the output waveform parameters.

The SARAM6 is mainly used for storing waveform quantization data.

The control module 7 mainly controls the DDS signal synthesizer, wherein the amplitude control DAC receives the control instruction of the MCU processor 3 and outputs an amplitude adjustable signal within the range of 0V to +/-10V, the output waveform resolution can reach 24 bits, and the high-precision requirement of ADC test is met.

The signal amplification and conditioning module 1 performs shaping processing on the DDS output waveform signal.

Aiming at the problem that high-precision ADC test does not have a high-precision signal source, the application provides a device for synthesizing a high-precision digital signal source, as shown in figure 1, a DDS signal synthesizer 2 is adopted as the signal source, and firstly, an MCU processor 3 reads waveform amplitude values stored in an SDRAM6; according to different frequency requirements, accumulating phase increment in an N-phase accumulator by taking a frequency control word K as a step, reading waveform phase data stored in a ROM by taking an accumulated phase value as an address code, filtering by a digital-to-analog converter DAC and an amplitude control DAC, finally obtaining a required waveform by filtering by a low pass filter LPF, and finally inputting the required waveform into a signal amplifying and conditioning module 1 by a micro control unit MCU, and converting the required waveform into a standard signal which can be identified by ADC test equipment by the signal amplifying and conditioning module 1.

The basic principle of the DDS synthesizer is that a waveform function-phase data table is put in a high-speed memory, read data is sent to a high-speed DAC to generate sine waves through table lookup operation, and the designed programmable DDS system principle is shown in figure 2.

In fig. 2:

"N" in an N-bit phase accumulator refers to the number of phase accumulator bits;

m: the phase accumulator actually addresses the sine look-up table ROM for bits;

s: the sine lookup table ROM outputs waveform signals or discretized digits, wherein S adopts a linear interpolation method, so that the output precision of a waveform generator is improved by more than two times, and the test requirement of higher precision can be met;

amplitude control DAC: the high-speed 12-bit DAC with the latching function is adopted, so that the amplitude precision of the output waveform signal is improved by more than 10 times.

Number of bits: the number of bits truncated by the phase accumulator satisfies the number of bits=n-M.

In one embodiment of the present application, the DDS signal synthesizer is a programmable DDS system, where the DDS system is composed of a frequency control word, an N-bit phase accumulator, a sine lookup table ROM, a digital-to-analog converter DAC, an amplitude control DAC, and a low pass filter LPF, where the model of the amplitude control DAC is: DAC1210; the system clock FCLK is a crystal oscillator with high stability (40 mhZ specification/model, 5 ppm/DEG C active crystal oscillator), and the output of the system clock FCLK is used for synchronizing the work of each component part of the DDS; the core of DDS system is N-bit phase accumulator, which is composed of N-bit adder and N-bit phase register, and is similar to a simple calculator, the output of phase register is increased by one step phase increment value every clock pulse, adder adds the frequency control data and the accumulated phase data output by accumulator register, and the added result is sent to the data input end of accumulator register. The phase accumulator enters linear phase accumulation, and generates a count overflow when the phase accumulator accumulates to a full range, and the overflow frequency is the output frequency of the DDS. The sine lookup table ROM is a programmable read-only memory (PROM) and stores sampling code values of a periodic sine signal with the phase as an address, and the sampling code values comprise digital amplitude information of a periodic sine wave, and each address corresponds to a phase point in the range of 0-360 degrees in the sine wave. The output of the phase register is added with the phase control word, the obtained data is used as an address to address a sine lookup table ROM, the sine lookup table ROM maps the input address phase information into sine wave amplitude signals, and the digital-to-analog converter DAC is driven to output analog signals. The low pass filter LPF smoothes and filters out unwanted sampled components in order to output a spectrally pure sine wave signal.

2. Parameter calculation in DDS Signal synthesizer 2

For a 2N phase accumulator with a counting capacity and a sine wave waveform memory with M phase sampling points, if the frequency control word is K, the output signal frequency is f o, the reference clock frequency is f c, the frequency of the output signal of the DDS system is

f o = kfc/2N (1)

The frequency resolution of the output signal frequency is

Δfmin=fc/2N (formula 2)

From the Nyquist sampling theorem, the maximum frequency of the DDS output is

fmax=fc/2 (formula 3)

The frequency control word can be deduced from the above formula:

k= f o ×2N/fc (formula 4)

When the external reference clock frequency is 50MHz and the output frequency is 1MHz, the system clock is subjected to frequency multiplication by 6 to change f c into 300MHz, so that the control frequency word K=248/300 required to be set of the DDS can be calculated by using the formula.

In one embodiment of the application the DDS signal synthesizer 2 employs programmable direct digital synthesis (Direct Digital Frequency Synthesizer, DDS or DDFS for short). In the application, the DDS signal synthesizer has the advantages of wide relative bandwidth, extremely short frequency conversion time (less than 20 microseconds), high frequency resolution, convenient integration of a full-digital structure, continuous output phase, program control of frequency, phase and amplitude, and capability of completely meeting the requirement of ADC test equipment on the input signal precision. Meanwhile, the DDS operation speed is high, and the signal generator with the advantage design of strong system integration level has higher speed and simpler and more convenient realization than the prior digital signal generator.

The indexes (parameters) required for the ADC test are: bandwidth 200KHZ, resolution 16bit, single channel. The signal source synthesizing device can output indexes (parameters) as follows: the bandwidth is more than 800KHZ, the resolution is 24bit, the channel is two channels, and the maximum amplitude (absolute value) of the output waveform signal is 20V.

In the industry, signal sources for ADC testing often use signal generators (PSGs), where the bandwidth of the signal generator is below 200KHZ and the resolution is not greater than 12 bits (12 bits), so that the requirements for high-precision ADC testing cannot be met, and for additional high-precision devices, i.e., signal source devices with bandwidths greater than 200KHZ and resolutions greater than 16 bits (16 bits), the cost is increased due to the high price.

The waveform output amplitude of the signal source synthesized by the device is shown in table 1,

table 1 waveform output amplitude table

The waveform output by the signal source synthesized by the device is shown in the figure 3, the abscissa in the figure 3 represents the phase, the ordinate represents the amplitude, the maximum amplitude absolute value of the output waveform is 20V, the output of an amplitude control DAC can be controlled to be adjustable within the range of 0 to +/-10V through MCU software according to the test requirement, the waveform resolution can reach 24 bits, the high-precision requirement of ADC test is met far, and the device is adopted without adding high-precision signal source equipment.

The utility model is characterized in that the hardware connection relation of each module, unit and device, the change of the installation position of each hardware and the like, and the special connection relation and corresponding space relation are formed, when an application specific integrated circuit is adopted, the special connection relation and corresponding space relation can be realized without auxiliary software, even if corresponding software is needed in specific application, the special connection relation and the corresponding space relation are only used as the utility model to be matched and coordinated with other parts in specific application scenes so as to better realize the function of the utility model in application, the utility model is irrelevant to the utility model, meanwhile, if the traditional chip matched software is adopted to work, the used software and processing method are the traditional software and the method, the realized utility model effect and destination are realized by the utility model is not dependent on the software, but the realized by the improvement of the hardware structure, the realized utility model effect and the realized object are not dependent on the software, the utility model is realized by the improvement of the hardware structure, and the scope of the protection claimed by the utility model is not related to the software itself, but only the connection relation and the relative space relation of each part.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the spirit or scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (6)

1. A synthesizer of an ADC test system signal source, comprising:

SDRAM (6), synchronous dynamic random access memory;

the MCU processor (3) is used for receiving the waveform quantized data and storing the waveform quantized data into the SDRAM (6);

the DDS signal synthesizer (2) is used for directly synthesizing the digital signals of the signal source, accumulating the phase increment by taking the frequency control word K as a step according to different frequency requirements, and reading waveform data stored in the SDRAM (6) by taking the accumulated phase value as an address code through the MCU processor (3);

the signal amplifying and conditioning module (1) is connected with the DDS signal synthesizer (2) and is used for converting signals output by the DDS signal synthesizer (2) into waveform signals meeting the ADC test requirements through amplifying and filtering;

the control module (7) is used for receiving the data of the MCU processor (3) and controlling the DDS signal synthesizer (2) to output waveform data;

the control module (7), the DDS signal synthesizer (2) and the SDRAM (6) are respectively connected with the MCU processor (3).

2. The device for synthesizing the signal source of the ADC test system according to claim 1, wherein the control module (7) comprises an N-bit phase accumulator, a sine lookup table ROM, a digital-to-analog converter DAC and a low pass filter LPF, which are sequentially connected;

the N-bit phase accumulator is connected with the MCU processor (3).

3. The device for synthesizing the signal source of the ADC test system according to claim 2, wherein the output end of the MCU processor (3) is further provided with a system clock FCLK and an amplitude control DAC;

the input end of the system clock FCLK is connected with the MCU processor (3), and the output end of the system clock FCLK is respectively connected with the N-bit phase accumulator, the sine lookup table ROM and the digital-to-analog converter DAC;

the amplitude control DAC is respectively connected with the MCU processor (3) and the digital-analog converter DAC.

4. A synthesis apparatus for an ADC test system signal source according to claim 3, wherein said amplitude control DAC is a 12-bit DAC cell having a latch function.

5. A synthesizing apparatus of an ADC test system signal source according to claim 3, wherein said system clock FCLK is a high stability crystal oscillator.

6. The synthesizer of the signal source of the ADC test system according to claim 1, further comprising a display (5) and a PC (4);

the display (5) and the PC (4) are respectively connected with the MCU processor (3);

the MCU processor (3) receives waveform quantized data issued by the PC (4) and stores the waveform quantized data into the SDRAM (6).