CN220188973U - High-speed collection system of pcie - Google Patents

Abstract

The utility model belongs to the technical field of computers, in particular to a PCIE high-speed acquisition system, which comprises an analog front-end circuit, a high-speed signal acquisition and signal processing module, a PCIE backboard, computer control software, an AC-DC power module and a structural member, wherein an external power supply of the system is 220V, and the system provides energy for a whole machine; the analog front-end circuit power supply network further processes the direct current power supply provided by the AC-DC power supply module and outputs 12V, 5V, 3.3V, 1.8V and other power supplies; the utility model integrates the technologies of high-speed parallel interface communication, signal processing, clock synchronization, PCIE system structure and the like into a whole, has 12 signal input channels, can perform various signal data acquisition, and can be widely applied to the fields of automatic test systems, signal measurement display and the like.

Description

High-speed collection system of pcie

Technical Field

The utility model belongs to the technical field of computers, and particularly relates to a pcie high-speed acquisition system.

Background

PCI-Express is a high-speed serial computer expansion bus standard, and is originally named as '3 GIO', proposed by Intel in 2001, and aims to replace the old PCI, PCI-X and AGP bus standards, PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, connected devices allocate single-shared channel bandwidth, do not share bus bandwidth, mainly support the functions of active power management, error reporting, end-to-end reliability transmission, hot plug, quality of service (QOS) and the like, and has the main advantages of high data transmission rate and considerable development potential.

Based on the above situation, we propose a new PCIE high-speed acquisition system, which integrates the technologies of high-speed parallel interface communication, signal processing, clock synchronization, PCIE architecture and the like, has 12 signal input channels, can perform various signal data acquisition, can be widely applied to the fields of automatic test systems, signal measurement display and the like, meanwhile, the design of mass DMA transmission of data through PCIE interfaces can be realized, an application layer is notified to acquire data in an asynchronous notification mode, a synchronous acquisition function among multiple platen cards is realized in an external synchronous clock mode, and the system supports edge calculation of signals, and can analyze time domain information and waveform characteristic information of the signals.

Disclosure of Invention

In order to solve the problems in the prior art, the utility model provides a PCIE high-speed acquisition system which integrates the technologies of high-speed parallel interface communication, signal processing, clock synchronization, PCIE system structure and the like, has 12 signal input channels, can acquire various signal data, can be widely applied to the fields of automatic test systems, signal measurement display and the like, can realize the design of mass DMA (direct memory access) transmission of data through a PCIE interface, informs an application layer to acquire data in an asynchronous notification mode, realizes a synchronous acquisition function among a plurality of platen cards in an external synchronous clock mode, supports edge calculation of signals, and can analyze time domain information and waveform characteristic information of the signals.

In order to achieve the above purpose, the present utility model provides the following technical solutions: the PCIE high-speed acquisition system comprises an analog front-end circuit, a high-speed signal acquisition and signal processing module, a PCIE backboard, computer control software, an AC-DC power module and a structural member, wherein the external power supply of the system is 220V, and the system provides energy for the whole machine; the analog front-end circuit power supply network further processes the direct current power supply provided by the AC-DC power supply module and outputs 12V, 5V, 3.3V and 1.8V power supplies; the PCIE bus is selected as the data transmission bus, the analog front-end circuit and the FPGA core board circuit form an acquisition main card, each acquisition main card realizes synchronous acquisition of 6 channels, and the system totally uses two acquisition main cards to realize synchronous acquisition of 12 channels.

As the preferable technical scheme of the pcie high-speed acquisition system, on a signal path, an input signal is sent to an analog front-end circuit, an output signal is connected to an FPGA signal acquisition module, and the FPGA receives a digital signal transmitted by an ADC (analog-to-digital converter) to perform signal processing, storage and transmission operations; the power supply network provides power for the analog front-end circuit and the FPGA core board, and the power supply isolation scheme is adopted to separate the analog power supply from the digital power supply so as to ensure the stable operation of the system; meanwhile, in order to ensure synchronous acquisition accuracy, the clock of the master card is transmitted to the slave machine through the coaxial cable, and the slave machine receives the clock as the sampling clock of the ADC; the PC upper computer software realizes interaction with the FPGA through the PCIE of the backboard, and comprises data read-write operation, and in order to improve the data transmission efficiency, a DMA mode is adopted.

As the preferable technical scheme of the PCIE high-speed acquisition system, the signal acquisition card is realized by a hardware circuit and consists of a power circuit unit, a clock circuit unit, an analog-digital conversion circuit unit, an FPGA circuit unit, a high-speed large-capacity storage unit and a PCIE interface unit; the internal logic of the FPGA consists of data calibration, fine triggering, storage control, a data and synchronization interface, a DMA (direct memory access) and a PCIe (peripheral component interconnect express) interface.

As the preferable technical scheme of the pc ie high-speed acquisition system, the input source of the power circuit is a 12V power supply provided by the backboard, the primary power circuit adopts a DC-DC converter to convert 12V into a plurality of voltages of 1V, 1.5V and 3.3V, and for the voltage with higher ripple requirement, a low-noise LDO converter is adopted to convert the voltage into the required voltage.

As the preferable technical scheme of the PCIe high-speed acquisition system, the clock circuit unit generates multiple paths of clocks required by the system operation, including multiple different-speed clocks required by FPGA, high-speed ADC, DDR3 and PCIe interfaces.

Compared with the prior art, the utility model has the beneficial effects that:

the utility model mainly comprises an analog front-end circuit, a high-speed signal acquisition and signal processing module, a PCIE backboard, computer control software, an AC-DC power module and a structural member, integrates the technologies of high-speed parallel interface communication, signal processing, clock synchronization, PCIE architecture and the like, has 12 signal input channels, can acquire various signal data, can be widely applied to the fields of automatic test systems, signal measurement display and the like, can realize the design of mass DMA (direct memory access) transmission of the data through the PCIE interface, informs an application layer to acquire the data in an asynchronous notification mode, realizes the synchronous acquisition function among a plurality of platen cards in an external synchronous clock mode, and can analyze the time domain information and waveform characteristic information of the signal by carrying out edge calculation on the signal by the system support.

Drawings

The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the embodiments of the utility model, serve to explain the utility model. In the drawings:

FIG. 1 is a general block diagram of the present utility model;

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Examples

Referring to fig. 1, the present utility model provides the following technical solutions: the whole PCIE high-speed acquisition system consists of an analog front-end circuit, a high-speed signal acquisition and signal processing module, a PCIE backboard, computer control software, an AC-DC power module and a structural member; the external power supply of the whole machine is 220V, so as to provide energy for the whole machine; the analog front-end circuit power supply network further processes the direct current power supply provided by the AC-DC power supply module and outputs 12V, 5V, 3.3V, 1.8V and other power supplies; the PCIE bus is selected as the data transmission bus, the analog front-end circuit and the FPGA core board circuit form an acquisition main card, each acquisition main card realizes synchronous acquisition of 6 channels, and the system totally uses two acquisition main cards to realize synchronous acquisition of 12 channels.

Further, on the signal path, an input signal is sent to an analog front-end circuit, an output signal is connected to an FPGA signal acquisition module, and the FPGA receives a digital signal transmitted by the ADC to perform signal processing, storage and transmission operation; the power supply network provides power for the analog front-end circuit and the FPGA core board, and the power supply isolation scheme is adopted to separate the analog power supply from the digital power supply so as to ensure the stable operation of the system; meanwhile, in order to ensure synchronous acquisition accuracy, the clock of the master card is transmitted to the slave machine through the coaxial cable, and the slave machine receives the clock as the sampling clock of the ADC; the PC upper computer software realizes interaction with the FPGA through the PCIE of the backboard, and comprises data read-write operation, and in order to improve the data transmission efficiency, a DMA mode is adopted.

Further, in the hardware circuit implementation, the signal acquisition card consists of a power supply circuit unit, a clock circuit unit, an analog-digital conversion circuit unit, an FPGA circuit unit, a high-speed large-capacity storage unit and a PCIE interface unit; the system comprises an FPGA circuit unit, a high-speed large-capacity storage unit, a PCIe interface unit and the like; the internal logic of the FPGA consists of data calibration, fine triggering, storage control, a data and synchronization interface, a DMA (direct memory access) and a PCIe (peripheral component interconnect express) interface.

Furthermore, the power circuit is the basis of the high-speed acquisition module to work, and the design principle of the power circuit has two requirements, namely, the requirements of circuit current and ripple are met, and the power utilization efficiency is improved; the input source of the power circuit is a 12V power supply provided by a backboard, the primary power circuit adopts a DC-DC converter to convert 12V into a plurality of voltages of 1V, 1.5V, 3.3V and the like, and for other voltages with higher ripple requirements, the primary power circuit adopts a low-noise LDO converter to convert the other voltages into required voltages.

Furthermore, the clock circuit unit generates multiple paths of clocks required by system operation, including multiple different-speed clocks required by FPGA, high-speed ADC, DDR3, PCIe interface and the like; the quality of the clock is critical for high-speed signal acquisition, and important attention is paid to design, which directly affects the effective resolution of the sampled signal.

Referring to fig. 1, a PCIE core acquisition board hardware design analyzes an analog-to-digital converter (ADC), an FPGA, and a DDR3 memory interface from impedance matching and level compatibility aspects, and completes a corresponding circuit design, then completes simulation analysis and circuit design of an off-chip loop filter according to a phase noise model of a phase locked loop, and finally, in order to meet different power requirements of each device of a module, uses an LDO (low dropout linear regulator) and a switching power supply to construct a power supply circuit of the module.

Furthermore, the FPGA logic design mainly analyzes a system acquisition flow, completes acquisition and storage of waveform data through the design of an ADC data receiving module and an on-chip storage module, learns a high-speed serial interface protocol, transmits the waveform data to an upper computer through a PCIE data transmission module, and completes FPGA logic design, time domain feature and waveform feature calculation of an FFT algorithm.

In this embodiment, the utility model is mainly composed of analog front-end circuit, high-speed signal acquisition and signal processing module, PCIE backboard, computer control software, AC-DC power module and structural component, which integrates the technologies of high-speed parallel interface communication, signal processing, clock synchronization, PCIE architecture, etc., with 12 signal input channels, able to collect various signal data, able to be widely used in fields of automatic test system, signal measurement display, etc., and able to realize massive DMA transmission of data through PCIE interface, adopting asynchronous notification mode to inform application layer to obtain data, adopting external synchronous clock mode to realize synchronous acquisition function among multiple platen cards, and the system supports edge calculation of signals, able to analyze time domain information and waveform characteristic information of signals.

The utility model has the following application flow and working principle: the upper computer software runs on the PC, and can directly double click the EXE executable file to run and can open QT source code to run; the soft panel interface mainly includes: the device comprises an acquisition configuration part, a waveform display part, a parameter display part, an amplitude and time base control part, a parameter measurement part, a waveform data processing part and an acquisition control part, wherein the waveform display part is used for completing the display of two paths of waveforms and measurement auxiliary lines; the amplitude and time base control area mainly completes the movement and the expansion transformation of the waveform in the horizontal and vertical directions, and simultaneously can use the function of a magnifying glass to carry out frame selection and magnification on the waveform, so that the acquired waveform is easy to observe and measure; the measurement control area realizes control of the waveform measurement auxiliary line, and is convenient for a user to manually measure the waveform.

In this embodiment, the contents not described in detail are common knowledge and the prior art.

Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present utility model, and the present utility model is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present utility model has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (5)

1. A pcie high-speed acquisition system, characterized in that: the system comprises an analog front-end circuit, a high-speed signal acquisition and signal processing module, a PCIE backboard, computer control software, an AC-DC power module and a structural member, wherein the external power supply of the system is 220V, and provides energy for the whole machine; the analog front-end circuit power supply network further processes the direct current power supply provided by the AC-DC power supply module and outputs 12V, 5V, 3.3V and 1.8V power supplies; the PCIE bus is selected as the data transmission bus, the analog front-end circuit and the FPGA core board circuit form an acquisition main card, each acquisition main card realizes synchronous acquisition of 6 channels, and the system totally uses two acquisition main cards to realize synchronous acquisition of 12 channels.
2. 2. The pcie high speed acquisition system according to claim 1, wherein: on the signal path, an input signal is sent to an analog front-end circuit, an output signal is connected to an FPGA signal acquisition module, and the FPGA receives a digital signal transmitted by an ADC (analog to digital converter) to perform signal processing, storage and transmission operations; the power supply network provides power for the analog front-end circuit and the FPGA core board, and the power supply isolation scheme is adopted to separate the analog power supply from the digital power supply so as to ensure the stable operation of the system; meanwhile, in order to ensure synchronous acquisition accuracy, the clock of the master card is transmitted to the slave machine through the coaxial cable, and the slave machine receives the clock as the sampling clock of the ADC; the PC upper computer software realizes interaction with the FPGA through the PCIE of the backboard, and comprises data read-write operation, and in order to improve the data transmission efficiency, a DMA mode is adopted.
3. 3. The pcie high speed acquisition system according to claim 1, wherein: in the hardware circuit implementation, the signal acquisition card consists of a power supply circuit unit, a clock circuit unit, an analog-digital conversion circuit unit, an FPGA circuit unit, a high-speed large-capacity storage unit and a PCIE interface unit; the internal logic of the FPGA consists of data calibration, fine triggering, storage control, a data and synchronization interface, a DMA (direct memory access) and a PCIe (peripheral component interconnect express) interface.
4. 4. The pcie high speed acquisition system according to claim 1, wherein: the input source of the power circuit is a 12V power supply provided by a backboard, the primary power circuit adopts a DC-DC converter to convert 12V into a plurality of voltages of 1V, 1.5V and 3.3V, and for the voltage with higher ripple requirements, the primary power circuit adopts a low-noise LDO converter to convert the voltage into the required voltage.
5. 5. The pcie high speed acquisition system according to claim 1, wherein: the clock circuit unit generates multiple paths of clocks required by the system operation, including multiple different-speed clocks required by FPGA, high-speed ADC, DDR3 and PCIe interfaces.