CN220173719U - Superconducting quantum chip - Google Patents
Superconducting quantum chip Download PDFInfo
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- CN220173719U CN220173719U CN202321589888.8U CN202321589888U CN220173719U CN 220173719 U CN220173719 U CN 220173719U CN 202321589888 U CN202321589888 U CN 202321589888U CN 220173719 U CN220173719 U CN 220173719U
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- 239000002096 quantum dot Substances 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 181
- 238000000034 method Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Abstract
The utility model discloses a superconducting quantum chip, and belongs to the technical field of quantum bit chips. The superconducting quantum chip comprises three stacked superconducting layers and supporting layers for mutually spacing the three superconducting layers, wherein a first grounding structure, a quantum bit structure and a first coplanar waveguide are formed on one of the uppermost superconducting layer and the lowermost superconducting layer, and a second grounding structure, a transmission line and a second coplanar waveguide are formed on the other superconducting layer; the first grounding structure and the second grounding structure are oppositely arranged and are interconnected with the middle layer superconducting layer through a through hole penetrating through the supporting layer, the qubit structure and the transmission line are oppositely arranged and are coupled through different surfaces of a window on the middle layer superconducting layer, and the first coplanar waveguide and the second coplanar waveguide are oppositely arranged and are isolated by the middle layer superconducting layer; through the mode, the flip chip bonding device can realize similar functions of flip chip bonding, circuits can be crossed, and flexibility of wiring is improved.
Description
Technical Field
The utility model belongs to the technical field of a quantum bit chip, and particularly relates to a superconducting quantum chip.
Background
At present, three technologies for interconnecting integrated circuits are mainly used: wire bonding techniques, tape automated bonding techniques, and flip chip techniques, wherein the flip chip technique can use the entire chip area for interconnection with a substrate, greatly increasing the number of I/os.
The flip chip technology greatly improves the integration level of the electronic device, has the advantages of small size, thin thickness, light weight, strong heat dissipation capacity and the like, but has complex process and high packaging precision requirement, and has a plurality of defects such as: flip-chip bonding is prone to distortion, i.e., the Base layer and Flip layer are not parallel, resulting in reduced yields when specifically produced.
Disclosure of Invention
The utility model aims to provide a superconducting quantum chip, which solves the problems of complex process, high required precision and the like of the flip chip technology in the prior art, can realize similar functions without using the flip chip technology, not only can the circuits be crossed, but also the flexibility of wiring is increased.
In order to solve the technical problems, the utility model provides a superconducting quantum chip, which comprises three layers of laminated superconducting layers 1 and supporting layers 2 for mutually spacing the three layers of superconducting layers 1,
one superconducting layer 1 of the uppermost superconducting layer 11 and the lowermost superconducting layer 13 is formed with a first grounding structure 111, a qubit structure 112 and a first coplanar waveguide 113, and the other superconducting layer 1 is formed with a second grounding structure 131, a transmission line 132 and a second coplanar waveguide 133;
the first and second ground structures 111 and 131 are disposed opposite each other and interconnected with the intermediate layer superconducting layer 12 through a via 3 penetrating the support layer 2, the qubit structure 112 and the transmission line 132 are disposed opposite each other and coupled out-of-plane through a window 121 on the intermediate layer superconducting layer 12, and the first and second coplanar waveguides 113 and 133 are disposed opposite each other and isolated by the intermediate layer superconducting layer 12.
Preferably, the supporting layer 2 is a low-loss material.
Preferably, the support layer 2 includes a first support layer 21 and a second support layer 22;
the first support layer 21 is located between the uppermost superconducting layer 11 and the intermediate superconducting layer 12, and the second support layer 22 is located between the lowermost superconducting layer 13 and the intermediate superconducting layer 12;
the superconducting quantum chip further includes: the substrate 4 is disposed on a surface of the lowermost superconducting layer 13 facing away from the first supporting layer 21.
Preferably, the thickness of the support layer 2 in the lamination direction is much larger than the thickness of the superconductive layer 1.
Preferably, the uppermost superconducting layer 11 is formed with a first ground structure 111, a qubit structure 112, and a first coplanar waveguide 113.
Preferably, the lowermost superconducting layer 13 is formed with a second ground structure 131, a transmission line 132, and a second coplanar waveguide 133.
Preferably, the transmission line 132 includes a control line;
the control lines comprise a microwave control line and a direct current control line.
Preferably, the through hole 3 includes a first through hole 31 and a second through hole 32 which are opposite to each other;
the first through hole 31 penetrates the first support layer 21, and the second through hole 32 penetrates the second support layer 22.
Preferably, the first through hole 31 communicates with the second through hole 32, that is, the through hole 3 penetrates the intermediate layer superconductive layer 12;
alternatively, the first via 31 is located above the intermediate layer superconductive layer 12, and the second via 32 is located below the intermediate layer superconductive layer 12, i.e. the via 3 is interrupted by the intermediate layer superconductive layer 12.
Preferably, the sections of the first through hole 31 and the second through hole 32 in the horizontal direction are rectangular;
the edge of the first through hole 31 cut in the horizontal direction is within the edge of the second through hole 32 cut in the horizontal direction.
Compared with the prior art, the utility model provides a layout structure and a quantum chip, which are formed by stacking a first superconducting layer, a second superconducting layer, a third superconducting layer, a first dielectric layer and a second dielectric layer; and the grounding hole penetrates through the second superconducting layer, the first dielectric layer and the second dielectric layer, so that the electrical connection among the third superconducting layer, the first superconducting layer and the second superconducting layer is realized, and the signal wires on the first superconducting layer and the second superconducting layer are subjected to out-of-plane coupling through the opening of the second superconducting layer, so that the quantum bit structure on the superconducting layer can be in information interconnection, and a complete superconducting quantum chip is formed. According to the utility model, the flip chip bonding process is not used, the problems of complex process, high packaging precision and the like are not faced, and similar packaging performance can be still obtained.
Drawings
FIG. 1 is a schematic view of the superconducting layer and supporting layer structure of a superconducting quantum chip according to the present utility model;
FIG. 2 is a schematic view of a superconducting layer and a supporting layer structure of a superconducting quantum chip provided by the utility model, which are placed on a substrate;
FIG. 3 is a schematic diagram of a structure in which a through hole of a superconducting quantum chip provided by the utility model is blocked by a superconducting layer of an intermediate layer;
fig. 4 is a top view of a superconducting quantum chip provided by the present utility model.
Reference numerals illustrate: 1-superconducting layer, 11-uppermost superconducting layer, 12-intermediate superconducting layer, 13-lowermost superconducting layer, 111-first grounding structure, 112-qubit structure, 113-first coplanar waveguide, 121-window, 131-second grounding structure, 132-transmission line, 133-second coplanar waveguide, 2-supporting layer, 21-first supporting layer, 22-second supporting layer, 3-through hole, 31-first through hole, 32-second through hole, 4-substrate.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model.
Referring to fig. 1, a superconducting quantum chip includes three stacked superconducting layers 1 and a supporting layer 2 separating the three superconducting layers 1 from each other;
one superconducting layer 1 of the uppermost superconducting layer 11 and the lowermost superconducting layer 13 is formed with a first grounding structure 111, a qubit structure 112 and a first coplanar waveguide 113, and the other superconducting layer 1 is formed with a second grounding structure 131, a transmission line 132 and a second coplanar waveguide 133;
the first and second ground structures 111 and 131 are disposed opposite each other and interconnected with the intermediate layer superconducting layer 12 through the via 3 penetrating the support layer 2, the qubit structure 112 and the transmission line 132 are disposed opposite each other and coupled out-of-plane through the window 121 on the intermediate layer superconducting layer 12, and the first and second coplanar waveguides 113 and 133 are disposed opposite each other and isolated by the intermediate layer superconducting layer 12.
In this scheme, a new quantum chip structure is provided, and three layers of superconducting layers 1 are designed, wherein the uppermost superconducting layer 11 and the lowermost superconducting layer 13 are used for forming the necessary structure of the superconducting quantum chip, and various circuits of the superconducting quantum chip are arranged, and in consideration of the fact that signal reading lines of the superconducting quantum chip are easy to generate crosstalk due to the influence of magnetic fields and electric fields, an intermediate superconducting layer 12 is additionally arranged between the uppermost superconducting layer 11 and the lowermost superconducting layer 13 and used for isolating the uppermost superconducting layer 11 and the lowermost superconducting layer 13.
Meanwhile, in order to stabilize and support the three-layer laminated superconducting layer 1, the scheme adopts a mode of adding the support layer 2 to physically isolate and stabilize the three-layer superconducting layer 1.
In order to couple the dc signal control line and the microwave control line to the uppermost superconducting layer 11 or the lowermost superconducting layer 13 respectively, the intermediate superconducting layer 12 at the opposite position is provided with a window 121 of a corresponding size to couple the two superconducting layers to each other in a different-surface manner.
As the conventional chip is consistent, the superconducting quantum chip in the scheme also needs to be provided with a grounding hole at a proper position, and the three layers of superconducting layers 1 which are stacked and arranged can be electrically connected through the grounding hole.
In the embodiment of the present utility model, the support layer 2 is a low-loss material.
In this embodiment, the bit structure of the uppermost superconducting layer 11 and the control line of the lowermost superconducting layer 13 need to be coupled in different planes, but in the present utility model, the different planes are coupled by a medium, so, to ensure the trafficability of the coupled signals, it is preferable to use a low-loss material, such as amorphous silicon, and the material of the supporting layer 2 can be selected according to the actual situation, and is not limited by the above materials.
Referring again to fig. 1 and 2, the support layer 2 includes a first support layer 21 and a second support layer 22; a first support layer 21 is located between the uppermost superconducting layer 11 and the intermediate superconducting layer 12, and a second support layer 22 is located between the lowermost superconducting layer 13 and the intermediate superconducting layer 12;
obviously, the supporting layer 2 comprises two parts which are distributed in the superconducting quantum chip in an up-down mode, wherein the first supporting layer 21 is arranged between the uppermost superconducting layer 11 and the middle superconducting layer 12 and is closely attached to the uppermost superconducting layer; the second support layer 22 is disposed between the lowermost superconducting layer 13 and the intermediate superconducting layer 12, in close contact therewith.
The superconducting quantum chip further includes: the substrate 4 is disposed on a surface of the lowermost superconducting layer 13 facing away from the first supporting layer 21.
As is well known, the superconducting quantum chip also comprises a substrate 4, which is used as a bottom material of the superconducting quantum chip and mainly plays roles of physical support, heat conduction, electric conduction and the like, and the substrate 4 can be a silicon substrate, a sapphire substrate and other materials, and can be selected according to actual needs.
Further, the thickness of the support layer 2 in the lamination direction is much larger than that of the superconducting layer 1.
In the process of manufacturing the superconducting quantum chip, various superconducting elements need to be etched on the surface of the superconducting layer 1, which inevitably leads to uneven surface of the superconducting layer 1, so that the subsequent packaging of the superconducting quantum chip is difficult, and performance loss is caused, therefore, the supporting layer 2 with the thickness far greater than that of the superconducting layer 1 is arranged and used for weakening negative effects caused by the uneven superconducting layer 1, for example, the order of magnitude of 5um is adopted as a dielectric layer, and the superconducting layer is 70-100nm, so that the uneven caused by the superconducting layer 1 can be ignored.
In the embodiment of the present utility model, the uppermost superconducting layer 11 is formed with a first ground structure 111, a qubit structure 112, and a first coplanar waveguide 113;
the transmission line 132 includes a control line;
the control lines comprise microwave control lines and direct current control lines.
The lowermost superconducting layer 13 is formed with a second ground structure 131, a transmission line 132, and a second coplanar waveguide 133.
The uppermost superconducting layer 11 and the lowermost superconducting layer 13 are oppositely arranged, so that electromagnetic balance among the components is achieved, crosstalk is avoided, and out-of-plane coupling can be performed through the window 121 of the intermediate superconducting layer 12; the microwave control line and the flux bias line are respectively associated with the quantum bit so as to control the quantum bit, for example, the microwave control line can adjust the state of the quantum bit, and the flux bias line can control the frequency of the quantum bit. In this embodiment, the bit capacitor, the josephson junction, the resonant cavity, and the qubit coupler are necessarily disposed on the uppermost superconducting layer 11, and the microwave control line, the direct current control line, and the readout signal line may be disposed on the lowermost superconducting layer 13, where the microwave control line performs out-of-plane coupling through the window 121 formed in the intermediate superconducting layer 12, and the direct current control line and the josephson junction perform out-of-plane coupling, and the readout signal line and the resonant cavity perform out-of-plane coupling; in addition, although the readout signal line may be theoretically provided on the uppermost superconducting layer 11, if the readout signal line is provided on the same superconducting layer 1 as the qubit, the bit array is likely to be limited due to the structural problem, and the entire planar layout is not possible.
Referring to fig. 2, the through hole 3 includes a first through hole 31 and a second through hole 32 opposite to each other;
the first through hole 31 penetrates through the first supporting layer 21, and the second through hole 32 penetrates through the second supporting layer 22;
in the embodiment, the through hole 3 is a grounding hole, and three layers of superconducting layers 1 which are mainly stacked are kept at the same potential, so that no potential difference exists between the three layers of superconducting layers 1; in addition, electrical connection between the superconducting layers 1 is required, and the through holes 3 provide a connection channel with extremely high efficiency for electrical connection between the superconducting layers 1, and the charged wires may be in the form of conductive layers attached to the through holes 3.
Referring to fig. 1 and 3, the first through hole 31 communicates with the second through hole 32, i.e. the through hole 3 penetrates the interlayer superconductive layer 12;
alternatively, the first via 31 is located above the intermediate layer superconductive layer 12, and the second via 32 is located below the intermediate layer superconductive layer 12, i.e. the via 3 is interrupted by the intermediate layer superconductive layer 12.
In the utility model, to realize the functions of electric connection, grounding and the like of three superconducting layers, the uppermost superconducting layer 11 and the lowermost superconducting layer 13 can be simultaneously and electrically connected with the middle superconducting layer 12, namely the first through hole 31 and the second through hole 32 can be communicated, the middle superconducting layer 12 is penetrated, the through holes 3 of the type are easier to etch in terms of manufacturing process, and the requirement on the precision of equipment is not high; it is not excluded that the intermediate superconducting layer 12 may maintain the integrity except for the opening of the window 121 as required, i.e. in the manufacturing process, the second support layer 22 is etched through the hole 3, then the intermediate superconducting layer 12 is plated, then the first support layer 21 is provided and etched, and finally the uppermost superconducting layer 11 is plated.
Referring to fig. 4, the cross sections of the first through holes 31 and the second through holes 32 in the horizontal direction are rectangular;
the edge of the first through hole 31 cut in the horizontal direction is within the edge of the second through hole 32 cut in the horizontal direction.
In the present embodiment, the first through hole 31 and the second through hole 32 are set to be rectangular, and the tangential edge of the first through hole 31 in the horizontal direction is set to be stepped in the tangential edge of the second through hole 32 in side view, since the intermediate superconducting layer 12 is thin and tends to be less than 100nm in thickness, if not stepped, the intermediate superconducting layer 12 is difficult to contact well with the uppermost superconducting layer 11 and the lowermost superconducting layer 13, resulting in poor electrical communication effect; in practical application, the first through hole 31 and the second through hole 32 can be smoothly transited without steps, and the purpose of electrically connecting the three layers of superconducting layers 1 can be achieved through the connection of the chip surrounding bonding wires, and the method can be selected according to practical situations in practical application, and is not limited by the above.
While the foregoing is directed to embodiments of the present utility model, other and further embodiments of the utility model may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A superconducting quantum chip is characterized by comprising three stacked superconducting layers (1) and supporting layers (2) for mutually spacing the three superconducting layers (1),
a first grounding structure (111), a qubit structure (112) and a first coplanar waveguide (113) are formed on one superconducting layer (1) of the uppermost superconducting layer (11) and the lowermost superconducting layer (13), and a second grounding structure (131), a transmission line (132) and a second coplanar waveguide (133) are formed on the other superconducting layer (1);
the first grounding structure (111) and the second grounding structure (131) are oppositely arranged and are interconnected with the middle-layer superconducting layer (12) through a through hole (3) penetrating through the supporting layer (2), the quantum bit structure (112) and the transmission line (132) are oppositely arranged and are coupled in an out-of-plane manner through a window (121) on the middle-layer superconducting layer (12), and the first coplanar waveguide (113) and the second coplanar waveguide (133) are oppositely arranged and are isolated by the middle-layer superconducting layer (12).
2. Superconducting quantum chip according to claim 1, characterized in that the support layer (2) is a low-loss material.
3. Superconducting quantum chip according to claim 1, characterized in that the support layer (2) comprises a first support layer (21) and a second support layer (22);
the first support layer (21) is located between the uppermost superconducting layer (11) and the intermediate superconducting layer (12), and the second support layer (22) is located between the lowermost superconducting layer (13) and the intermediate superconducting layer (12);
the superconducting quantum chip further includes: and the substrate (4) is arranged on one surface of the lowest superconducting layer (13) which is away from the first supporting layer (21).
4. Superconducting quantum chip according to claim 1, characterized in that the thickness of the support layer (2) in the stacking direction is much greater than the thickness of the superconducting layer (1).
5. The superconducting quantum chip according to claim 1, wherein the uppermost superconducting layer (11) is formed with a first ground structure (111), a qubit structure (112) and a first coplanar waveguide (113).
6. The superconducting quantum chip according to claim 5, wherein the lowermost superconducting layer (13) is formed with a second ground structure (131), a transmission line (132), and a second coplanar waveguide (133).
7. The superconducting quantum chip of claim 6, wherein the transmission line (132) comprises a control line;
the control lines comprise a microwave control line and a direct current control line.
8. A superconducting quantum chip according to claim 3, characterized in that the via (3) comprises a first via (31) and a second via (32) opposite each other;
the first through hole (31) penetrates through the first supporting layer (21), and the second through hole (32) penetrates through the second supporting layer (22).
9. The superconducting quantum chip according to claim 8, wherein the first via (31) communicates with a second via (32), the via (3) penetrating the intermediate layer superconducting layer (12);
or, the first through hole (31) is located above the middle-layer superconducting layer (12), the second through hole (32) is located below the middle-layer superconducting layer (12), and the through hole (3) is blocked by the middle-layer superconducting layer (12).
10. The superconducting quantum chip according to claim 8, wherein the first through hole (31) and the second through hole (32) have a rectangular cross section in a horizontal direction;
the edge of the first through hole (31) cut in the horizontal direction is positioned in the edge of the second through hole (32) cut in the horizontal direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321589888.8U CN220173719U (en) | 2023-06-20 | 2023-06-20 | Superconducting quantum chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321589888.8U CN220173719U (en) | 2023-06-20 | 2023-06-20 | Superconducting quantum chip |
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| Publication Number | Publication Date |
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| CN220173719U true CN220173719U (en) | 2023-12-12 |
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| CN202321589888.8U Active CN220173719U (en) | 2023-06-20 | 2023-06-20 | Superconducting quantum chip |
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| CN (1) | CN220173719U (en) |
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