CN220172072U - Heat treatment device for semiconductor - Google Patents

Abstract

The present utility model provides a heat treatment apparatus for a semiconductor, comprising: the first furnace body is used for being in butt joint with the heating device so as to heat the first furnace body through the heating device; the second furnace body is positioned in the first furnace body and is used for butting heat conducted by the first furnace body; the second furnace body is internally provided with a chip heating space, and the chip heating space conducts heat through the second furnace body so as to heat at least two chips. According to the utility model, the heat of the first furnace body is conducted through the second furnace body, so that the heat distribution of the second furnace body is more uniform, the temperature difference between the upper surface and the lower surface of the chip during heating is reduced, and the chip is uniformly annealed.

Description

Heat treatment device for semiconductor

Technical Field

The utility model relates to the technical field of semiconductor manufacturing, in particular to a heat treatment device for a semiconductor.

Background

In the semiconductor industry, it is essential to heat treat semiconductor materials, and the main purpose of the heat treatment is to release internal stress, increase ductility of the materials, reduce deformation and crack tendency, and at the same time, change the crystal phase organization structure of the surface or the inside of the semiconductor materials, eliminate defects, etc., so as to obtain the required specific properties. In practice, annealing is one of the most common means in semiconductor material heat treatment processes.

However, the conventional heat treatment apparatus has the following drawbacks: firstly, in the heating process of the existing heat treatment device, huge temperature difference exists on the upper surface and the lower surface of a chip, and the heating is uneven; secondly, in the annealing process, the whole heat treatment device has temperature gradient, so that semiconductor chips at different positions are subjected to different temperatures, and the annealing treatment of a plurality of semiconductor chips is not facilitated.

Disclosure of Invention

In order to overcome the defects in the prior art, the utility model provides a heat treatment device for a semiconductor, which conducts heat of a first furnace body through a second furnace body so as to enable heat distribution of the second furnace body to be more uniform, thereby reducing temperature difference between the upper surface and the lower surface of a chip during heating and enabling the chip to be annealed uniformly. The specific technical scheme is as follows:

a heat treatment apparatus for a semiconductor, comprising: the device comprises a first furnace body and a second furnace body, wherein the first furnace body is used for being in butt joint with a heating device so as to heat the first furnace body through the heating device;

the second furnace body is positioned in the first furnace body and is used for butting heat conducted by the first furnace body;

the second furnace body is internally provided with a chip heating space, and the chip heating space conducts heat through the second furnace body so as to heat at least two chips.

In a specific embodiment, at least two chip containers are arranged in the second furnace body, and a containing cavity for containing chips is formed in the chip containers.

In a specific embodiment, at least two chip containers are sequentially arranged along the height direction of the second furnace body, and a gap is reserved between two adjacent chip containers.

In a specific embodiment, a supporting member is disposed on the bottom surface of the interior of the first furnace body, and the supporting member is connected to the bottom of the second furnace body.

In a specific embodiment, the contact area of the support member and the second furnace body is less than 30% of the contact area of the support member and the first furnace body.

In a specific embodiment, the thickness of the first furnace body is greater than 2mm and less than 10mm.

In a specific embodiment, the first furnace body is provided with a temperature measuring hole, and the temperature measuring hole is used for being connected with a temperature measuring device to measure the temperature of the first furnace body.

In a specific embodiment, the diameter of the temperature measuring hole is not less than 2mm.

In a specific embodiment, the chip container includes a placement table and an upper cover, one of the placement table and the upper cover is provided with a protrusion portion, and the other is provided with a groove portion, and the protrusion portion is adapted to the groove portion, so as to realize detachable connection of the placement table and the upper cover.

In a specific embodiment, a plurality of mounting grooves are formed in the side portion of the second furnace body, and the mounting grooves are matched with the chip container and are used for embedding the chip container into the mounting grooves.

The utility model has at least the following beneficial effects:

the present utility model provides a heat treatment apparatus for a semiconductor, comprising: the first furnace body is used for being in butt joint with the heating device so as to heat the first furnace body through the heating device; the second furnace body is positioned in the first furnace body and is used for butting heat conducted by the first furnace body; the second furnace body is internally provided with a chip heating space, and the chip heating space conducts heat through the second furnace body so as to heat at least two chips. According to the utility model, the heat of the first furnace body is conducted through the second furnace body, so that the heat distribution of the second furnace body is more uniform, the temperature difference between the upper surface and the lower surface of the chip during heating is reduced, the chip is uniformly annealed, the normal operation of chip annealing is ensured, and the plurality of chips are heated simultaneously by reducing the temperature difference, so that the production efficiency of the chips is improved.

Further, at least two chip containers are arranged in the second furnace body, and a containing cavity for containing chips is formed in the chip containers. At least two chip containers are sequentially arranged along the height direction of the second furnace body, and a gap is reserved between every two adjacent chip containers. The heat conduction between the two adjacent chip containers is reduced by reserving a gap between the two adjacent chip containers, thereby reducing the temperature difference between the chip containers.

Further, a temperature measuring hole is formed in the first furnace body and is used for being connected with a temperature measuring device to measure the temperature of the first furnace body. Preferably, the diameter of the temperature measuring hole is not less than 2mm. The diameter of the temperature measuring hole is limited to ensure that the temperature measurement of the first furnace body can be performed.

Further, the contact area of the supporting piece and the second furnace body is smaller than 30% of the contact area of the supporting piece and the first furnace body. Through this setting, under the support effect of support piece to the second furnace body, still reduced the heat that conducts to the second furnace body through support piece to it is more even to make the second furnace body be heated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a cross-sectional view of a heat treatment apparatus for a semiconductor provided by the present utility model;

fig. 2 is a cross-sectional view 2 of a heat treatment apparatus for semiconductors provided by the present utility model;

fig. 3 is a cross-sectional view of a chip container of a heat treatment apparatus for semiconductors provided by the present utility model;

FIG. 4 is a schematic diagram of a chip container for a semiconductor heat treatment apparatus according to the present utility model;

fig. 5 is a schematic diagram showing the temperature difference between the upper and lower surfaces of the heat treatment apparatus for semiconductor according to the present utility model.

Reference numerals:

1-a first furnace body; 2-a second furnace body; 3-chip container; 4-a support; 5-a temperature measuring hole;

11-a bottom plate; 12-side plates; 13-cover plate;

21-chip heating space;

31-a receiving chamber;

32-placing a table; 33-an upper cover;

321-groove portions; 331-protrusions.

Detailed Description

Hereinafter, various embodiments of the present utility model will be described more fully. The utility model is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the various embodiments of the utility model to the specific embodiments disclosed herein, but rather the utility model is to be understood to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the utility model.

Hereinafter, the terms "comprises" or "comprising" as may be used in various embodiments of the present utility model indicate the presence of the disclosed functions, operations or elements, and are not limiting of the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the utility model, the terms "comprises," "comprising," and their cognate terms are intended to refer to a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be interpreted as first excluding the existence of or increasing likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

As shown in fig. 1 to 4, the present utility model provides a heat treatment apparatus for a semiconductor, comprising: the furnace comprises a first furnace body 1 and a second furnace body 2, wherein the first furnace body 1 is used for being abutted with a heating device so as to heat the first furnace body 1 through the heating device; the second furnace body 2 is positioned in the first furnace body 1, and the second furnace body 2 is used for butting heat conducted by the first furnace body 1; the second furnace body 2 has a chip heating space 21 inside, and the chip heating space 21 conducts heat through the second furnace body 2 to heat at least two chips. According to the utility model, the heat of the first furnace body 1 is conducted through the second furnace body 2, so that the heat distribution of the second furnace body 2 is more uniform, the temperature difference between the upper surface and the lower surface of the chip during heating is reduced, the chip is uniformly annealed, the normal operation of chip annealing is ensured, and the plurality of chips are heated simultaneously by reducing the temperature difference, so that the chip production efficiency is improved.

As shown in fig. 1 to 4, the first furnace body 1 has a bottom plate 11, side plates 12, and a cover plate 13. The bottom plate 11, the side plates 12 and the cover plate 13 may be separated from each other. The bottom plate 11 closes one end of the side plate 12, and the cover plate 13 closes the other end of the side plate 12, thereby forming a first sealed space in the first furnace body 1. By providing the first furnace body 1 with a plurality of components including the bottom plate 11, the side plate 12 and the cover plate 13, and the bottom plate 11, the side plate 12 and the cover plate 13 are detachably connected, the subsequent installation of the second furnace body 2 and the like is facilitated.

Wherein the first furnace body 1 is heated by a heating device arranged outside. The first furnace 1 may be heated by a hot electron bombardment method, a high-frequency heating method, a resistance heating method, a lamp heating method, or the like. The hot electron bombardment method is a method of heating the first furnace body 1 by irradiating the first furnace body 1 with hot electrons in vacuum. The high-frequency heating method is a method of applying a high-frequency wave to the first furnace 1 to heat the first furnace 1 itself. The resistance heating method heats the resistance heating method of the first furnace body 1 by radiation from a heater. The lamp heating method is a method of heating the first furnace body 1 with a lamp.

When annealing is performed, the inside of the first furnace body 1 reaches a high temperature of 1600-2000 ℃. The first furnace body 1 is thus preferably a graphite furnace body.

As shown in fig. 1 to 4, at least two chip containers 3 are provided inside the second furnace body 2, and a housing chamber 31 for housing chips is provided inside the chip containers 3.

At least two chip containers 3 are arranged in sequence along the height direction of the second furnace body 2, and a gap is reserved between two adjacent chip containers 3.

As shown in fig. 1 to 4, the bottom surface of the interior of the first furnace body 1 is provided with a support member 4, and the support member 4 is connected to the bottom plate 11 of the second furnace body 2.

As shown in fig. 1-4, the contact area of the support 4 with the second furnace body 2 is less than 30% of the contact area of the support 4 with the first furnace body 1.

The thickness of the first furnace body 1 is more than 2mm and less than 10mm. In the case of high-frequency heating, the thickness of the first furnace 1 is preferably 2mm or more, and more preferably 3mm or more. The first furnace body 1 can fully absorb heat through the thickness setting of the first furnace body 1, so that the second furnace body 2 can also obtain heat, and the temperature distribution of the heating space inside the second furnace body 2 is ensured to be uniform.

In the case where the heating by the heating device is not high-frequency heating, the thickness of the first furnace body 1 is preferably 10mm or less, more preferably 5mm or less. When the thickness of the first furnace body 1 is reduced, the heat capacity of the first furnace body 1 is reduced. Therefore, the heating and cooling speeds of the first furnace body 1 are increased. The faster the heating/cooling rate, the shorter the time required for the annealing process.

In the present embodiment, since the bottom plate 11, the side plate 12, and the cover of the first furnace 1 are different in thickness, the thickness of the first furnace 1 refers to the average thickness of the bottom plate 11, the side plate 12, and the cover.

In other embodiments, the bottom plate 11, the side plate 12, and the cover of the first furnace 1 are the same in thickness, so the thickness of the first furnace 1 refers to the thickness of the bottom plate 11, or the thickness of the side plate 12, or the thickness of the cover.

As shown in fig. 1 to 4, a temperature measuring hole 5 is provided on the first furnace body 1, and the temperature measuring hole 5 is used for connecting a temperature measuring device to measure the temperature of the first furnace body 1.

Wherein the diameter of the temperature measuring hole 5 is not less than 2mm. The diameter of the temperature measuring hole 5 is preferably 2.5mm, and the temperature measurement can be better ensured by the diameter setting of the temperature measuring hole 5.

As shown in fig. 1 to 4, the chip container 3 includes a placement stage 32 and an upper cover 33, one of the placement stage 32 and the upper cover 33 is provided with a projection 331, and the other is provided with a recess 321, and the projection 331 is adapted to the recess 321 to achieve detachable connection of the placement stage 32 and the upper cover 33. Before annealing, the upper cover 33 is opened to place the chip on the placing table 32; when annealing is performed, the upper cover 33 is connected with the placing table 32 to realize sealing of the chip container 3, so that the annealing of the chip in a sealed environment is ensured, the heating uniformity of the chip is ensured, and the production efficiency of the chip is improved.

In one embodiment, the placement stage 32 is provided with a protrusion 331, the upper cover 33 is provided with a recess 321, and the protrusion 331 is adapted to the recess 321 to achieve a detachable connection of the placement stage 32 and the upper cover 33.

In another embodiment, the placement stage 32 is provided with a recess 321, the upper cover 33 is provided with a protrusion 331, and the protrusion 331 is adapted to the recess 321 to achieve a detachable connection of the placement stage 32 and the upper cover 33.

As shown in fig. 1 to 4, a plurality of mounting grooves are formed in the side portion of the second furnace body 2, and the mounting grooves are adapted to the chip container 3 for embedding the chip container 3 into the mounting grooves. The chip container 3 is embedded in the second furnace body 2 through the mounting groove, the mounting structure is convenient and simple, and the embedded mounting is convenient for replacing the chip container 3 subsequently.

The side of the second furnace body 2 is a plurality of panels, and two adjacent panels in the plurality of panels are detachably connected to form the side of the second furnace body 2. The side part of the second furnace body 2 consists of a plurality of detachable panels and the embedded connection between the chip container 3 and the second furnace body 2 is realized, so that the second furnace body 2 and the chip container 3 are convenient to disassemble and assemble and replace.

As shown in fig. 5, the comparative example is a conventional heat treatment apparatus for semiconductors, and the heating of the chip is directly achieved by heat conduction from one furnace body; an embodiment is a heat treatment apparatus for a semiconductor using the present utility model. The difference in temperature between the upper and lower surfaces of the second furnace body at the time of the temperature rise in the annealing treatment of the example was measured. Since the comparative example has only one furnace body, the temperature difference between the upper and lower surfaces of the chip container of the comparative example was measured.

In the embodiment, the difference in temperature between the upper and lower surfaces of the second furnace body during the annealing treatment is 10 ℃ or less. In the comparative example, the difference in temperature between the upper and lower surfaces of the chip container during the annealing treatment was 100℃or higher. Therefore, the heat of the first furnace body is conducted through the second furnace body, so that the heat distribution of the second furnace body is more uniform, the temperature difference of the chip container in the second furnace body is small, the annealing treatment of a plurality of semiconductor chips is realized at the same time, and the production efficiency of the chips is improved.

In various embodiments of the utility model, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B or may include both a and B.

Expressions (such as "first", "second", etc.) used in the various embodiments of the utility model may modify various constituent elements in the various embodiments, but the respective constituent elements may not be limited. For example, the above description does not limit the order and/or importance of the elements. The above description is only intended to distinguish one element from another element. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present utility model.

It should be noted that: in the present utility model, unless explicitly specified and defined otherwise, terms such as "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium; may be a communication between the interiors of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present utility model, it should be understood by those of ordinary skill in the art that the terms indicating an orientation or a positional relationship are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of description and simplicity of description, not to indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the utility model.

The terminology used in the various embodiments of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the utility model. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the utility model belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the utility model.

Claims (10)

1. A heat treatment apparatus for a semiconductor, comprising: the device comprises a first furnace body and a second furnace body, wherein the first furnace body is used for being in butt joint with a heating device so as to heat the first furnace body through the heating device;

the second furnace body is positioned in the first furnace body and is used for butting heat conducted by the first furnace body;

the second furnace body is internally provided with a chip heating space, and the chip heating space conducts heat through the second furnace body so as to heat at least two chips.

2. The heat treatment apparatus for a semiconductor according to claim 1, wherein at least two chip containers having a housing chamber for housing chips are provided inside the second furnace body.

3. The heat treatment apparatus for semiconductors according to claim 2, wherein at least two of the chip containers are disposed in order along a height direction of the second furnace body, and a gap is reserved between adjacent two of the chip containers.

4. The heat treatment apparatus for a semiconductor according to claim 1, wherein a bottom surface of an interior of the first furnace body is provided with a support member, the support member being connected to a bottom of the second furnace body.

5. The heat treatment apparatus for a semiconductor according to claim 4, wherein a contact area of the support member with the second furnace body is less than 30% of a contact area of the support member with the first furnace body.

6. The heat treatment apparatus for a semiconductor according to claim 1, wherein the thickness of the first furnace body is greater than 2mm and less than 10mm.

7. The heat treatment apparatus for a semiconductor according to claim 1, wherein a temperature measuring hole is provided on the first furnace body, the temperature measuring hole being for connecting a temperature measuring device to measure a temperature of the first furnace body.

8. The heat treatment apparatus for a semiconductor according to claim 7, wherein the diameter of the temperature measurement hole is not less than 2mm.

9. The heat treatment apparatus for a semiconductor according to claim 2, wherein the chip container includes a placement stage and an upper cover, one of the placement stage and the upper cover is provided with a protruding portion, and the other is provided with a recessed portion, the protruding portion being adapted to the recessed portion to achieve detachable connection of the placement stage and the upper cover.

10. The heat treatment apparatus for a semiconductor according to claim 2, wherein a plurality of mounting grooves are provided on a side portion of the second furnace body, the mounting grooves being adapted to the chip container for embedding the chip container therein.