CN220107949U - Solar cell edge-wrapping debugging sample wafer - Google Patents
Solar cell edge-wrapping debugging sample wafer Download PDFInfo
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- CN220107949U CN220107949U CN202321397897.7U CN202321397897U CN220107949U CN 220107949 U CN220107949 U CN 220107949U CN 202321397897 U CN202321397897 U CN 202321397897U CN 220107949 U CN220107949 U CN 220107949U
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- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000002161 passivation Methods 0.000 claims description 33
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 27
- 238000009957 hemming Methods 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 abstract description 17
- 238000007688 edging Methods 0.000 description 32
- 239000003292 glue Substances 0.000 description 21
- 230000008569 process Effects 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910001369 Brass Inorganic materials 0.000 description 3
- 239000010951 brass Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 239000003637 basic solution Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000013072 incoming material Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Abstract
The utility model discloses a solar cell edge-covering debugging sample wafer, which comprises the following components: a substrate; the first photoresist layer is arranged on one side of the substrate, and a first scale groove group formed by the first photoresist layer is arranged in the edge area of the first photoresist layer; and/or a second photoresist layer, wherein the second photoresist layer is arranged on one side of the substrate far away from the first photoresist layer, and a second scale groove group formed by the second photoresist layer is arranged in the edge area of the second photoresist layer. According to the utility model, the first scale groove group formed by the first photoresist layer is arranged in the edge area of the first photoresist layer of the edge-covering debugging sample wafer, and/or the second scale groove group formed by the second photoresist layer is arranged in the edge area of the second photoresist layer, so that the approximate width of the edge-covering formed on the edge-covering debugging sample wafer can be judged quickly by naked eyes according to the first scale groove group and/or the second scale groove group, the use of a microscope is reduced, time and labor are saved, and the method is very convenient, thereby improving the debugging efficiency.
Description
Technical Field
The utility model relates to the technical field of solar cells, in particular to a solar cell edge-wrapping debugging sample wafer.
Background
The preparation process of the solar cell brass sheet comprises the following steps: cleaning an original silicon wafer, texturing, diffusing a heterojunction, and plating an ITO-PVD copper plating film by PVD. In order to produce a solar cell with copper grid lines, a photoresist layer needs to be printed on a brass sheet. And (3) drying the photosensitive glue printed on the two sides of the brass sheet to form a photosensitive glue layer, exposing the photosensitive glue layer according to a preset grid line pattern, developing to remove the unexposed photosensitive glue region, exposing the copper film, electroplating the exposed copper film region, and depositing grid lines on the copper film.
In actual production, when printing photosensitive glue, if the pattern of the printing screen is slightly larger than or equal to that of the battery piece, glue overflows to the printing table surface, so that the next silicon wafer is stuck or polluted; it may also lead to lamination, chipping, etc. if not found timely. Therefore, the pattern of the screen is slightly smaller than that of the battery piece, and each edge of the battery piece after the printing photosensitive glue is dried can leave a blank area with the width of about 0.1mm, and the photosensitive glue layer is not arranged in the blank area. When the battery piece with the edge area without the photoresist layer is electroplated, copper can be plated on the edge area and the side surface of the battery piece, so that the front side and the back side of the battery piece are conducted and short-circuited, and the battery piece is invalid. In order to avoid this, it is necessary to encapsulate the edge regions of the battery sheet prior to electroplating.
In actual production, under the influence of eccentric difference of the edge wrapping wheel, level difference between platforms, difference of XYZ shaft precision of a manipulator, pressure fluctuation of a glue injection system, edge wrapping parameter requirements, difference of incoming materials of a silicon wafer and the like, the problem that the edge of a battery piece is wrapped in a wrapping straight line which cannot be stabilized, thick wrapping narrow wavy edges and the like can be caused. Such a binding abnormality may adversely affect the subsequent plating process, for example, if the binding is narrow, the binding glue cannot be bonded to the photoresist layer, and a blank area where the binding glue layer is not bonded to the photoresist layer Bian Jiao may grow copper edges during plating, resulting in poor battery cells. If the package is too wide, the exposed areas to be plated are easily covered by the development, resulting in gate breakage. If wavy edges appear during edge wrapping, the two anomalies are easy to exist on the same battery piece at the same time because of wide edge wrapping glue and narrow edge wrapping glue.
Therefore, the battery piece needs to be firstly thrown with the debugging sample piece before the throwing of the edge covering process, and whether the edge covering width of the debugging sample piece is within a reasonable range is checked. In the prior art, after the edge of the debugging sample wafer is finished, a microscope is adopted to measure specific data such as the edge-wrapping width of the debugging sample wafer, and the formally feeding of the battery wafer is carried out after the edge-wrapping test data of the debugging sample wafer is not abnormal. If the first inspection is unqualified, the edging process parameters are required to be adjusted, the new debugging sample wafer is subjected to edging again after the edging process parameters are adjusted, and then the debugging sample wafer subjected to edging is observed again until the debugging is qualified.
However, the existing debugging sample wafer does not consider the debugging requirement of the edge covering process, so that even when the debugging sample wafer is prepared for the edge covering process, the pattern of the normal production wafer is printed, so that the width of the edge covering glue of the debugging sample wafer needs to be observed frequently by a microscope when the parameters of the edge covering process are debugged, and the width of all the edge covering glue of one debugging sample wafer needs to be observed by the microscope for 10-15min, which is very inconvenient.
Disclosure of Invention
The present utility model aims to solve at least one of the technical problems in the related art to some extent. Therefore, the utility model aims to provide a solar cell edge-wrapping debugging sample wafer. According to the utility model, the first scale groove group formed by the first photoresist layer is arranged in the edge area of the first photoresist layer of the edge-covering debugging sample wafer, and/or the second scale groove group formed by the second photoresist layer is arranged in the edge area of the second photoresist layer, so that the approximate width of the edge-covering formed on the edge-covering debugging sample wafer can be judged quickly by naked eyes according to the first scale groove group and/or the second scale groove group, the use of a microscope is reduced, time and labor are saved, and the method is very convenient, thereby improving the debugging efficiency.
In order to achieve the above purpose, the utility model provides a solar cell edge-covering debugging sample wafer. According to an embodiment of the present utility model, the solar cell hemming debugging sample wafer includes:
a substrate;
the first photoresist layer is arranged on one side of the substrate, and a first scale groove group formed by the first photoresist layer is arranged in the edge area of the first photoresist layer;
and/or a second photoresist layer, wherein the second photoresist layer is arranged on one side of the substrate far away from the first photoresist layer, and a second scale groove group formed by the second photoresist layer is arranged in the edge area of the second photoresist layer.
According to the solar cell edge-covering debugging sample wafer, the edge area of the first photosensitive layer of the edge-covering debugging sample wafer is provided with the first scale groove group formed by the first photosensitive layer and/or the edge area of the second photosensitive layer is provided with the second scale groove group formed by the second photosensitive layer, and the approximate width of the edge-covering formed on the edge-covering debugging sample wafer can be judged quickly by naked eyes according to the first scale groove group and/or the second scale groove group, so that the use of a microscope is reduced, time and labor are saved, the use is very convenient, and the debugging efficiency is improved.
In addition, the solar cell edge-covering debugging sample wafer according to the embodiment of the utility model can also have the following additional technical characteristics:
in some embodiments of the utility model, the substrate comprises: a silicon substrate; a first passivation layer and a second passivation layer, wherein the first passivation layer is arranged on one side of the silicon substrate, and the second passivation layer is arranged on one side of the silicon substrate far away from the first passivation layer; the N-type amorphous silicon layer and the P-type amorphous silicon layer are arranged on one side of the first passivation layer far away from the silicon substrate, and the P-type amorphous silicon layer is arranged on one side of the second passivation layer far away from the silicon substrate; the first conductive layer is arranged on one side of the N-type amorphous silicon layer, which is far away from the first passivation layer, and the second conductive layer is arranged on one side of the P-type amorphous silicon layer, which is far away from the second passivation layer; the first metal seed layer is arranged on one side of the first conductive layer far away from the N-type amorphous silicon layer, and the second metal seed layer is arranged on one side of the second conductive layer far away from the P-type amorphous silicon layer; the first photoresist layer is arranged on one side of the first metal seed layer away from the first conductive layer, and/or the second photoresist layer is arranged on one side of the second metal seed layer away from the second conductive layer.
In some embodiments of the present utility model, the first scale groove group includes a first sub-scale groove group, a second sub-scale groove group, a third sub-scale groove group, and a fourth sub-scale groove group, the first sub-scale groove group and the second sub-scale groove group are disposed at opposite ends in a width direction of the solar cell edging adjustment sample sheet, and the first sub-scale groove group and the second sub-scale groove group each extend in a length direction of the solar cell edging adjustment sample sheet, the third sub-scale groove group and the fourth sub-scale groove group are disposed at opposite ends in a length direction of the solar cell edging adjustment sample sheet, and the third sub-scale groove group and the fourth sub-scale groove group each extend in a width direction of the solar cell edging adjustment sample sheet.
In some embodiments of the utility model, the first sub-set of scale grooves, the second sub-set of scale grooves, the third sub-set of scale grooves, and the fourth sub-set of scale grooves each independently comprise 2-7 scale grooves.
In some embodiments of the utility model, the first sub-scale groove set, the third sub-scale groove set, the second sub-scale groove set, and the fourth sub-scale groove set are connected end to end in sequence.
In some embodiments of the present utility model, the second scale groove group includes a fifth sub-scale groove group, a sixth sub-scale groove group, a seventh sub-scale groove group, and an eighth sub-scale groove group, the fifth sub-scale groove group and the sixth sub-scale groove group being disposed at opposite ends in a width direction of the solar cell edging adjustment sample sheet, and the fifth sub-scale groove group and the sixth sub-scale groove group each extending in a length direction of the solar cell edging adjustment sample sheet, the seventh sub-scale groove group and the eighth sub-scale groove group being disposed at opposite ends in a length direction of the solar cell edging adjustment sample sheet, and the seventh sub-scale groove group and the eighth sub-scale groove group each extending in a width direction of the solar cell edging adjustment sample sheet.
In some embodiments of the utility model, the fifth sub-set of scale grooves, the sixth sub-set of scale grooves, the seventh sub-set of scale grooves, and the eighth sub-set of scale grooves each independently comprise 2-7 scale grooves; and/or the fifth sub-scale groove group, the seventh sub-scale groove group, the sixth sub-scale groove group and the eighth sub-scale groove group are connected end to end in sequence.
In some embodiments of the utility model, the spacing between adjacent ones of the scale grooves is 160-200 μm; and/or the width of each scale groove is 18-22 mu m; and/or the depth of the scale groove is 45-55 mu m.
In some embodiments of the present utility model, the outermost distance between the outermost scale groove in the first sub-scale groove group and the adjacent solar cell edge-covering debug sample wafer is 80-120 μm; and/or the outermost distance between the outermost scale groove in the second sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the third sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the fourth sub-scale groove group and the adjacent solar cell edge-wrapping debugging sample wafer is 80-120 mu m.
In some embodiments of the present utility model, the outermost distance between the outermost scale groove in the fifth sub-scale groove group and the adjacent solar cell edge-covering debug sample wafer is 80-120 μm; and/or the outermost distance between the outermost scale groove in the sixth sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the seventh sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the eighth sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
Drawings
The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a cross-sectional view of a solar cell hemming debug coupon according to an embodiment of the present utility model;
fig. 2 is a top view (from the N-side) of a solar cell edging debug coupon according to an embodiment of the utility model;
fig. 3 is a bottom view (viewed from the P-side) of a solar cell edging debug coupon according to an embodiment of the present utility model.
Reference numerals:
101-silicon substrate, 102-first passivation layer, 103-second passivation layer, 104-N amorphous silicon layer, 105-P amorphous silicon layer, 106-first conductive layer, 107-second conductive layer, 108-first metal seed layer, 109-second metal seed layer, 110-first photoresist layer, 111-second photoresist layer, 112-first scale groove set, 112-1-first sub-scale groove set, 112-2-second sub-scale groove set, 112-3-third sub-scale groove set, 112-4-fourth sub-scale groove set, 113-second scale groove set, 113-1-fifth sub-scale groove set, 113-2-sixth sub-scale groove set, 113-3-seventh sub-scale groove set, 113-4-eighth sub-scale groove set.
Detailed Description
Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present utility model and should not be construed as limiting the utility model.
In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present utility model, unless explicitly specified and limited otherwise, terms such as "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present utility model, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
The utility model provides a solar cell edge-covering debugging sample wafer, which refers to the accompanying drawings 1-3, and comprises the following components: a substrate; the first photoresist layer 110, the first photoresist layer 110 is arranged on one side of the substrate, and a first scale groove group 112 formed by the first photoresist layer is arranged in the edge area of the first photoresist layer 110; and/or the second photoresist layer 111, the second photoresist layer 111 is disposed on one side of the substrate far away from the first photoresist layer 110, and a second scale groove group 113 formed by the second photoresist layer is disposed on an edge region of the second photoresist layer 111. Therefore, the first scale groove group 112 formed by the first photoresist layer is arranged at the edge area of the first photoresist layer 110 of the edge-covering debugging sample wafer, and/or the second scale groove group 113 formed by the second photoresist layer is arranged at the edge area of the second photoresist layer 111, so that the approximate width of the edge-covering formed on the edge-covering debugging sample wafer can be rapidly judged by naked eyes according to the first scale groove group 112 and/or the second scale groove group 113, the use of a microscope is reduced, time and labor are saved, and the method is very convenient, thereby improving the debugging efficiency.
The principle that the solar cell edge-covering debugging sample wafer provided by the utility model can realize the beneficial effects is described in detail as follows:
in the prior art, a battery piece needs to be firstly thrown into a debugging sample piece before the material throwing of the edge wrapping process, and whether the edge wrapping width of the debugging sample piece is in a reasonable range is checked. In the prior art, after the edge of the debugging sample wafer is finished, a microscope is adopted to measure specific data such as the edge-wrapping width of the debugging sample wafer, and the formally feeding of the battery wafer is carried out after the edge-wrapping test data of the debugging sample wafer is not abnormal. If the first inspection is unqualified, the edging process parameters are required to be adjusted, the new debugging sample wafer is subjected to edging again after the edging process parameters are adjusted, and then the debugging sample wafer subjected to edging is observed again until the debugging is qualified. However, the existing debugging sample wafer does not consider the debugging requirement of the edge covering process, so that even when the debugging sample wafer is prepared for the edge covering process, the pattern of the normal production wafer is printed, so that the width of the edge covering glue of the debugging sample wafer needs to be observed frequently by a microscope when the parameters of the edge covering process are debugged, and the width of all the edge covering glue of one debugging sample wafer needs to be observed by the microscope for 10-15min, which is very inconvenient.
In order to solve the above-mentioned problems, the present utility model provides a novel solar cell edge-covering debug sample wafer, wherein a first scale groove group 112 formed by a first photoresist layer 110 is arranged in an edge region of the first photoresist layer 110 of the edge-covering debug sample wafer; and/or a second scale groove group 113 formed by the second photoresist layer 111 is arranged in the edge area of the second photoresist layer 111, so that scale groove patterns are formed on the solar cell edge-covering debugging sample wafer, and a person skilled in the art can quickly judge the approximate width of the edge-covering formed on the edge-covering debugging sample wafer according to the first scale groove group 112 and/or the second scale groove group 113 naked eyes, and then quickly adjust edge-covering technological parameters according to the requirement of the cell on the edge-covering width, so that the requirement of the cell on the edge-covering width can be met. When judging the width of borduring that forms on bordure debugging sample wafer, reduced the use of microscope, labour saving and time saving is very convenient to debug efficiency has been improved.
According to some embodiments of the utility model, referring to fig. 1, the substrate includes: a silicon substrate 101; a first passivation layer 102 and a second passivation layer 103, the first passivation layer 102 being disposed on one side of the silicon substrate 101, the second passivation layer 103 being disposed on a side of the silicon substrate 101 remote from the first passivation layer 102; an N-type amorphous silicon layer 104 and a P-type amorphous silicon layer 105, the N-type amorphous silicon layer 104 being disposed on a side of the first passivation layer 102 remote from the silicon substrate 101, the P-type amorphous silicon layer 105 being disposed on a side of the second passivation layer 103 remote from the silicon substrate 101; a first conductive layer 106 and a second conductive layer 107, the first conductive layer 106 being disposed on a side of the N-type amorphous silicon layer 104 away from the first passivation layer 102, the second conductive layer 107 being disposed on a side of the P-type amorphous silicon layer 105 away from the second passivation layer 103; a first metal seed layer 108 and a second metal seed layer 109, the first metal seed layer 108 being disposed on a side of the first conductive layer 106 away from the N-type amorphous silicon layer 104, the second metal seed layer 109 being disposed on a side of the second conductive layer 107 away from the P-type amorphous silicon layer 105; the first photoresist layer 110 is disposed on a side of the first metal seed layer 108 away from the first conductive layer 106, and/or the second photoresist layer 111 is disposed on a side of the second metal seed layer 109 away from the second conductive layer 107. The substrate structure of the solar cell edge-covering adjustment sample wafer is the same as the structure of the solar cell wafer before exposure and development before the first scale groove group 112 and/or the second scale groove group 113 are formed. In the field, defective solar cell pieces are generally used as substrates of solar cell edging debugging sample pieces, and scale groove groups are formed on the substrates of the solar cell edging debugging sample pieces.
Specifically, the specific types of the first passivation layer 102 and the second passivation layer 103 are not particularly limited, and may be, for example, intrinsic amorphous silicon layers, respectively. As some specific examples, the thickness of the first passivation layer 102 may be 3nm to 6nm; and/or the thickness of the second passivation layer 103 may be 3nm to 9nm.
As some specific examples, the thickness of the N-type amorphous silicon layer 104 may be 5nm to 10nm; and/or the thickness of the P-type amorphous silicon layer 105 may be 5nm to 15nm.
In the embodiment of the present utility model, the types of the first conductive layer 106 and the second conductive layer 107 are not particularly limited, and for example, an ITO (indium tin oxide) transparent conductive film may be used, and specific preparation process parameters may refer to the preparation methods of the first conductive layer 106 and the second conductive layer 107 in the related art. As some specific examples, the thicknesses of the first conductive layer 106 and the second conductive layer 107 may be 90nm to 110nm, respectively and independently.
As some specific examples, the thicknesses of the first metal seed layer 108 (e.g., copper seed layer) and the second metal seed layer 109 (e.g., copper seed layer) may each independently be 100nm to 250nm. As some specific examples, the thicknesses of the first photoresist layer 110 and the second photoresist layer 111 may be 45-55 μm, respectively and independently.
In the embodiment of the present utility model, the forming process of the first scale groove group 112 and/or the second scale groove group 113 is as follows:
first, a first photoresist layer 110 is formed on one side of the substrate, and a second photoresist layer 111 is formed on one side of the substrate far from the first photoresist layer 110, then, the non-scale groove area of the edge area of the first photoresist layer 110 is exposed according to the shape of the first scale groove group 112, and/or the non-scale groove area of the edge area of the second photoresist layer 111 is exposed according to the shape of the second scale groove group 113, and a series of crosslinking polymerization reactions occur after the photoresist film is exposed, so that the photoresist film is insoluble in weak alkaline solution. Then using a weakly basic solution (e.g. Na 2 CO 3 Solution) to form grooves and expose the underlying metal seed layer for development purposes, and finally forming the pattern of the first set of scale grooves 112 and/or the second set of scale grooves 113, as shown in fig. 2 and 3.
In embodiments of the present utility model, the depth of the scale groove is equal to the thickness of the photoresist layer, and as some specific examples, the depth of the scale groove may be 45-55 μm.
According to still other embodiments of the present utility model, referring to fig. 2, the first scale groove group 112 includes a first sub-scale groove group 112-1, a second sub-scale groove group 112-2, a third sub-scale groove group 112-3, and a fourth sub-scale groove group 112-4, the first sub-scale groove group 112-1 and the second sub-scale groove group 112-2 are disposed at opposite ends of the solar cell edging adjustment sample sheet in the width direction, and the first sub-scale groove group 112-1 and the second sub-scale groove group 112-2 each extend in the length direction of the solar cell edging adjustment sample sheet, the third sub-scale groove group 112-3 and the fourth sub-scale groove group 112-4 are disposed at opposite ends of the solar cell edging adjustment sample sheet in the length direction, and the third sub-scale groove group 112-3 and the fourth sub-scale groove group 112-4 each extend in the width direction of the solar cell edging adjustment sample sheet. Therefore, the four edges of the N surface of the edge-covering debugging sample wafer are provided with the scale groove groups, so that a technician can conveniently judge the edge-covering width of each edge of the edge-covering debugging sample wafer according to the scale groove groups arranged on each edge, the use of a microscope is reduced, time and labor are saved, and the device is very convenient, and therefore the debugging efficiency is improved.
Further, referring to fig. 2, the first sub-scale groove group 112-1, the third sub-scale groove group 112-3, the second sub-scale groove group 112-2 and the fourth sub-scale groove group 112-4 are connected end to end in this order. Therefore, the edge of the N face of the edge-covering debugging sample wafer is provided with the scale groove groups, and the edge-covering width of the edge-covering debugging sample wafer is further conveniently judged by technicians according to the scale groove groups arranged on the edge.
Further, referring to fig. 2, the first sub-scale groove group 112-1, the second sub-scale groove group 112-2, the third sub-scale groove group 112-3 and the fourth sub-scale groove group 112-4 each independently include 2-7 scale grooves, and the width of each scale groove and the distance between adjacent scale grooves are preset, so that a technician can determine the width of the edging adhesive according to the specific position of the edging adhesive on each scale groove, and the use of the microscope is reduced. As some specific examples, the spacing between adjacent scale grooves may be 160-200 μm; and/or the width of a single scale groove may be 18-22 μm.
According to still other embodiments of the present utility model, referring to fig. 3, the second scale groove group 113 includes a fifth sub-scale groove group 113-1, a sixth sub-scale groove group 113-2, a seventh sub-scale groove group 113-3, and an eighth sub-scale groove group 113-4, the fifth sub-scale groove group 113-1 and the sixth sub-scale groove group 113-2 are disposed at opposite ends of the solar cell edging adjustment sample piece in the width direction, and the fifth sub-scale groove group 113-1 and the sixth sub-scale groove group 113-2 each extend in the length direction of the solar cell edging adjustment sample piece, the seventh sub-scale groove group 113-3 and the eighth sub-scale groove group 113-4 are disposed at opposite ends of the solar cell edging adjustment sample piece in the length direction, and the seventh sub-scale groove group 113-3 and the eighth sub-scale groove group 113-4 each extend in the width direction of the solar cell edging adjustment sample piece. Therefore, the four edges of the P surface of the edge-covering debugging sample wafer are provided with the scale groove groups, so that a technician can conveniently judge the edge-covering width of each edge of the edge-covering debugging sample wafer according to the scale groove groups arranged on each edge, the use of a microscope is reduced, time and labor are saved, and the debugging efficiency is improved.
Further, referring to fig. 3, the fifth sub-scale groove group 113-1, the seventh sub-scale groove group 113-3, the sixth sub-scale groove group 113-2 and the eighth sub-scale groove group 113-4 are connected end to end in this order. Therefore, the edge of the P face of the edge-covering debugging sample wafer is provided with the scale groove groups, and the edge-covering width of the edge-covering debugging sample wafer is further conveniently judged by technicians according to the scale groove groups arranged on the edge.
Further, referring to fig. 3, the fifth sub-scale groove group 113-1, the sixth sub-scale groove group 113-2, the seventh sub-scale groove group 113-3 and the eighth sub-scale groove group 113-4 each independently include 2-7 scale grooves, and the width of each scale groove and the distance between adjacent scale grooves are preset, so that a technician can approximately judge the width of the edging adhesive according to the specific position of the edging adhesive on each scale groove, thereby reducing the use of the microscope. As some specific examples, the spacing between adjacent scale grooves may be 160-200 μm; and/or the width of a single scale groove may be 18-22 μm.
In fig. 1 to 3, the X direction indicates the longitudinal direction or the width direction of the hemming debug sample, the Y direction indicates the width direction or the length direction of the hemming debug sample, and when the X direction indicates the longitudinal direction of the hemming debug sample, the Y direction indicates the width direction of the hemming debug sample. The Z direction represents the thickness direction of the hemming debug sample.
In the embodiment of the utility model, when the photosensitive glue is printed, if the printing screen pattern is a little larger than or equal to the debugging sample wafer, the glue overflows to the printing table surface, so that the next debugging sample wafer is stuck or polluted; it may also lead to lamination, chipping, etc. if not found timely. Therefore, the screen pattern is slightly smaller than the debugging sample wafer, and each edge of the debugging sample wafer after the printing photosensitive glue is dried can leave a blank area with a certain width, and the photosensitive glue layer is not arranged in the blank area. Therefore, a blank area with a certain width is left between the outermost scale groove in each scale groove group and the outermost side of the adjacent edge-covering debugging sample wafer.
Specifically, the outermost distance between the outermost scale groove in the first sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the second sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the third sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m; and/or the outermost distance between the outermost scale groove in the fourth sub-scale groove group and the adjacent solar cell edge-wrapping debugging sample wafer is 80-120 mu m.
Specifically, the outermost scale groove in the fifth sub-scale groove group 113-1 is 80-120 μm away from the outermost side of the solar cell edge-wrapping debugging sample wafer which is close to the outermost scale groove; and/or the outermost scale groove of the sixth sub-scale groove group 113-2 is close to the outermost distance of the solar cell edge-wrapping debugging sample wafer, which is 80-120 mu m; and/or the outermost scale groove of the seventh sub-scale groove group 113-3 is close to the outermost distance of the solar cell edge-wrapping debugging sample wafer, which is 80-120 mu m; and/or the outermost scale groove in the eighth sub-scale groove group 113-4 is close to the outermost distance of the solar cell edge-wrapping debugging sample wafer, which is 80-120 mu m.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present utility model have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the utility model, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the utility model.
Claims (10)
1. The utility model provides a solar cell debugging sample wafer of borduring which characterized in that includes:
a substrate;
the first photoresist layer is arranged on one side of the substrate, and a first scale groove group formed by the first photoresist layer is arranged in the edge area of the first photoresist layer;
and/or a second photoresist layer, wherein the second photoresist layer is arranged on one side of the substrate far away from the first photoresist layer, and a second scale groove group formed by the second photoresist layer is arranged in the edge area of the second photoresist layer.
2. The solar cell hemming debug coupon of claim 1 wherein the substrate comprises:
a silicon substrate;
a first passivation layer and a second passivation layer, wherein the first passivation layer is arranged on one side of the silicon substrate, and the second passivation layer is arranged on one side of the silicon substrate far away from the first passivation layer;
the N-type amorphous silicon layer and the P-type amorphous silicon layer are arranged on one side of the first passivation layer far away from the silicon substrate, and the P-type amorphous silicon layer is arranged on one side of the second passivation layer far away from the silicon substrate;
the first conductive layer is arranged on one side of the N-type amorphous silicon layer, which is far away from the first passivation layer, and the second conductive layer is arranged on one side of the P-type amorphous silicon layer, which is far away from the second passivation layer;
the first metal seed layer is arranged on one side of the first conductive layer far away from the N-type amorphous silicon layer, and the second metal seed layer is arranged on one side of the second conductive layer far away from the P-type amorphous silicon layer;
the first photoresist layer is arranged on one side of the first metal seed layer away from the first conductive layer, and/or the second photoresist layer is arranged on one side of the second metal seed layer away from the second conductive layer.
3. The solar cell hemming debugging sample of claim 2 wherein the first scale groove set comprises a first sub-scale groove set, a second sub-scale groove set, a third sub-scale groove set and a fourth sub-scale groove set, the first sub-scale groove set and the second sub-scale groove set are disposed at opposite ends of the solar cell hemming debugging sample in a width direction, and the first sub-scale groove set and the second sub-scale groove set each extend along a length direction of the solar cell hemming debugging sample, the third sub-scale groove set and the fourth sub-scale groove set are disposed at opposite ends of the solar cell hemming debugging sample in a length direction, and the third sub-scale groove set and the fourth sub-scale groove set each extend along the width direction of the solar cell hemming debugging sample.
4. The solar cell hemming debug coupon of claim 3 wherein the first sub-set of scale slots, the second sub-set of scale slots, the third sub-set of scale slots, and the fourth sub-set of scale slots each independently comprise 2-7 scale slots.
5. The solar cell hemming debugging coupon of claim 3 wherein the first sub-set of scale grooves, the third sub-set of scale grooves, the second sub-set of scale grooves and the fourth sub-set of scale grooves are connected end to end in sequence.
6. The solar cell hemming debugging sample of claim 2 wherein the second set of graduation grooves comprises a fifth sub-set of graduation grooves, a sixth sub-set of graduation grooves, a seventh sub-set of graduation grooves and an eighth sub-set of graduation grooves, the fifth sub-set of graduation grooves and the sixth sub-set of graduation grooves are disposed at opposite ends of the solar cell hemming debugging sample in the width direction, and the fifth sub-set of graduation grooves and the sixth sub-set of graduation grooves each extend along the length direction of the solar cell hemming debugging sample, the seventh sub-set of graduation grooves and the eighth sub-set of graduation grooves are disposed at opposite ends of the solar cell hemming debugging sample in the length direction, and the seventh sub-set of graduation grooves and the eighth sub-set of graduation grooves each extend along the width direction of the solar cell hemming debugging sample.
7. The solar cell hemming debug coupon of claim 6 wherein the fifth sub-set of scale slots, the sixth sub-set of scale slots, the seventh sub-set of scale slots, and the eighth sub-set of scale slots each independently comprise 2-7 scale slots;
and/or the fifth sub-scale groove group, the seventh sub-scale groove group, the sixth sub-scale groove group and the eighth sub-scale groove group are connected end to end in sequence.
8. The solar cell edge-covering adjustment coupon of claim 4 or 7, wherein a spacing between adjacent ones of the scale grooves is 160-200 μm;
and/or the width of each scale groove is 18-22 mu m;
and/or the depth of the scale groove is 45-55 mu m.
9. The solar cell edge-covering adjustment sample wafer according to claim 4, wherein the outermost distance between the scale groove on the outermost side in the first sub-scale groove group and the adjacent solar cell edge-covering adjustment sample wafer is 80-120 μm;
and/or the outermost distance between the outermost scale groove in the second sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m;
and/or the outermost distance between the outermost scale groove in the third sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m;
and/or the outermost distance between the outermost scale groove in the fourth sub-scale groove group and the adjacent solar cell edge-wrapping debugging sample wafer is 80-120 mu m.
10. The solar cell hemming debugging sample according to claim 7 wherein the outermost distance between the outermost scale groove in the fifth sub-scale groove group and the adjacent solar cell hemming debugging sample is 80-120 μm;
and/or the outermost distance between the outermost scale groove in the sixth sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m;
and/or the outermost distance between the outermost scale groove in the seventh sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m;
and/or the outermost distance between the outermost scale groove in the eighth sub-scale groove group and the adjacent solar cell edge-covering debugging sample wafer is 80-120 mu m.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321397897.7U CN220107949U (en) | 2023-06-02 | 2023-06-02 | Solar cell edge-wrapping debugging sample wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321397897.7U CN220107949U (en) | 2023-06-02 | 2023-06-02 | Solar cell edge-wrapping debugging sample wafer |
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| CN220107949U true CN220107949U (en) | 2023-11-28 |
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| CN202321397897.7U Active CN220107949U (en) | 2023-06-02 | 2023-06-02 | Solar cell edge-wrapping debugging sample wafer |
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| Country | Link |
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| CN (1) | CN220107949U (en) |
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