CN220106544U - Wide bandgap semiconductor cornerite trench MOSFET device structure - Google Patents

Abstract

The utility model relates to the technical field of semiconductors, and provides a wide band gap semiconductor cornerite groove MOSFET device structure, which comprises: the device comprises a substrate, a P well region, an N column group, a source P+ region, a source N+ region, a grid, a source and a drain; the P well region is arranged on the upper surface of the substrate, the N column group penetrates through the P well region along the first direction, and the lower end part of the N column group is connected with the upper surface of the substrate; the bottom of the grid is connected to the upper end part of the N column group, and the grid is embedded in the P well region along the first direction; the source electrode P+ regions and the source electrode N+ regions are arranged on the upper surface of the P well region, and the plurality of source electrode P+ regions and the plurality of source electrode N+ regions are arranged at intervals in sequence; the source electrode is arranged on the upper surfaces of the source electrode P+ region and the source electrode N+ region, and the drain electrode is arranged at the bottom of the substrate. The device structure can construct a P well region deeper than the groove, so that the P well region wraps the groove angle, the electric field at the groove angle can be reduced, the N column group can inhibit surge current, and the stability and reliability of the device performance are improved.

Description

Wide bandgap semiconductor cornerite trench MOSFET device structure

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a wide-bandgap semiconductor cornerite groove MOSFET device structure.

Background

Currently, ultra-wide band gap semiconductor materials with a forbidden band width larger than that of silicon carbide (SiC) and gallium nitride (GaN) mainly comprise gallium oxide (Ga) ₂ O ₃ ) Diamond (C), aluminum nitride (AlN), etc., have been considered as an exciting and challenging new field of research due to their superior optical and electrical properties. The large forbidden bandwidth makes the device applicable in many extremely severe environments: in the background of geothermal energy production and oil and gas exploitation, higher drilling speed and lower failure rate can be realized, and the working temperatures of an aluminum plant, a steel plant and a coal and gas fired power plant controlled by an electronic sensor are higher under the high temperature condition, so that the energy efficiency of the industrial processes is improved.

The silicon carbide device can realize P-type doping through ion implantation or epitaxial growth, but materials with larger forbidden band widths than silicon carbide such as gallium nitride, gallium oxide, diamond, aluminum nitride (AlN) and the like are difficult to realize P-type doping through ion implantation, and the P-type doping is generally realized through special processes such as growth epitaxy or oxide and the like.

Trench MOSFETs of wide bandgap semiconductor materials have several problems in practical process fabrication and application:

1. the high electric field of the material drift region causes the electric field on the gate dielectric layer to be very high, and the problem is aggravated at the groove angle, so that the gate dielectric layer is rapidly broken down under high drain voltage, and the electrostatic effect on severe environment and the high-voltage spike tolerance in a circuit are poor;

2. because the wide-bandgap semiconductor power MOSFET is mainly applied to the field of high voltage, high frequency and large current, parasitic parameters in the circuit can cause spike burrs such as overschoot and the like to be generated in the high-frequency switching process, so that instantaneous overvoltage on a current channel of a device is caused, and meanwhile, the loss in the switching process is increased; or a large surge voltage is formed due to a change in power load or the like;

3. the limited ion implantation depth results in many targeted trench gate protection structures and anti-surge designs that are difficult to implement technically.

In summary, the existing MOSFET device does not have the surge voltage self-suppression capability and the overvoltage protection capability, and the suppression and overvoltage protection circuit matched through the external is often delayed in time, so that the high-frequency spike voltage surge in the actual switching process is still borne by the device itself, breakdown failure of the channel region of the device and gradual failure of the ohmic contact region of the gate structure and the electrode sometimes result in the problem of device reliability, and therefore, a new wide bandgap semiconductor MOSFET device structure needs to be designed as a more ideal semiconductor material.

Disclosure of Invention

Based on the expression, the utility model provides a wide-bandgap semiconductor cornering groove MOSFET device structure, so that the surge voltage resistance and overvoltage protection of the existing MOSFET device structure are optimized, and the reliability of the device is improved.

The technical scheme for solving the technical problems is as follows:

the utility model provides a wide bandgap semiconductor cornerite groove MOSFET device structure, comprising: the device comprises a substrate, a P well region, an N column group, a source P+ region, a source N+ region, a grid, a source and a drain;

the P well region is arranged on the upper surface of the substrate, the N column group penetrates through the P well region along the first direction, and the lower end part of the N column group is connected with the upper surface of the substrate;

the bottom of the grid is connected to the upper end part of the N column group, and the grid is embedded in the P well region along the first direction;

the source P+ regions and the source N+ regions are arranged on the upper surface of the P well region, and the source P+ regions and the source N+ regions are sequentially arranged at intervals;

the source electrode is arranged on the upper surfaces of the source electrode P+ region and the source electrode N+ region, and the drain electrode is arranged at the bottom of the substrate.

On the basis of the technical scheme, the utility model can be improved as follows.

Further, the grid electrode comprises a grid electrode dielectric layer, grid electrode silicon and a grid electrode groove;

the grid electrode groove is U-shaped and extends along the first direction;

the grid dielectric layer is arranged on the inner wall side of the grid groove; and the grid silicon is filled in the middle of the grid groove and is in contact with the grid dielectric layer.

Further, the wide bandgap semiconductor wrap-angle groove MOSFET device structure further comprises an interlayer dielectric layer;

the interlayer dielectric layer is covered at the opening of the grid electrode groove, the middle part of the interlayer dielectric layer is contacted with the upper end surfaces of the grid electrode dielectric layer and the grid electrode silicon, and the two end parts of the interlayer dielectric layer are contacted with the source electrode N+ region.

Further, the set of N columns includes a first N column and a second N column;

the first N columns and the second N columns are arranged at intervals along a second direction;

wherein the second direction is perpendicular to the first direction.

Further, the first N column and the second N column each comprise a plurality of N column sections, and a plurality of N column sections are arranged at intervals.

Further, the N column groups are multiple; the N column groups are arranged in the P well region at intervals along the second direction;

the number of the grid electrodes and the interlayer dielectric layers is the same as that of the N column groups, and the grid electrodes and the interlayer dielectric layers are arranged corresponding to the N column groups.

Further, the wide bandgap semiconductor cornering trench MOSFET device structure further comprises a current guiding layer;

the flow guide layer is arranged between the grid groove and the N column group;

the width dimension of the diversion layer along the second direction is smaller than the width dimension of the grid groove; or, the width dimension of the diversion layer along the second direction is larger than the width dimension of the grid groove.

Further, the substrate comprises an N+ substrate layer and an N-epitaxial layer;

the N-epitaxial layer is arranged on the N+ substrate layer;

the P well region is arranged on the upper surface of the N-epitaxial layer, and the drain electrode is arranged on the lower surface of the N+ substrate layer.

Compared with the prior art, the technical scheme of the utility model has the following beneficial technical effects:

the wide-band gap semiconductor wrap angle groove MOSFET device structure is provided with a substrate, a P well region, an N column group, a source electrode P+ region, a source electrode N+ region, a grid electrode, a source electrode and a drain electrode, wherein the P well region is arranged on the upper surface of the substrate, the N column group penetrates through the P well region along a first direction, the lower end part of the N column group is connected with the upper surface of the substrate, the bottom of the grid electrode is connected with the upper end part of the N column group, the grid electrode is embedded in the P well region along the first direction, a P column can be formed in the middle of the N column group, and the arrangement is such that a P well region deeper than a grid electrode groove can be constructed, the P well region wraps the groove angle of the grid electrode groove, a conductive channel is formed through the N column group at the bottom of the grid electrode, and the P column is connected with the P well region so as to be grounded.

Compared with the prior art, the wide bandgap semiconductor cornerite trench MOSFET device structure has the following advantages:

the high electric field of the drift region of the first and the wide forbidden band semiconductor materials causes the electric field on the gate dielectric layer to be very high, and the problem is aggravated at the groove angle, so that the gate dielectric layer is rapidly broken down under high drain voltage, a P well region deeper than the groove is constructed, the P well region wraps the groove angle, and the electric field at the groove angle can be effectively reduced.

Second, the existing MOSFET device itself does not have anti-surge voltage self-suppression capability and overvoltage protection capability, and when surge voltage occurs, the N column group provided by the utility model can fully deplete the region to increase on-resistance and suppress surge current.

Third, the effect of superjunction can appear when reaching charge balance between N post group and the P well/P post, and the electric field in the N post group can evenly distributed, can reduce on resistance when improving breakdown voltage.

In conclusion, the wide band gap semiconductor wrap angle groove MOSFET device structure provided by the utility model can effectively improve the stability and reliability of the device performance.

Drawings

Fig. 1 is a schematic three-dimensional structure diagram of a wide bandgap semiconductor corner trench MOSFET device structure according to an embodiment of the utility model;

fig. 2 is a schematic cross-sectional structure diagram of a wide bandgap semiconductor corner trench MOSFET device structure at a cross-section a according to an embodiment of the utility model;

fig. 3 is a schematic charge balance diagram of a wide bandgap semiconductor corner trench MOSFET device structure according to a first embodiment of the utility model;

fig. 4 is a schematic three-dimensional structure diagram of a wide bandgap semiconductor corner trench MOSFET device structure according to a second embodiment of the utility model;

fig. 5 is a schematic diagram of a cross-sectional structure of a wide bandgap semiconductor corner trench MOSFET device structure according to a second embodiment of the utility model;

FIG. 6 is a schematic diagram of a different section of N-pillar connection structure according to a second embodiment of the present utility model;

FIG. 7 is a second schematic diagram of a different section of N-pillar connection structure according to the second embodiment of the present utility model;

FIG. 8 is a third schematic diagram of an N-pillar connection structure of a second embodiment of the present utility model;

FIG. 9 is a diagram showing a second embodiment of the present utility model for providing a different section of N-pillar connection structure;

FIG. 10 is a fifth schematic diagram of a different section of N-pillar connection structure according to the second embodiment of the present utility model;

FIG. 11 is a diagram showing a second embodiment of the present utility model for a different section of N-pillar connection structure;

fig. 12 is a schematic three-dimensional structure diagram of a wide bandgap semiconductor corner trench MOSFET device structure according to a third embodiment of the utility model;

fig. 13 is a schematic cross-sectional structure diagram of a wide bandgap semiconductor corner trench MOSFET device structure according to a third embodiment of the utility model;

FIG. 14 is one of the schematic N-pillar connecting structures of the different sections according to the third embodiment of the present utility model;

FIG. 15 is a second schematic view of a different section of N-pillar connection structure according to the third embodiment of the present utility model;

FIG. 16 is a third schematic view of an N-pillar connection structure of a different section according to the third embodiment of the present utility model;

FIG. 17 is a fourth schematic diagram of a different section of N-pillar connection structure according to the third embodiment of the present utility model;

FIG. 18 is a fifth schematic diagram of a different section of N-pillar connection structure according to the third embodiment of the present utility model;

FIG. 19 is a diagram showing a connection structure of N columns in different sections according to a third embodiment of the present utility model;

fig. 20 is a schematic diagram of a manufacturing method of a wide bandgap semiconductor corner trench MOSFET device structure provided by the present utility model;

reference numerals:

1. a substrate; 101. an n+ substrate layer; 102. n-epitaxial layer

2. A P well region; 201. a P column;

3. an N column group; 301. a first N column; 302. a second N column;

4. a source p+ region;

5. a source n+ region;

6. a gate; 601. a gate dielectric layer; 602. gate silicon; 603. a gate trench;

7. a source electrode;

8. a drain electrode;

9. an interlayer dielectric layer;

10. and a diversion layer.

Detailed Description

In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. Embodiments of the utility model are illustrated in the accompanying drawings. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

SiC and GaN are third generation wide bandgap semiconductor materials, and are more advantageous than Si in terms of physical characteristics such as bandgap width, breakdown field strength, electron saturation drift velocity, etc., and the prepared power devices such as diodes, transistors and power modules have more excellent electrical characteristics, can overcome the defect that silicon-based cannot meet application requirements of high power, high voltage, high frequency, high temperature, etc., and are one of breakthrough paths beyond moore's law, so that the SiC and GaN are widely applied to new energy fields (photovoltaic, energy storage, charging piles, electric vehicles, etc.).

Ultra-wide band gap semiconductor materials with a forbidden band width larger than that of SiC and GaN, mainly include gallium oxide (Ga 2O 3), diamond (C), aluminum nitride (AlN), etc., and have been considered as an exciting and challenging new research field due to their superior optical and electrical properties.

In power switching applications, the Balga's figure-of-merit (BFOM) is an indicator used to represent the applicability of semiconductor materials in terms of power electronics, expressed as: BFOM = epsilon μe ³ Where ε is the dielectric constant, μ is the mobility, E is the breakdown field strength of the semiconductor, and the BFOM value is approximately related to six times Fang Chengzheng of the forbidden band width Eg. Therefore, a larger forbidden bandwidth means that the wide bandgap semiconductor has lower power loss and higher conversion efficiency in power device applications, thereby achieving more excellent and ideal power electronics applications.

Ga in wide bandgap semiconductor material ₂ O ₃ Having a forbidden band width of 4.8eV, an ideal breakdown field strength of 8MV/cm and a BFOM value of up to 3400About 4 times that of GaN and 10 times that of SiC. Ga is therefore in power electronics applications today with higher power density and lower power consumption requirements ₂ O ₃ The material has more important research significance and wider market application prospect.

The anti-surge voltage self-inhibition capability and the overvoltage protection capability are important indexes for measuring the performance of the MOSFET device, however, the trench MOSFET of the wide bandgap semiconductor material does not have the anti-surge voltage self-inhibition capability and the overvoltage protection capability, and a complex buffer circuit, a surge voltage inhibition circuit and an overvoltage protection circuit are often required to be designed in practical application.

However, such external matching suppression and overvoltage protection circuits often have time delays, and high-frequency spike voltage surges in the actual switching process are still borne by the device itself, sometimes resulting in breakdown failure of the device channel region, and gradual failure of the gate structure and electrode ohmic contact region, leading to device reliability problems.

The present utility model provides a wide bandgap semiconductor corner trench MOSFET device structure, which can effectively solve the above-mentioned problems, and the following embodiments of the present utility model are described in further detail with reference to the accompanying drawings and examples, which are provided for illustrating the present utility model, but are not intended to limit the scope of the present utility model.

Example 1

As shown in fig. 1 and 2, the wide bandgap semiconductor corner trench MOSFET device structure provided in this embodiment is composed of a substrate 1, a P-well region 2, an N pillar group 3, a source p+ region 4, a source n+ region 5, a gate 6, a source 7 and a drain 8.

Wherein the substrate 1 comprises an n+ substrate layer 101 and an N-epitaxial layer 102; an N-epitaxial layer 102 is provided on the n+ substrate layer 101.

The P-well region 2 is disposed on the upper surface of the N-epi layer 102, and the drain electrode 8 is disposed on the lower surface of the n+ substrate layer 101.

The P well region 2 is arranged on the upper surface of the substrate 1, the N column group 3 penetrates through the P well region 2 along the first direction, and the lower end part of the N column group 3 is connected with the upper surface of the substrate 1.

The bottom of the gate 6 is connected to the upper end of the N pillar set 3, and the gate 6 is embedded in the P-well region 2 along the first direction. The width direction of the structure in fig. 1 is defined as the first direction.

Wherein the N column set 3 comprises a first N column 301 and a second N column 302; the first N-pillar 301 and the second N-pillar 302 are spaced apart along the second direction.

Wherein the second direction is perpendicular to the first direction. The length direction of the structure in fig. 1 is defined as the second direction.

The first N-pillar 301 and the second N-pillar 302 each include a plurality of N-pillar segments that are spaced apart. As shown in fig. 1, in an alternative example, the number of N column segments may be 2, and the 2N column segments are spaced apart by a certain distance, where the distance between the two segments is not limited, and may be set according to actual needs.

Further, as shown in fig. 1, the source p+ region 4 and the source n+ region 5 are both disposed on the upper surface of the P-well region 2, and the plurality of source p+ regions 4 and the plurality of source n+ regions 5 are sequentially disposed at intervals. The specific number and spacing distance of the source p+ regions 4 and the source n+ regions 5 are not particularly limited herein, and may be set according to actual needs, and various arrangements capable of satisfying the functions of the present utility model may fall within the scope of the present utility model.

The source electrode 7 is arranged on the upper surfaces of the source electrode P+ region 4 and the source electrode N+ region 5, and the drain electrode 8 is arranged at the bottom of the substrate 1.

Further, as shown in fig. 1, the gate 6 includes a gate dielectric layer 601, gate silicon 602, and gate trenches 603.

As shown in fig. 2, the gate trench 603 has a U shape and extends in the first direction.

The gate dielectric layer 601 is arranged on the inner wall side of the gate groove 603; gate silicon 602 fills the middle of gate trench 603 and contacts gate dielectric layer 601.

Further, as shown in fig. 1, the wide bandgap semiconductor corner trench MOSFET device structure further includes an interlayer dielectric layer 9, where the interlayer dielectric layer 9 is disposed at the opening of the gate trench 603 in a covering manner, and the middle portion of the interlayer dielectric layer is in contact with the gate dielectric layer 601 and the upper end surface of the gate silicon 602, and the two end portions of the interlayer dielectric layer are in contact with the source n+ region 5.

As shown in fig. 1, the N column groups 3 are plural; the plurality of N column groups 3 are arranged in the P well region 2 at intervals along the second direction; the description will be given here taking 3N column groups 3 as an example. Each of the N column groups 3 includes two N columns with a P column 201 formed therebetween.

Correspondingly, the number of the grid electrodes 6 and the interlayer dielectric layers 9 is the same as that of the N column groups 3, and the number of the grid electrodes and the interlayer dielectric layers is 3, and the grid electrodes and the interlayer dielectric layers are arranged in one-to-one correspondence with the N column groups 3.

The wide-bandgap semiconductor wrap-angle groove MOSFET device structure provided by the embodiment of the utility model is provided with a substrate 1, a P-well region 2, an N-column group 3, a source P+ region 4, a source N+ region 5, a grid electrode 6, a source electrode 7 and a drain electrode 8, wherein the P-well region 2 is arranged on the upper surface of the substrate 1, the N-column group 3 is penetrated in the P-well region 2 along a first direction, the lower end part of the N-column group 3 is connected with the upper surface of the substrate 1, the bottom of the grid electrode 6 is connected with the upper end part of the N-column group 3, the grid electrode 6 is embedded in the P-well region 2 along the first direction, a P-column 201 can be formed in the middle of the N-column group 3, and the arrangement can be used for constructing the P-well region 2 deeper than the grid electrode groove 603, so that the P-well region 2 wraps the groove angle of the grid electrode groove 603, a conductive channel is formed by the N-column group 3 at the bottom of the grid electrode 6, and the P-column 201 is connected with the P-well region 2 through the P-well region 2 so as to be grounded.

Compared with the prior art, the charge balance schematic diagram of the wide bandgap semiconductor cornering trench MOSFET device structure shown in FIG. 3 has the following advantages:

the high electric field of the drift region of the first and the wide forbidden band semiconductor materials causes the electric field on the gate dielectric layer to be very high, and the problem is aggravated at the groove angle, so that the gate dielectric layer is rapidly broken down under high drain voltage, the P well region 2 deeper than the groove is constructed, the P well region 2 wraps the groove angle, and the electric field at the groove angle can be effectively reduced.

Second, the existing MOSFET device itself does not have anti-surge voltage self-suppression capability and overvoltage protection capability, and when surge voltage occurs, the N column group 3 provided in the embodiment of the present utility model can fully deplete the region to increase on-resistance and suppress surge current.

Third, the effect of superjunction will occur when the charge balance between the N column group 3 and the P well/P column 201 is achieved, the electric field in the N column group 3 can be uniformly distributed, and the breakdown voltage can be improved while the on-resistance can be reduced.

In summary, the wide bandgap semiconductor cornerite trench MOSFET device structure provided by the embodiment of the utility model can effectively improve the stability and reliability of the device performance.

Example two

On the basis of the first embodiment, as shown in fig. 4 and 5, the wide bandgap semiconductor corner trench MOSFET device structure further includes a current guiding layer 10; the guiding layer 10 is disposed between the gate trench 603 and the N pillar set 3, and a width dimension of the guiding layer 10 along the second direction is smaller than a width dimension of the gate trench 603.

In a specific example, an N-type current guiding layer 10 is added between N pillars at the bottom of the trench, where the N-type current guiding layer 10 can enable two N-pillar conductive channels to be mutually communicated, further reduce on-resistance, define the width of the trench as W1, and the width of the current guiding layer 10 as W2, and when W1 is greater than W2, the structure is shown in fig. 4.

On the basis of the above structure, the arrangement among the N pillar, the guiding layer 10, and the gate trench 603 may have the following cases:

1. one or more of the guiding layers 10 may be provided along a length of the N pillar extending in the gate trench 603 (first direction), as shown in fig. 6, for example, 2 guiding layers 10 are provided on any one of the N pillar sections.

2. The N pillars along the extending direction of the gate trench 603 may have a diversion layer 10 at intervals of one N pillar section or multiple N pillar sections, as shown in fig. 7, the N pillar sections have three sections, where no diversion layer 10 is disposed on the N pillar section at one end in the middle, and the other two sections are provided with diversion layers 10.

3. The N columns of different sections can also be connected through the flow guide layer 10, as shown in fig. 8, only the adjacent N column sections on one side are connected through the flow guide layer 10; as shown in fig. 9, adjacent N column sections on both sides are connected by a guide layer 10; as shown in fig. 10, the left (upper) N column section is connected to the right (lower) N column section by a guide layer 10; as shown in fig. 11, the left N column segments are connected to the right N column segments in a staggered manner by the guide layer 10.

Example III

On the basis of the first embodiment, as shown in fig. 12 and 13, the wide bandgap semiconductor corner trench MOSFET device structure further includes a current guiding layer 10; the guiding layer 10 is disposed between the gate trench 603 and the N pillar set 3, and a width dimension of the guiding layer 10 along the second direction is greater than a width dimension of the gate trench 603. The opening of the corners of the channel with the deflector layer 10 can further reduce the on-resistance.

In a specific example, an N-type current guiding layer 10 is added between N pillars at the bottom of the trench, where the N-type current guiding layer 10 can enable two N-pillar conductive channels to be mutually communicated, further reduce on-resistance, define the width of the trench as W1, and the width of the current guiding layer 10 as W2, and when W1 is smaller than W2, the structure is shown in fig. 12.

On the basis of the above structure, the arrangement among the N pillar, the guiding layer 10, and the gate trench 603 may have the following cases: (the same arrangement as in the second embodiment is described briefly herein and will not be repeated here

1. A length of the N pillar along the direction in which the gate trench 603 extends (first direction) may have one or more conductive layers 10, as shown in fig. 14.

2. The N pillars along the extending direction of the gate trench 603 may be separated by one N pillar segment or multiple N pillar segments, and the guiding layer 10 is shown in fig. 15.

3. The N columns of different sections can also be connected by a flow guiding layer 10, as shown in FIGS. 16-19.

Taking the wide bandgap semiconductor corner trench MOSFET device structure of the first embodiment as an example, for convenience of understanding, as shown in fig. 20, a method for manufacturing the MOSFET device structure is further provided, including:

step S1: and growing an N-epitaxial layer on the N+ substrate layer to obtain the substrate.

Step S2: and manufacturing a P-type oxide on the N-epitaxial layer to obtain a P-well region.

Step S3: and manufacturing a source electrode P+ region and a source electrode N+ region on the P well region.

Step S4: and carrying out dry etching on the P well region, the source P+ region and the source N+ region to obtain a gate trench.

Step S5: and carrying out ion implantation on the P well region at the bottom of the grid electrode groove to obtain the N column group.

Step S6: and sequentially carrying out gate dielectric growth, gate silicon growth and interlayer dielectric deposition on the gate trench to obtain the gate.

Step S7: depositing metal on the upper surfaces of the source P+ region and the source N+ region to manufacture a source; and depositing metal on the lower surface of the N+ substrate layer to manufacture a drain electrode.

The manufacturing method is used for manufacturing the wide-bandgap semiconductor cornering groove MOSFET device structure, so that the beneficial effects of the wide-bandgap semiconductor cornering groove MOSFET device structure are also applicable to the manufacturing method, and the beneficial effects of the wide-bandgap semiconductor cornering groove MOSFET device structure can be referred to as embodiment one and are not described in detail herein.

In the description of the present specification, reference to the term "a particular example" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the utility model. In this specification, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims (8)

1. A wide bandgap semiconductor corner trench MOSFET device structure comprising: the device comprises a substrate, a P well region, an N column group, a source P+ region, a source N+ region, a grid, a source and a drain;

the P well region is arranged on the upper surface of the substrate, the N column group penetrates through the P well region along the first direction, and the lower end part of the N column group is connected with the upper surface of the substrate;

the bottom of the grid is connected to the upper end part of the N column group, and the grid is embedded in the P well region along the first direction;

the source P+ regions and the source N+ regions are arranged on the upper surface of the P well region, and the source P+ regions and the source N+ regions are sequentially arranged at intervals;

the source electrode is arranged on the upper surfaces of the source electrode P+ region and the source electrode N+ region, and the drain electrode is arranged at the bottom of the substrate.

2. The wide bandgap semiconductor corner trench MOSFET device structure of claim 1, wherein said gate comprises a gate dielectric layer, gate silicon and gate trenches;

the grid electrode groove is U-shaped and extends along the first direction;

the grid dielectric layer is arranged on the inner wall side of the grid groove; and the grid silicon is filled in the middle of the grid groove and is in contact with the grid dielectric layer.

3. The wide bandgap semiconductor corner trench MOSFET device structure of claim 2, further comprising an interlayer dielectric layer;

the interlayer dielectric layer is covered at the opening of the grid electrode groove, the middle part of the interlayer dielectric layer is contacted with the upper end surfaces of the grid electrode dielectric layer and the grid electrode silicon, and the two end parts of the interlayer dielectric layer are contacted with the source electrode N+ region.

4. The wide bandgap semiconductor corner trench MOSFET device structure of claim 3, wherein said set of N pillars comprises a first N pillar and a second N pillar;

the first N columns and the second N columns are arranged at intervals along a second direction;

wherein the second direction is perpendicular to the first direction.

5. The wide bandgap semiconductor corner trench MOSFET device structure of claim 4, wherein said first N pillar and said second N pillar each comprise a plurality of N pillar segments, a plurality of said N pillar segments being spaced apart.

6. The wide bandgap semiconductor corner trench MOSFET device structure of claim 4, wherein said group of N pillars is a plurality; the N column groups are arranged in the P well region at intervals along the second direction;

the number of the grid electrodes and the interlayer dielectric layers is the same as that of the N column groups, and the grid electrodes and the interlayer dielectric layers are arranged corresponding to the N column groups.

7. The wide bandgap semiconductor corner trench MOSFET device structure of claim 4, further comprising a current guiding layer;

the flow guide layer is arranged between the grid groove and the N column group;

the width dimension of the diversion layer along the second direction is smaller than the width dimension of the grid groove; or, the width dimension of the diversion layer along the second direction is larger than the width dimension of the grid groove.

8. The wide bandgap semiconductor corner trench MOSFET device structure of claim 1, wherein said substrate comprises an n+ substrate layer and an N-epitaxial layer;

the N-epitaxial layer is arranged on the N+ substrate layer;

the P well region is arranged on the upper surface of the N-epitaxial layer, and the drain electrode is arranged on the lower surface of the N+ substrate layer.