CN220065703U - Enhancement type gallium oxide transistor - Google Patents
Enhancement type gallium oxide transistor Download PDFInfo
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- CN220065703U CN220065703U CN202321399381.6U CN202321399381U CN220065703U CN 220065703 U CN220065703 U CN 220065703U CN 202321399381 U CN202321399381 U CN 202321399381U CN 220065703 U CN220065703 U CN 220065703U
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- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 77
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000313 electron-beam-induced deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The utility model discloses an enhanced gallium oxide transistor, which comprises: a substrate and a gallium oxide epitaxial layer disposed on the substrate; one end of the gallium oxide epitaxial layer is provided with an electrode growth step, and the electrode growth step penetrates through the gallium oxide epitaxial layer; the source electrode is arranged on the electrode growth step and extends out of the gallium oxide epitaxial layer; the drain electrode is arranged on the gallium oxide epitaxial layer; the gate dielectric layer is arranged in a gate position area of the gallium oxide epitaxial layer; the gate dielectric layer is positioned between the source electrode and the drain electrode; and the gate electrode is arranged on the gate dielectric layer. The device has the characteristic of normal closing, simple structure and lower cost.
Description
Technical Field
The utility model relates to the technical field of microelectronics, in particular to an enhanced gallium oxide transistor.
Background
Ga 2 O 3 Is a novel semiconductor material with excellent characteristics of ultra-wide forbidden band width, ultra-high critical breakdown field strength and the like, and Ga 2 O 3 Under the same voltage withstand condition as the GaN and SiC devices, the power device has the advantages of lower on-resistance and lower power consumption, can greatly reduce the electric energy loss during the operation of the device, and has the triple advantages of high breakdown, low on-resistance and low cost.
At present, internationally match Ga 2 O 3 Research on base MOSFETs has focused mainly on depletion mode devices, but normally-on Ga 2 O 3 The transistor has a potential safety hazard in operation, and thus a normally-off device having a positive threshold voltage Vth needs to be developed. However, existing technologies such as p-NiO cap technology may introduce a comparisonMultiple gate defects, which further cause unstable threshold voltage, limit Ga 2 O 3 Application of transistors. Thus, there is a need for a more efficient Ga 2 O 3 Enhancement device solution for transistors.
Disclosure of Invention
Accordingly, in order to solve the above-described problems, the present utility model provides an enhanced gallium oxide transistor.
The utility model provides an enhanced gallium oxide transistor, which comprises:
a substrate and a gallium oxide epitaxial layer disposed on the substrate; one end of the gallium oxide epitaxial layer is provided with an electrode growth step, and the electrode growth step penetrates through the gallium oxide epitaxial layer;
the source electrode is arranged on the electrode growth step and extends out of the gallium oxide epitaxial layer;
the drain electrode is arranged on the gallium oxide epitaxial layer;
the gate dielectric layer is arranged in a gate position area of the gallium oxide epitaxial layer; the gate dielectric layer is positioned between the source electrode and the drain electrode;
and the gate electrode is arranged on the gate dielectric layer.
In one possible implementation, the electrode growth step also extends into the substrate.
In one possible implementation, the gallium oxide epitaxial layer is a beta-type gallium oxide epitaxial layer.
In one possible implementation, the source electrode includes a first sub-electrode and a second sub-electrode, and the second sub-electrode has a size smaller than the first sub-electrode; the first sub-electrode is arranged on the electrode growth step, and the second sub-electrode is arranged on the first sub-electrode; the gate dielectric layer also extends to cover the exposed surface of the first sub-electrode.
In one possible implementation, a portion of the gate electrode spans the first sub-electrode.
In one possible implementation, the drain electrode includes a third sub-electrode and a fourth sub-electrode, and the fourth sub-electrode has a size smaller than the size of the third sub-electrode; the third sub-electrode is arranged on the gallium oxide epitaxial layer, and the fourth sub-electrode is arranged on the third sub-electrode; the gate dielectric layer also extends to cover the exposed surface of the third sub-electrode.
In one possible implementation, the substrate is a gallium oxide substrate.
In one possible implementation, the gallium oxide epitaxial layer is a Cu-doped beta-type gallium oxide epitaxial layer, and the Cu doping concentration therein is 1×10 16 ～1×10 18 cm -3 Between them.
The technical scheme provided by the utility model has the following advantages:
according to the enhanced gallium oxide transistor provided by the utility model, the electrode growth step penetrating through the gallium oxide epitaxial layer is arranged at one end of the gallium oxide epitaxial layer to expose the gallium oxide channel, and the source electrode is arranged on the electrode growth step, so that when the device is in zero bias, if positive pressure is applied to the drain electrode, the Schottky junction of the source electrode is reversely biased, no current flows in the channel, and the device is turned off; if a gate voltage higher than a threshold voltage is applied to the gate electrode, the gallium oxide potential of the source electrode Schottky junction is lowered, so that the barrier thickness of the Schottky junction is obviously reduced, electrons can be directly tunneled into a gallium oxide channel from the source electrode metal, and the device is started; and the enhanced device function is realized. And the structure is simple, and the cost is low.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present utility model, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an enhanced gallium oxide transistor according to an embodiment of the present utility model;
reference numerals illustrate:
1-a substrate; a 2-gallium oxide epitaxial layer; 3-source electrode; 3 a-a first sub-electrode; 3 b-a second sub-electrode; 4-drain electrode; 4 a-a third sub-electrode; 4 b-a fourth sub-electrode; 5-gate dielectric layer; 6-gate electrode.
Detailed Description
The following description of the embodiments of the present utility model will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the present utility model, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present utility model and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The present embodiment provides an enhancement mode gallium oxide transistor, as shown in fig. 1, including: substrate 1, gallium oxide epitaxial layer 2, source electrode 3, drain electrode 4, gate dielectric layer 5 and gate electrode 6.
As shown in fig. 1, a gallium oxide epitaxial layer 2 is provided on a substrate 1, and one end of the gallium oxide epitaxial layer 2 is provided with an electrode growth step penetrating the gallium oxide epitaxial layer 2.
Specifically, the substrate 1 may also be a gallium oxide substrate, and in particular, it may be any crystal plane and doped gallium oxide substrate, and its thickness may be between 50 μm and 1000 μm.
Specifically, the gallium oxide epitaxial layer 2 may be a beta-type gallium oxide epitaxial layer 2, such as a Cu-doped beta-type gallium oxide epitaxial layer 2, wherein the Cu doping concentration is 1×10 16 ～1×10 18 cm -3 Between them. In specific implementation, molecular beam epitaxy equipment or vapor phase epitaxy growth equipment can be used for homoepitaxy to complete gallium oxide epitaxyThe layer 2 is provided and the thickness of the gallium oxide epitaxial layer 2 may be provided between 50nm and 600 nm.
Specifically, the electrode growth step may extend through only the gallium oxide epitaxial layer 2, or may extend into the substrate 1 while extending through the gallium oxide epitaxial layer 2 (fig. 1 is shown as an example). In specific implementation, the gallium oxide epitaxial layer 2 may be etched by using an inductively coupled plasma etching process to complete the electrode growth step arrangement, and more specifically, the etching gas may be BCl 3 Ar; of course, the photoresist may be disposed in other areas except the electrode growth step for protection during etching, and acetone, ethanol or deionized water may be used to clean the remaining photoresist after etching the electrode growth step.
As shown in fig. 1, the source electrode 3 is disposed on the electrode growth step and extends out of the gallium oxide epitaxial layer 2, the drain electrode 4 is disposed on the gallium oxide epitaxial layer 2, the gate dielectric layer 5 is disposed in the gate position region of the gallium oxide epitaxial layer 2, the gate dielectric layer 5 is disposed between the source electrode 3 and the drain electrode 4, and the gate electrode 6 is disposed on the gate dielectric layer 5.
Specifically, the source electrode 3 may be provided as a Ni/Au electrode, and in a specific implementation, the source electrode 3 may be provided by using an electron beam deposition process or a magnetron sputtering process, and the thicknesses of the Ni metal layer and the Au metal layer may be respectively between 50nm and 70nm and between 100nm and 140 nm.
Specifically, the drain electrode 4 may be a Ti/Au electrode, and when implemented, the source electrode 3 may be similarly disposed by an electron Beam deposition process or a magnetron sputtering process (more specifically, ti/Au ohmic deposition is performed in an E-Beam or magnetron sputtering PVD apparatus, and then an RTP apparatus is used to perform N 2 The atmosphere is subjected to rapid thermal annealing at 480 ℃ for 60 seconds, and the thicknesses of the Ti metal layer and the Au metal layer can be set to be between 50nm and 70nm and between 100nm and 140nm, respectively.
Specifically, the gate dielectric layer 5 may be Al 2 O 3 Layers or SiO 2 Layers, etc. In particular embodiments, the placement of gate dielectric layer 5 may be accomplished using a Plasma Enhanced Atomic Layer Deposition (PEALD) apparatus toThe gate dielectric layer 5 is Al 2 O 3 For example, the atmosphere in the PEALD apparatus may be set to TMA and H 2 O; similarly, al 2 O 3 RTP equipment can be reused at N after layer deposition is completed 2 Annealing under atmosphere. In specific implementation, the thickness of the gate dielectric layer 5 may be set to be between 5nm and 50 nm.
Specifically, the gate electrode 6 may be any one of a metal layer of Ti, tiN, ni, au, alCu, and the like, or may be a multilayer metal formed by combining two or more of the above. In specific implementation, the preparation of the gate electrode 6 may be completed by using a magnetron sputtering or electron beam evaporation process, and the thickness of the gate electrode 6 may be between 100 μm and 1000 μm.
In one possible implementation, as shown in fig. 1, the source electrode 3 includes a first sub-electrode 3a and a second sub-electrode 3b, and the size of the second sub-electrode 3b is smaller than that of the first sub-electrode 3 a; the first sub-electrode 3a is arranged on the electrode growth step, and the second sub-electrode 3b is arranged on the first sub-electrode 3 a; the gate dielectric layer 5 also extends over the exposed surface of the first sub-electrode 3 a. Specifically, taking the source electrode 3 as the above-mentioned Ni/Au electrode as an example, the first sub-electrode 3a may be provided as a Ni electrode, and the second sub-electrode 3b as an Au electrode.
In this embodiment, as shown in fig. 1, a portion of the gate electrode 6 may also cross over the first sub-electrode 3 a. In practice, the gate electrode 6 may be provided to span between 100nm and 300nm across the source electrode 3.
In another possible implementation, as shown in fig. 1, the drain electrode 4 includes a third sub-electrode 4a and a fourth sub-electrode 4b, and the size of the fourth sub-electrode 4b is smaller than the size of the third sub-electrode 4 a; the third sub-electrode 4a is arranged on the gallium oxide epitaxial layer 2, and the fourth sub-electrode 4b is arranged on the third sub-electrode 4 a; the gate dielectric layer 5 also extends over the exposed surface of the third sub-electrode 4 a. Specifically, taking the drain electrode 4 as the Ti/Au electrode as an example, the third sub-electrode 4a may be provided as a Ti electrode, and the fourth sub-electrode 4b may be provided as an Au electrode.
In the enhanced gallium oxide transistor in the embodiment, by arranging an electrode growth step penetrating through the gallium oxide epitaxial layer 2 at one end of the gallium oxide epitaxial layer 2 to expose a gallium oxide channel and arranging a source electrode 3 on the electrode growth step, when the device is in zero bias, if positive pressure is applied to a drain electrode 4, a Schottky junction of the source electrode 3 is reversely biased, no current flows in the channel, and the device is turned off; if the gate electrode 6 applies a gate voltage higher than the threshold voltage, the gallium oxide potential of the source electrode 3 Schottky junction is lowered, so that the barrier thickness of the Schottky junction is obviously reduced, electrons can be tunneled from the source electrode 3 metal into a gallium oxide channel, and the device is started; and the enhanced device function is realized. And the structure is simple, and the cost is low.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While obvious variations or modifications are contemplated as falling within the scope of the present utility model.
Claims (8)
1. An enhanced gallium oxide transistor, comprising:
a substrate and a gallium oxide epitaxial layer disposed on the substrate; an electrode growth step is arranged at one end of the gallium oxide epitaxial layer, and penetrates through the gallium oxide epitaxial layer;
the source electrode is arranged on the electrode growth step and extends out of the gallium oxide epitaxial layer;
the drain electrode is arranged on the gallium oxide epitaxial layer;
the gate dielectric layer is arranged in a gate position area of the gallium oxide epitaxial layer; the gate dielectric layer is positioned between the source electrode and the drain electrode;
and the gate electrode is arranged on the gate dielectric layer.
2. The enhancement-mode gallium oxide transistor of claim 1, wherein the electrode growth step further extends into the substrate.
3. The enhancement-mode gallium oxide transistor according to claim 1 or 2, wherein the gallium oxide epitaxial layer is a beta-type gallium oxide epitaxial layer.
4. The enhancement-mode gallium oxide transistor according to claim 1 or 2, wherein the source electrode comprises a first sub-electrode and a second sub-electrode, and wherein the second sub-electrode has a size smaller than the first sub-electrode; the first sub-electrode is arranged on the electrode growth step, and the second sub-electrode is arranged on the first sub-electrode; the gate dielectric layer also extends to cover the exposed surface of the first sub-electrode.
5. The enhancement-mode gallium oxide transistor of claim 4, wherein a portion of the gate electrode spans the first sub-electrode.
6. The enhancement-mode gallium oxide transistor according to claim 4, wherein the drain electrode comprises a third sub-electrode and a fourth sub-electrode, and wherein the fourth sub-electrode has a size smaller than the third sub-electrode; the third sub-electrode is arranged on the gallium oxide epitaxial layer, and the fourth sub-electrode is arranged on the third sub-electrode; the gate dielectric layer also extends to cover the exposed surface of the third sub-electrode.
7. The enhancement-mode gallium oxide transistor according to claim 3, wherein the substrate is a gallium oxide substrate.
8. The enhancement-mode gallium oxide transistor according to claim 6, wherein the gallium oxide epitaxial layer is a Cu-doped beta gallium oxide epitaxial layer and wherein the Cu doping concentration is 1 x 10 16 ～1×10 18 cm -3 Between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321399381.6U CN220065703U (en) | 2023-06-02 | 2023-06-02 | Enhancement type gallium oxide transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321399381.6U CN220065703U (en) | 2023-06-02 | 2023-06-02 | Enhancement type gallium oxide transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220065703U true CN220065703U (en) | 2023-11-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202321399381.6U Active CN220065703U (en) | 2023-06-02 | 2023-06-02 | Enhancement type gallium oxide transistor |
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| CN (1) | CN220065703U (en) |
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- 2023-06-02 CN CN202321399381.6U patent/CN220065703U/en active Active
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Effective date of registration: 20240411 Address after: Room 501, 505, 506, Building 4 (self numbered D), No. 18 Shenzhou Road, Huangpu District, Guangzhou City, Guangdong Province, 510663 Patentee after: Guangdong Zhineng Technology Co.,Ltd. Country or region after: China Address before: 710071 No. 2 Taibai South Road, Shaanxi, Xi'an Patentee before: XIDIAN University Country or region before: China Patentee before: Guangzhou Research Institute of Xi'an University of Electronic Science and technology |
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