CN220022605U - Driving circuit and current transformer - Google Patents
Driving circuit and current transformer Download PDFInfo
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- CN220022605U CN220022605U CN202320696070.XU CN202320696070U CN220022605U CN 220022605 U CN220022605 U CN 220022605U CN 202320696070 U CN202320696070 U CN 202320696070U CN 220022605 U CN220022605 U CN 220022605U
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- 230000001629 suppression Effects 0.000 claims abstract description 18
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- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000006731 degradation reaction Methods 0.000 abstract description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 15
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
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Abstract
The present utility model provides a driving circuit, comprising: the driving push-pull circuit comprises a first power end, an output node, a second power end and a driving control end, and is used for controlling the output voltage of the output node to be the voltage of the first power end or the voltage of the second power end according to a control signal of the driving control end; the driving resistor is used for controlling the grid voltage of a target transistor according to the output voltage of the output node, wherein the target transistor is an upper bridge arm transistor or a lower bridge arm transistor; and the negative voltage suppression circuit is used for determining whether the grid voltage of the target transistor is clamped to be the same as the source voltage of the target transistor according to the voltage difference between the first power supply terminal and the output node. The problem of accelerated degradation or damage of the gate insulating layer caused by overlarge negative voltage can be effectively avoided, and the problem of direct connection of the upper bridge arm transistor and the lower bridge arm transistor caused by overlarge positive voltage can be effectively avoided.
Description
Technical Field
The present utility model relates to the field of semiconductor devices, and in particular, to a driving circuit and a current transformer.
Background
In the field of power electronic conversion, an IGBT (Insulated Gate BipolarTransistor ) made of a Si-based material is generally used as a high-speed switching element to form a power conversion circuit, so as to realize power conversion from direct current to alternating current, alternating current to direct current, direct current to direct current, alternating current to alternating current, and the like, and the power conversion circuit is widely applied to new energy fields such as electric automobiles, wind power generation, photovoltaic power generation, and the like. In recent years, as power electronic current converting technology is rapidly developed toward high frequency, high efficiency and high power density, a power electronic current converting device employing a low-loss SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) instead of an IGBT of Si-based material is becoming popular.
Compared with an IGBT power module made of Si-based materials, the SiC MOSFET power module has the advantages of low on resistance and high switching speed, and the application of the SiC MOSFET power module has the characteristics of high frequency resistance, high temperature resistance and strong interference resistance. The high frequency and high switching speed cause new application problems, i.e. crosstalk problems. The problem of crosstalk has become a significant challenge affecting SiC power module applications. If not addressed, it may result in the SiC power module not being applicable.
Therefore, a new driving circuit is required to solve the above-mentioned problems.
Disclosure of Invention
The utility model mainly aims to provide a driving circuit and a converter so as to avoid crosstalk between transistors of an upper bridge arm and a lower bridge arm.
The present utility model provides a driving circuit, comprising: the driving push-pull circuit comprises a first power end, an output node, a second power end and a driving control end, and is used for controlling the output voltage of the output node to be the voltage of the first power end or the voltage of the second power end according to a control signal of the driving control end; the driving resistor is used for controlling the grid voltage of the target transistor according to the output voltage of the output node, wherein the target transistor is an upper bridge arm transistor or a lower bridge arm transistor; and the negative voltage suppression circuit is used for determining whether the grid voltage of the target transistor is clamped to be the same as the source voltage of the target transistor according to the voltage difference between the first power supply terminal and the output node.
In one embodiment, driving the push-pull circuit includes: a first transistor and a second transistor; the grid electrode of the first transistor is connected with the driving control end, the drain electrode of the first transistor is connected with the first power end, the source electrode of the first transistor is connected with the output node, the grid electrode of the second transistor is connected with the driving control end, the source electrode of the second transistor is connected with the output node, and the drain electrode of the second transistor is connected with the second power end.
In one embodiment, the negative voltage suppression circuit includes: the first resistor, the second resistor, the capacitor, the third transistor and the first diode; the first end of the first resistor is connected with the first power end, the second end of the first resistor is connected with the middle node, the first end of the second resistor is connected with the middle node, the second end of the second resistor is connected with the output node, the first end of the capacitor is connected with the middle node, the second end of the capacitor is connected with the output node, the grid electrode of the third transistor is connected with the middle node, the source electrode of the third transistor is connected with the positive electrode of the first diode, the drain electrode of the third transistor is connected with the source electrode of the target transistor, and the negative electrode of the first diode is connected with the grid electrode of the target transistor.
In an embodiment, further comprising: and the positive pressure suppression circuit is used for controlling the grid voltage of the target transistor not to exceed a preset value according to the control signal of the driving control end.
In one embodiment, the positive pressure suppression circuit includes: a fourth transistor, a fifth transistor, and an operational amplifier; the grid electrode of the fourth transistor is connected with the driving control end, the source electrode of the fourth transistor is connected with the grid electrode of the target transistor, the drain electrode of the fourth transistor is connected with the first input end of the operational amplifier, the second input end of the operational amplifier is connected with the reference potential, the output end of the operational amplifier is connected with the grid electrode of the fifth transistor, the drain electrode of the fifth transistor is connected with the grid electrode of the target transistor, and the source electrode of the fifth transistor is connected with the second power end.
In an embodiment, further comprising: a third resistor and a second diode; the first end of the third resistor is connected with the grid electrode of the target transistor, the second end of the third resistor is connected with the positive electrode of the second diode, and the negative electrode of the second diode is connected with the output node.
In an embodiment, further comprising: the system comprises a first power supply, a second power supply and a control module; the positive electrode of the first power supply is connected with the first power supply end, the negative electrode of the first power supply is connected with the positive electrode of the second power supply, the negative electrode of the second power supply is connected with the second power supply end, and the output end of the control module is connected with the driving control end to output a control signal.
In one embodiment, the target transistor comprises a SiC MOS transistor.
In one embodiment, the voltage at the first power supply terminal is used to turn on the target transistor, and the voltage at the second power supply terminal is used to turn off the target transistor.
The utility model provides a current transformer, comprising: the inverter circuit comprises a plurality of upper bridge arm transistors and a plurality of lower bridge arm transistors which are connected in a one-to-one correspondence manner; a plurality of driving circuits connected to the plurality of upper arm transistors in one-to-one correspondence; and a plurality of driving circuits connected to the plurality of lower arm transistors in one-to-one correspondence.
The driving circuit of the embodiment can flexibly control whether to clamp the grid voltage of the target transistor by using the negative pressure suppressing circuit according to the on-off state of the target transistor; the negative voltage suppression circuit is utilized to clamp the gate voltage of the target transistor, so that the gate insulating layer of the target transistor can be prevented from bearing excessive negative voltage, the gate insulating layer of the transistor is prevented from bearing larger voltage stress, and the service life of the transistor is prolonged. The driving circuit can effectively avoid the problem of accelerated degradation or damage of the gate insulating layer caused by overlarge negative voltage, and can effectively avoid the problem of direct connection of the upper bridge arm transistor and the lower bridge arm transistor caused by overlarge positive voltage.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a undue limitation on the utility model, wherein:
fig. 1 is a topology diagram of an inverter circuit in the related art;
fig. 2 is a schematic diagram of waveforms of Vds and Vgs of the upper arm transistor of the inverter circuit shown in fig. 1;
fig. 3 is a topology of an inverter circuit according to an exemplary embodiment of the present utility model;
fig. 4 is a topology diagram of a driving circuit of the half bridge 210 of the inverter circuit shown in fig. 3;
fig. 5 is a schematic waveform diagram of Vds and Vgs of the upper and lower leg transistors of the half-bridge 210 of the inverter circuit shown in fig. 3;
fig. 6 is a schematic diagram of waveforms of Vds and Vgs of the upper arm transistor driven by the driving circuit shown in fig. 4.
Detailed Description
It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be combined with each other. The utility model will be described in detail below with reference to the drawings in connection with embodiments.
In a power converter, siC power modules perform high-speed switching, completing switching operations tens of thousands or more times per second. The high speed switch causes the SiC power module to be high dv/dt.
Referring to fig. 1, a topology of an inverter circuit in the related art is shown. The inverter circuit includes 3 half-bridge circuits. The half-bridge circuit 110 includes an upper bridge arm 111 and a lower bridge arm 112, the upper bridge arm 111 is connected to a positive pole vdc+ of the dc power supply, and the lower bridge arm 112 is connected to a negative pole VDC-of the dc power supply. In the half-bridge circuit, the SiC MOSFET power modules of the upper bridge arm and the lower bridge arm cannot be simultaneously turned on and always work in a complementary high-speed switch switching state.
Referring to fig. 2, the high speed switching creates a large dv/dt between the drain D and source S of the SiC MOSFET power module, which will result in a voltage Vgs between the SiC MOSFET gate G and source S having a large spike (excessive negative voltage and excessive positive voltage in fig. 2). Because the forward threshold voltage between the grid sources of the SiC MOSFET is lower, the SiC MOSFET power module is easy to open by mistake due to the excessive forward voltage, so that the upper bridge arm and the lower bridge arm are directly connected, and the direct current can damage the SiC MOSFET power module. In addition, the excessive negative voltage makes the grid insulation layer of the SiC MOSFET power module bear larger voltage stress, so that the degradation and even the damage of the grid insulation layer are accelerated. Therefore, in the half-bridge circuit, in order to fully utilize the advantages of the SiC MOSFET, the problem of crosstalk between the upper and lower arms needs to be solved.
The present embodiment provides a driving circuit that can be applied to the inverter circuit shown in fig. 3, and that can be used to drive each transistor of the upper and lower arms of the half-bridge circuit 210 in the inverter circuit. The driving circuit of the present embodiment will be described below taking the driving circuit of the upper arm transistor as an example.
Referring to fig. 4, a driving circuit 310 (a total driving circuit 300 includes an upper arm transistor driving circuit 310 and a lower arm transistor driving circuit 320) of the present embodiment may include: the driving push-pull circuit 311 (321) (similar reference numerals in brackets denote corresponding devices of the driving circuit of the lower bridge arm transistor), the driving push-pull circuit 311 (321) includes a first power supply terminal AH (AL), an output node CH (CL), a second power supply terminal BH (BL), and a driving control terminal DH (DL), for controlling an output voltage of the output node CH (CL) to be a voltage of the first power supply terminal AH (AL) or the second power supply terminal BH (BL) according to a control signal of the driving control terminal DH (DL); a driving resistor RgH (RgL) for controlling a gate voltage of a target transistor Q6H (Q6L) according to an output voltage of the output node CH (CL), wherein the target transistor is an upper bridge arm transistor Q6H or a lower bridge arm transistor Q6L; the negative voltage suppression circuit 312 (322) is configured to determine whether to clamp the gate voltage of the target transistor Q6H (Q6L) to be the same as the source voltage of the target transistor according to the voltage difference between the first power supply terminal AH (AL) and the output node CH (CL). The target transistor may include a SiC MOS transistor.
In this embodiment, when the voltage difference between the first power supply terminal and the output node is 0, the voltage of the output node is the voltage of the first power supply terminal, and the negative voltage suppression circuit is bypassed, without clamping the gate voltage of the target transistor to be the same as the source voltage; when the voltage difference between the first power supply terminal and the output node is within the preset value range, the voltage of the output node is the voltage of the second power supply terminal, and the gate voltage of the target transistor needs to be clamped to be the same as the source voltage of the target transistor. The driving circuit of the embodiment can flexibly control whether to clamp the grid voltage of the target transistor by using the negative pressure suppressing circuit according to the on-off state of the target transistor; the negative voltage suppression circuit is utilized to clamp the gate voltage of the target transistor, so that the gate insulating layer of the target transistor can be prevented from bearing excessive negative voltage, the gate insulating layer of the transistor is prevented from bearing larger voltage stress, and the service life of the transistor is prolonged.
In an embodiment, referring to fig. 4, the driving push-pull circuit 311 (321) may include: a first transistor Q1H (Q1L) and a second transistor Q2H (Q2L); the gate of the first transistor Q1H (Q1L) is connected to the driving control terminal DH (DL), the drain of the first transistor Q1H (Q1L) is connected to the first power supply terminal AH (AL), the source of the first transistor Q1H (Q1L) is connected to the output node CH (CL), the gate of the second transistor Q2H (Q2L) is connected to the driving control terminal DH (DL), the source of the second transistor Q2H (Q2L) is connected to the output node CH (CL), and the drain of the second transistor Q2H (Q2L) is connected to the second power supply terminal BH (BL).
In this embodiment, the first transistor and the second transistor are controlled to be turned on and off by the control signal of the driving control terminal, wherein the first transistor and the second transistor cannot be turned on at the same time. When the first transistor is turned on, the voltage difference between the first power supply end and the output node is 0, and the negative voltage suppression circuit is bypassed; when the second transistor is turned on, the voltage difference between the first power supply terminal and the output node is, for example, the voltage difference between the first power supply terminal and the second power supply terminal, and then the negative voltage suppression circuit can clamp the gate voltage of the target transistor to be the same as the source voltage of the target transistor, so that the gate insulating layer of the target transistor is prevented from bearing excessive negative voltage.
In fig. 4, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.
In one embodiment, referring to fig. 4, the negative pressure suppression circuit 312 (322) may include: a first resistor R1H (R1L), a second resistor R2H (R2L), a capacitor C1H (C1L), a third transistor Q3H (Q3L), and a first diode D1H (D1L); the first resistor R1H (R1L) has a first end connected to the first power supply end AH (AL), the second end of the first resistor R1H (R1L) is connected to the intermediate node EH (EL), the first end of the second resistor R2H (R2L) is connected to the intermediate node EH (EL), the second end of the second resistor R2H (R2L) is connected to the output node CH (CL), the first end of the capacitor C1H (C1L) is connected to the intermediate node EH (EL), the second end of the capacitor C1H (C1L) is connected to the output node CH (CL), the gate of the third transistor Q3H (Q3L) is connected to the intermediate node EH (EL), the source of the third transistor Q3H (Q3L) is connected to the positive electrode of the first diode D1H (D1L), the drain of the third transistor Q3H (Q3L) is connected to the source of the target transistor Q6H (Q6L), and the negative electrode of the first diode D1H (D1L) is connected to the gate of the target transistor Q6H (Q6L).
In fig. 4, the third transistor is a PMOS transistor.
In the negative pressure suppressing circuit of the present embodiment, referring to fig. 4, a circuit including the first resistor R1H, the second resistor R2H, and the capacitor C1H is a voltage dividing circuit, and the gate driving voltage is supplied to the third transistor Q3H. When the first transistor Q1H is turned on, vgs of the target transistor Q6H is 15V (first power supply terminal voltage), the negative voltage suppression circuit is bypassed, the charge on the capacitor C1H is discharged through the second resistor R2H until it is reduced to 0V, and the third transistor Q3H is turned off; when the first transistor Q1H is turned off, the second transistor Q2H is turned on, the Vgs of the target transistor Q6H is at-4V (the voltage of the second power supply terminal), the upper end of the first resistor R1H is connected to +15v, the lower end of the second resistor R2H is connected to-4V through the turned-on second transistor Q2H, the capacitor C1H is negatively charged until approaching or reaching-4V, the third transistor Q3H is turned on, the gate voltage of the target transistor Q6H is raised to the source voltage thereof, and the Vgs of the target transistor is approaching 0V. When Vgs is 0V, a negative spike voltage caused by crosstalk is superimposed on Vgs, and an excessive negative voltage does not occur, thereby protecting the target transistor.
By the negative voltage suppression circuit, the grid voltage of the target transistor is clamped to be the same as the source voltage of the target transistor, so that the grid insulating layer of the target transistor can be prevented from bearing excessive negative voltage, and the service life of the target transistor can be prolonged.
In the present embodiment, the on period of the third transistor Q3H may be controlled by the capacitor C1H by configuring the ratio of the resistances of the first resistor R1H and the second resistor R2H.
In an implementation manner, the driving circuit 310 (320) of this embodiment may further include: the positive voltage suppressing circuit 313 (323) is configured to control the gate voltage of the target transistor Q6H (Q6L) not to exceed a preset value according to the control signal of the drive control terminal DH (DL).
By controlling the gate voltage of the target transistor not to exceed the preset value, erroneous turn-on due to the excessive forward voltage that the gate of the target transistor receives when the target transistor is turned off can be avoided.
In one embodiment, referring to fig. 4, positive pressure suppression circuit 313 (323) may include: a fourth transistor Q4H (Q4L), a fifth transistor Q5H (Q5L), and an operational amplifier U1H (U1L); the gate of the fourth transistor Q4H (Q4L) is connected to the driving control terminal DH (DL), the source of the fourth transistor Q4H (Q4L) is connected to the gate of the target transistor Q6H (Q6L), the drain of the fourth transistor Q4H (Q4L) is connected to the first input terminal of the operational amplifier U1H (U1L), the second input terminal of the operational amplifier U1H (U1L) is connected to the reference potential REFH (REFL), the output terminal of the operational amplifier U1H (U1L) is connected to the gate of the fifth transistor Q5H (Q5L), the drain of the fifth transistor Q5H (Q5L) is connected to the gate of the target transistor Q6H (Q6L), and the source of the fifth transistor Q5H (Q5L) is connected to the second power supply terminal BH (BL).
In fig. 4, the fourth transistor is a PMOS transistor, and the fifth transistor is an NMOS transistor.
When the second transistor is turned on, the Vgs initial value of the target transistor Q6H is-4V (voltage of the second power supply terminal), the fourth transistor is turned on simultaneously, whether the gate voltage of the target transistor exceeds the reference potential or not can be monitored through the operational amplifier, and when the gate voltage of the target transistor exceeds the reference potential, that is, when Vgs > REFH, a voltage signal is output to enable the fifth transistor to be turned on, so that the gate voltage of the target transistor is directly pulled down to the voltage of the second power supply terminal, and the turning on of the target transistor is avoided.
Referring to fig. 5, the upper arm transistor is described as an example according to the operation timings of the upper arm transistor and the lower arm transistor. Vgs (upper leg) of the target transistor Q6H contains three levels, +15V, 0V, and-4V. When Vgs (upper leg) is +15v, Q6H will be on; Q6H will be turned off when Vgs (upper leg) is 0V and-4V. Similarly, vgs (lower leg) can control on and off of Q6L. Vgs (upper leg) and Vgs (lower leg) cannot be +15v at the same time.
With reference to fig. 4, the crosstalk suppression by the driving circuit of the present embodiment will be described with reference to fig. 6 by taking the above arm transistor as an example.
When Q2H is on, vgs (upper bridge arm) is-4V, and the upper bridge arm transistor Q6H is off. When t is reached 0 At this time, the third transistor Q3H is turned on, pulling Vgs (upper arm) to 0V. In this state, when Vds (upper arm) is changed from high voltage to low voltage, high dv/dt causes Vgs (upper arm) to have a downward spike voltage (excessive negative voltage) at which Vgs (upper arm) is 0V, so the downward spike voltage does not damage the gate insulating layer of the upper arm transistor.
When t is reached 1 At this time, the second transistor Q2H is turned off, the first transistor Q1H is turned on, vgs (upper arm) is +15v, and the upper arm transistor Q6H is turned on. When t is reached 2 At the moment, the first transistor Q1H is turned off, the second transistor Q2H is turned on, and Vgs (upper bridge arm) is-4V. When Vds (upper arm) is changed from low voltage to high voltage, high dv/dt causes Vgs (upper arm) to have an upward spike voltage (excessive forward voltage), if the upward spike voltage is higher than REFH, the fifth transistor Q5H is turned on, and Vgs (upper arm) is pulled down to-4V, so that the upward spike voltage of Vgs (upper arm) does not cause upper arm transistor Q6H to be turned on by mistake.
When t is reached 3 At time, the third transistor Q3H is turned on, pulls Vgs (upper arm) to 0V, and then returns to the state at time t0, thereby cyclically operating.
The driving circuit of the embodiment drives the transistors of the lower bridge arm in the same principle as the transistors of the upper bridge arm, so that the crosstalk problem between the transistors of the upper bridge arm and the transistors of the lower bridge arm is solved.
In an implementation manner, the driving circuit of this embodiment may further include: a third resistor R3H (R3L) and a second diode D2H (D2L); the first end of the third resistor R3H (R3L) is connected to the gate of the target transistor Q6H (Q6L), the second end of the third resistor R3H (R3L) is connected to the positive electrode of the second diode D2H (D2L), and the negative electrode of the second diode D2H (D2L) is connected to the output node CH (CL).
In an implementation manner, the driving circuit of this embodiment may further include: a first power supply V1H (V1L), a second power supply V2H (V2L), and a control module; the positive pole of the first power supply V1H (V1L) is connected to the first power supply end AH (AL), the negative pole of the first power supply V1H (V1L) is connected to the positive pole of the second power supply V2H (V2L), the negative pole of the second power supply V2H (V2L) is connected to the second power supply end BH (BL), and the output end of the control module is connected to the driving control end DH (DL) to output a control signal.
In one embodiment, the voltage at the first power supply terminal is used to turn on the target transistor, and the voltage at the second power supply terminal is used to turn off the target transistor.
The driving circuit of the upper arm transistor is described above, but the same circuit is also applicable to the lower arm transistor, and will not be described here again. The above-mentioned transistors are PMOS or NMOS, or other transistors, and those skilled in the art may select them as needed, which is not particularly limited by the present utility model.
The utility model is not limited to the applicable device types and scenes, and the driving circuit of the embodiment can be applied to all silicon carbide power semiconductor modules comprising gate structures, and can be applied to the following scenes: chips, discrete devices, modules, etc.
The present embodiment provides a current transformer, which may include: the inverter circuit comprises a plurality of upper bridge arm transistors and a plurality of lower bridge arm transistors which are connected in a one-to-one correspondence manner; a plurality of driving circuits connected to the plurality of upper arm transistors in one-to-one correspondence; and a plurality of driving circuits connected to the plurality of lower arm transistors in one-to-one correspondence.
By driving the transistors in the inverter circuit by the driving circuit, the crosstalk problem between the upper bridge arm transistor and the lower bridge arm transistor can be effectively restrained.
It is noted that the terms used herein are used merely to describe particular embodiments and are not intended to limit exemplary embodiments in accordance with the present utility model, when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It should be noted that the terms "first," "second," and the like in the description and the claims and drawings of the present utility model are used for distinguishing between similar objects and not for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
It should be understood that the exemplary embodiments in this specification may be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art, and should not be construed as limiting the utility model.
While the spirit and principles of the present utility model have been described with reference to several particular embodiments, it is to be understood that the utility model is not limited to the disclosed embodiments nor does it imply that features of the various aspects are not useful in combination, nor are they useful in any combination, such as for convenience of description. The utility model is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (10)
1. A driving circuit, characterized by comprising:
the driving push-pull circuit comprises a first power end, an output node, a second power end and a driving control end, and is used for controlling the output voltage of the output node to be the voltage of the first power end or the voltage of the second power end according to a control signal of the driving control end;
the driving resistor is used for controlling the grid voltage of a target transistor according to the output voltage of the output node, wherein the target transistor is an upper bridge arm transistor or a lower bridge arm transistor;
and the negative voltage suppression circuit is used for determining whether the grid voltage of the target transistor is clamped to be the same as the source voltage of the target transistor according to the voltage difference between the first power supply terminal and the output node.
2. The drive circuit according to claim 1, wherein the drive push-pull circuit includes: a first transistor and a second transistor;
the gate of the first transistor is connected with the driving control end, the drain of the first transistor is connected with the first power end, the source of the first transistor is connected with the output node, the gate of the second transistor is connected with the driving control end, the source of the second transistor is connected with the output node, and the drain of the second transistor is connected with the second power end.
3. The drive circuit according to claim 1, wherein the negative pressure suppressing circuit includes: the first resistor, the second resistor, the capacitor, the third transistor and the first diode;
the first end of the first resistor is connected with the first power supply end, the second end of the first resistor is connected with the middle node, the first end of the second resistor is connected with the middle node, the second end of the second resistor is connected with the output node, the first end of the capacitor is connected with the middle node, the second end of the capacitor is connected with the output node, the grid electrode of the third transistor is connected with the middle node, the source electrode of the third transistor is connected with the positive electrode of the first diode, the drain electrode of the third transistor is connected with the source electrode of the target transistor, and the negative electrode of the first diode is connected with the grid electrode of the target transistor.
4. The drive circuit of claim 1, further comprising:
and the positive pressure suppression circuit is used for controlling the grid voltage of the target transistor not to exceed a preset value according to the control signal of the driving control end.
5. The drive circuit according to claim 4, wherein the positive-pressure suppressing circuit includes: a fourth transistor, a fifth transistor, and an operational amplifier;
the grid electrode of the fourth transistor is connected with the driving control end, the source electrode of the fourth transistor is connected with the grid electrode of the target transistor, the drain electrode of the fourth transistor is connected with the first input end of the operational amplifier, the second input end of the operational amplifier is connected with the reference potential, the output end of the operational amplifier is connected with the grid electrode of the fifth transistor, the drain electrode of the fifth transistor is connected with the grid electrode of the target transistor, and the source electrode of the fifth transistor is connected with the second power end.
6. The drive circuit of claim 1, further comprising: a third resistor and a second diode;
the first end of the third resistor is connected with the grid electrode of the target transistor, the second end of the third resistor is connected with the positive electrode of the second diode, and the negative electrode of the second diode is connected with the output node.
7. The drive circuit of claim 1, further comprising: the system comprises a first power supply, a second power supply and a control module;
the positive electrode of the first power supply is connected with the first power supply end, the negative electrode of the first power supply is connected with the positive electrode of the second power supply, the negative electrode of the second power supply is connected with the second power supply end, and the output end of the control module is connected with the driving control end to output a control signal.
8. The drive circuit of claim 1, wherein the target transistor comprises a SiC MOS transistor.
9. The drive circuit of claim 1, wherein the voltage of the first power supply terminal is used to turn on the target transistor and the voltage of the second power supply terminal is used to turn off the target transistor.
10. A current transformer, comprising:
the inverter circuit comprises a plurality of upper bridge arm transistors and a plurality of lower bridge arm transistors which are connected in a one-to-one correspondence manner;
a plurality of driving circuits according to any one of claims 1 to 9 connected in one-to-one correspondence with a plurality of upper arm transistors; and
a plurality of the driving circuits according to any one of claims 1 to 9 connected to the plurality of lower arm transistors in one-to-one correspondence.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320696070.XU CN220022605U (en) | 2023-03-31 | 2023-03-31 | Driving circuit and current transformer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320696070.XU CN220022605U (en) | 2023-03-31 | 2023-03-31 | Driving circuit and current transformer |
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| CN220022605U true CN220022605U (en) | 2023-11-14 |
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| CN202320696070.XU Active CN220022605U (en) | 2023-03-31 | 2023-03-31 | Driving circuit and current transformer |
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| Country | Link |
|---|---|
| CN (1) | CN220022605U (en) |
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2023
- 2023-03-31 CN CN202320696070.XU patent/CN220022605U/en active Active
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