CN219937044U - Multi-chip parallel half-bridge IGBT module - Google Patents
Multi-chip parallel half-bridge IGBT module Download PDFInfo
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- CN219937044U CN219937044U CN202320685253.1U CN202320685253U CN219937044U CN 219937044 U CN219937044 U CN 219937044U CN 202320685253 U CN202320685253 U CN 202320685253U CN 219937044 U CN219937044 U CN 219937044U
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- 229910052802 copper Inorganic materials 0.000 claims abstract description 73
- 239000010949 copper Substances 0.000 claims abstract description 73
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 70
- 239000000919 ceramic Substances 0.000 claims description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 26
- 238000000034 method Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The utility model discloses a multi-chip parallel half-bridge IGBT module, which is additionally provided with an emitter signal copper layer, and directly leads emitter voltage signals out of a corresponding bonding wire cluster, so that common emitter parasitic inductance of a signal loop and a power loop and mutual inductance between the power loop and a signal control loop are reduced, partial pressure of the common emitter parasitic inductance to the signal control loop is reduced, influence of current change of the power loop on voltage change of the signal control loop is reduced, the descending speed of collector-emitter voltage of a chip in an opening process is accelerated, loss of the chip in the opening process is reduced, and the working frequency of the module is improved.
Description
Technical Field
The utility model relates to a multi-chip parallel half-bridge IGBT module, and belongs to the technical field of power semiconductor devices.
Background
The layout of a traditional multi-chip parallel half-bridge IGBT (insulated gate bipolar transistor) module is shown in fig. 1 and 2, and the traditional multi-chip parallel half-bridge IGBT (insulated gate bipolar transistor) module comprises an upper bridge arm and a lower bridge arm, wherein each bridge arm comprises four groups of IGBT chip sets, and each group of IGBT chip sets comprises an IGBT chip and a flywheel diode (FRD) which is antiparallel with the IGBT chip; wherein, the IGBT chips of the upper bridge arm are 4 a-4 d, the corresponding freewheel diodes are 5 a-5 d, the IGBT chips of the lower bridge arm are 6 a-6 d, and the corresponding freewheel diodes are 7 a-7 d; the IGBT chip and the freewheel diode are welded on the copper-clad ceramic lining board, wherein 2 and 3 in the figure are respectively an upper bridge arm copper-clad ceramic lining board and a lower bridge arm copper-clad ceramic lining board, the front sides of the IGBT chip and the freewheel diode are connected through a bonding wire cluster, 11 a-11 d in the figure are bonding wire clusters of the upper bridge arm, 12 a-12 d in the figure are bonding wire clusters of the lower bridge arm, 13 and 16 in the figure are respectively an upper bridge arm grid signal terminal and a lower bridge arm grid signal terminal, and 14 and 17 are respectively an upper bridge arm emitter signal terminal and a lower bridge arm emitter signal terminal; the on-off of IGBT chips of the upper bridge arm and the lower bridge arm is controlled by a driving signal, wherein the IGBT chips of the upper bridge arm are controlled by an upper bridge arm grid signal terminal 13 and an emitter signal terminal 14, grid control signals are connected with the grid of the chip through a path of the grid signal terminal 13-copper foil-bonding wire-copper foil-grid bonding wire, the emitter control signals are connected with the emitter of the chip through a loop of the emitter signal terminal 14-copper foil-bonding wire, and the path is long; the turn-on/off of the IGBT chip of the lower arm is controlled by the lower arm gate signal terminal 17 and the emitter signal terminal 16. The copper-clad ceramic lining plate is welded on the metal substrate 1, and the upper and lower bridge arms are connected with an external circuit through an output terminal 10, a positive electrode terminal 20 and a negative electrode terminal 30 and are connected with a drive control circuit through a grid signal terminal and an emitter signal terminal.
Because the chips of the upper bridge arm and the lower bridge arm are in central symmetry layout, the on-off curves of the upper bridge arm and the lower bridge arm are basically similar, and the parasitic inductance parameters of the upper bridge arm chip set are calculated and analyzed, and the on-off process is further calculated and analyzed to obtain the on curves of the three chips, as shown in fig. 3, the problems of slow voltage drop of the collector-emitter electrode and larger on-loss exist in the on-process, and the further improvement of the on-speed of the IGBT module is not facilitated.
Disclosure of Invention
The utility model provides a multi-chip parallel half-bridge IGBT module, which solves the problems disclosed in the background technology.
In order to solve the technical problems, the utility model adopts the following technical scheme:
an emitter signal copper layer is additionally arranged on a copper-clad ceramic lining plate, emitter voltage signals of all IGBT chips are directly led out from corresponding bonding wire clusters, and the led-out emitter voltage signals are transmitted to an emitter signal terminal through the emitter signal copper layer.
An upper bridge arm emitter electrode signal copper layer and a lower bridge arm emitter electrode signal copper layer are additionally arranged on the copper-clad ceramic lining plate;
the emitter voltage signals of all IGBT chips of the upper bridge arm are directly led out from the corresponding bonding wire clusters, and the emitter voltage signals led out from the upper bridge arm are transmitted to the emitter signal terminals of the upper bridge arm through the emitter signal copper layer of the upper bridge arm;
emitter voltage signals of all IGBT chips of the lower bridge arm are directly led out from the corresponding bonding wire clusters, and the emitter voltage signals led out from the lower bridge arm are transmitted to emitter signal terminals of the lower bridge arm through emitter signal copper layers of the lower bridge arm.
The upper bridge arm emitter electrode signal copper layer is positioned outside the upper bridge arm grid electrode signal copper layer.
The upper bridge arm emitter signal copper layer comprises a first emitter signal copper layer and a second emitter signal copper layer which are connected through bonding wires, and two emitter signals of the upper bridge arm are respectively transmitted to the first emitter signal copper layer and the second emitter signal copper layer.
The lower bridge arm emitter electrode signal copper layer is positioned outside the lower bridge arm grid electrode signal copper layer.
The lower bridge arm emitter signal copper layer comprises a third emitter signal copper layer and a fourth emitter signal copper layer which are connected through bonding wires, and two emitter signals of the lower bridge arm are respectively transmitted to the third emitter signal copper layer and the fourth emitter signal copper layer.
The utility model has the beneficial effects that: according to the utility model, the emitter signal copper layer is additionally arranged, the emitter voltage signal is directly led out from the corresponding bonding wire cluster, the common emitter parasitic inductance of the signal loop and the power loop and the mutual inductance between the power loop and the signal control loop are reduced, the partial pressure of the common emitter parasitic inductance to the signal control loop is reduced, the influence of the current change of the power loop on the voltage change of the signal control loop is reduced, the falling speed of the collector-emitter voltage of the chip in the opening process is accelerated, the loss of the chip in the opening process is reduced, and the working frequency of the module is improved.
Drawings
Fig. 1 is a perspective view of a conventional multi-chip parallel half-bridge IGBT module;
fig. 2 is a layout diagram of a conventional multi-chip parallel half-bridge IGBT module;
fig. 3 is a current graph of a switching-on process of four IGBT chips of an upper bridge arm of a conventional multi-chip parallel half-bridge IGBT module;
fig. 4 is a schematic diagram of parasitic inductance of a multi-chip parallel half-bridge IGBT module;
FIG. 5 is a layout of the present utility model;
fig. 6 is a current graph of the switching-on process of four IGBT chips of the upper arm of the present utility model.
Detailed Description
The utility model is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present utility model, and are not intended to limit the scope of the present utility model.
As shown in fig. 4, by analyzing the effect of the parasitic inductance of the half-bridge IGBT module on the turn-on current sharing, the emitter parasitic inductance of the shared portion of the signal control loop and the power loop is found (Luc is the parasitic inductance of the collector-power terminal P of the IGBT chip of the upper leg in the drawing, luk is the parasitic inductance of the gate-gate terminal UG of the IGBT chip of the upper leg, lug is the parasitic inductance of the gate-signal line of the IGBT chip of the upper leg, lsue is the parasitic inductance of the emitter-signal line of the upper leg, lpue is the shared parasitic inductance of the emitter-power/signal loop of the upper leg, lue is the parasitic inductance of the emitter-power loop of the upper leg, ldc is the parasitic inductance of the collector-power terminal AC of the IGBT chip of the lower leg, ldk is the parasitic inductance of the collector-power terminal AC of the IGBT chip of the lower leg, ldg is the parasitic inductance of the gate-gate terminal P of the IGBT chip of the lower leg, lsde is the parasitic inductance of the emitter-signal line of the lower leg, lsde is the parasitic inductance of the emitter-signal loop of the lower leg, and lrde is the parasitic inductance of the emitter-power loop of the upper leg), and the parasitic inductance of the emitter-power/signal loop of the upper leg, and lu is the parasitic inductance of the emitter-power loop of the upper leg, and DG is the parasitic inductance of the emitter-power loop of the upper leg, and the current of the upper leg, and the emitter-power loop is increased, and the actual speed of the emitter module is increased.
In order to achieve fast turn-on, as an embodiment of the present utility model, as shown in fig. 5, an emitter signal copper layer is added on a copper-clad ceramic liner plate, emitter voltage signals of each IGBT chip are directly led out from a corresponding bonding wire cluster, and the led-out emitter voltage signals are transmitted to an emitter signal terminal through the emitter signal copper layer.
By additionally arranging the emitter signal copper layer, emitter voltage signals are directly led out from the corresponding bonding wire clusters, common emitter parasitic inductance of a signal loop and a power loop and mutual inductance between the power loop and a signal control loop are reduced, partial pressure of the common emitter parasitic inductance to the signal control loop is reduced, influence of current change of the power loop on voltage change of the signal control loop is reduced, so that the descending speed of collector-emitter voltage of a chip in the opening process is accelerated, loss of the chip in the opening process is reduced, and the working frequency of a module is improved.
In the drawings, an upper bridge arm and a lower bridge arm are output terminals 10, a positive terminal 20 and a negative terminal 30 respectively through a first output terminal and a second output terminal respectively, the upper bridge arm and the lower bridge arm are connected with an external circuit through the first output terminal, the second output terminal and the negative terminal 30 respectively through the first output terminal, the second output terminal and the second output terminal respectively, 1 is a metal substrate, 2 is a copper-clad ceramic lining plate of the upper bridge arm, 3 is a copper-clad ceramic lining plate of the lower bridge arm, 2 and 3 are both welded on 1, 2 is welded on 2, and 3 is welded on 3.
4 a-4 d are four IGBT chips of an upper bridge arm, which can be sequentially defined as an upper bridge arm first IGBT chip, an upper bridge arm second IGBT chip, an upper bridge arm third IGBT chip and an upper bridge arm fourth IGBT chip, 5 a-5 d are four freewheeling diodes which are respectively connected with 4 a-4 d in anti-parallel, which can be sequentially defined as an upper bridge arm first freewheeling diode, an upper bridge arm second freewheeling diode, an upper bridge arm third freewheeling diode and an upper bridge arm fourth freewheeling diode, 11 a-11 d are four upper bridge arm bonding wire clusters, which can be sequentially defined as an upper bridge arm first bonding wire cluster, an upper bridge arm second bonding wire cluster, an upper bridge arm third bonding wire cluster and an upper bridge arm fourth bonding wire cluster, 4a front side and 5a front side, 4b front and 5b front side, 4c front and 5c front side are respectively connected through 11 a-11 d, 8 a-8 d are four upper bridge arm grid bonding wires, which can be sequentially defined as an upper first grid bonding wire, an upper bridge arm second grid bonding wire, an upper bridge arm third grid electrode bonding wire and an upper bridge arm fourth grid electrode bonding wire, and a copper foil signal wire are correspondingly connected with an upper bridge arm signal wire of an emitter electrode terminal of an upper bridge arm, and a longer-copper foil signal wire of the upper bridge arm is led out of the upper bridge arm signal wire is connected from an emitter electrode terminal of an upper bridge arm signal wire of an emitter electrode of the upper bridge arm 2-14.
6 a-6 d are four IGBT chips of the lower bridge arm, which can be sequentially defined as a first IGBT chip of the lower bridge arm, a second IGBT chip of the lower bridge arm, a third IGBT chip of the lower bridge arm and a fourth IGBT chip of the lower bridge arm, 7 a-7 d are four freewheel diodes which are respectively connected with 6 a-6 d in anti-parallel, which can be sequentially defined as a first freewheel diode of the lower bridge arm, a second freewheel diode of the lower bridge arm, a third freewheel diode of the lower bridge arm and a fourth freewheel diode of the lower bridge arm, 12 a-12 d are connected into four lower bridge arm bonding wire clusters, which can be sequentially defined as a first bonding wire cluster of the lower bridge arm, a second bonding wire cluster of the lower bridge arm, a third bonding wire cluster of the lower bridge arm and a fourth bonding wire cluster of the lower bridge arm, the front faces of 6a and 7a, the front faces of 6b and 7b, the front faces of 6c and 7c and the front faces of 6d and 7d are respectively connected through 12 a-12 d, 9 a-9 d are four lower bridge arm grid bonding wires, which can be sequentially defined as a lower bridge arm first grid bonding wire, a lower bridge arm second grid bonding wire, a lower bridge arm third grid bonding wire and a lower bridge arm fourth grid bonding wire, grid signals corresponding to IGBT chips are respectively led out of 12 a-12 d to the lower bridge arm grid signal copper layer 3a, the lower bridge arm grid signal copper layer 3a is connected with the lower bridge arm grid signal terminal 16 through bonding wires, and a loop of an emitter signal terminal 16-copper foil-bonding wire of the lower bridge arm emitter control signal is connected with a chip emitter, so that the path is long.
Fig. 5 is a diagram of an improved distribution diagram based on fig. 2, specifically, an upper bridge arm emitter signal copper layer 15 and a lower bridge arm emitter signal copper layer 18 are added on a copper-clad ceramic lining plate, emitter voltage signals of all IGBT chips of the upper bridge arm are directly led out from corresponding bonding wire clusters, emitter voltage signals led out from the upper bridge arm are transmitted to an upper bridge arm emitter signal terminal 14 through the upper bridge arm emitter signal copper layer 15, emitter voltage signals of all IGBT chips of the lower bridge arm are directly led out from corresponding bonding wire clusters, and emitter voltage signals led out from the lower bridge arm are transmitted to a lower bridge arm emitter signal terminal 17 through the lower bridge arm emitter signal copper layer 18.
In order to ensure that the chip arrangement mode is unchanged, an upper bridge arm emitter electrode signal copper layer 15 can be further arranged on the outer side of the upper bridge arm gate electrode signal copper layer 2a, and a lower bridge arm emitter electrode signal copper layer 18 can be arranged on the outer side of the lower bridge arm gate electrode signal copper layer 3 a.
Specific arrangement as shown in fig. 5, the emitter signal copper layer 15 of the upper bridge arm is arranged in two segments, including a first emitter signal copper layer and a second emitter signal copper layer, the first emitter signal copper layer and the second emitter signal copper layer are connected by bonding wires, two emitter signals of the upper bridge arm are respectively transferred to the first emitter signal copper layer and the second emitter signal copper layer, the emitter signal copper layer 18 of the lower bridge arm is also arranged in two segments, including a third emitter signal copper layer and a fourth emitter signal copper layer, the third emitter signal copper layer and the fourth emitter signal copper layer are connected by bonding wires, and two emitter signals of the lower bridge arm are respectively transferred to the third emitter signal copper layer and the fourth emitter signal copper layer.
The distribution inductance of the improved module is calculated and substituted into the opening simulation circuit to be calculated, the opening curves of the three improved chips are shown in fig. 6, and the result shows that the opening current rising time of the improved module is shortened from 250ns to 100ns, the shrinking amplitude is about 60%, the steps existing in the collector-emitter voltage at the initial stage of chip opening are obviously disappeared, the opening loss is correspondingly reduced, and the working frequency of the module is improved.
Therefore, after the improvement, the parasitic inductance shared by the power loop and the drive control loop is reduced, the mutual inductance between the power loop and the signal control loop is reduced, the influence of the current change of the power loop on the voltage change of the signal control loop is reduced, and the rising speed of the grid-emitter voltage of the chip is increased, so that the opening speed of the module is increased.
The foregoing is merely a preferred embodiment of the present utility model, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present utility model, and such modifications and variations should also be regarded as being within the scope of the utility model.
Claims (6)
1. A multi-chip parallel half-bridge IGBT module is characterized in that an emitter signal copper layer is additionally arranged on a copper-clad ceramic lining plate, emitter voltage signals of all IGBT chips are directly led out from a corresponding bonding wire cluster, and the led-out emitter voltage signals are transmitted to an emitter signal terminal through the emitter signal copper layer.
2. The multi-chip parallel half-bridge IGBT module of claim 1, wherein an upper bridge arm emitter signal copper layer and a lower bridge arm emitter signal copper layer are additionally arranged on the copper-clad ceramic lining plate;
the emitter voltage signals of all IGBT chips of the upper bridge arm are directly led out from the corresponding bonding wire clusters, and the emitter voltage signals led out from the upper bridge arm are transmitted to the emitter signal terminals of the upper bridge arm through the emitter signal copper layer of the upper bridge arm;
emitter voltage signals of all IGBT chips of the lower bridge arm are directly led out from the corresponding bonding wire clusters, and the emitter voltage signals led out from the lower bridge arm are transmitted to emitter signal terminals of the lower bridge arm through emitter signal copper layers of the lower bridge arm.
3. The multi-chip parallel half-bridge IGBT module of claim 2 wherein the upper leg emitter signal copper layer is located outside the upper leg gate signal copper layer.
4. A multi-chip parallel half-bridge IGBT module according to claim 2 or 3, characterized in that the upper leg emitter signal copper layer comprises a first emitter signal copper layer and a second emitter signal copper layer connected by bond wires, the two emitter signals of the upper leg being transferred to the first emitter signal copper layer and the second emitter signal copper layer, respectively.
5. The multi-chip parallel half-bridge IGBT module of claim 2 wherein the lower leg emitter signal copper layer is located outside the lower leg gate signal copper layer.
6. The multi-chip parallel half-bridge IGBT module of claim 2 or 5 wherein the lower leg emitter signal copper layer comprises a third emitter signal copper layer and a fourth emitter signal copper layer connected by bond wires, the two emitter signals of the lower leg being transferred to the third emitter signal copper layer and the fourth emitter signal copper layer, respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320685253.1U CN219937044U (en) | 2023-03-31 | 2023-03-31 | Multi-chip parallel half-bridge IGBT module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320685253.1U CN219937044U (en) | 2023-03-31 | 2023-03-31 | Multi-chip parallel half-bridge IGBT module |
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| Publication Number | Publication Date |
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| CN219937044U true CN219937044U (en) | 2023-10-31 |
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| CN202320685253.1U Active CN219937044U (en) | 2023-03-31 | 2023-03-31 | Multi-chip parallel half-bridge IGBT module |
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