CN219918911U

CN219918911U - Integrator circuit

Info

Publication number: CN219918911U
Application number: CN202321042224.XU
Authority: CN
Inventors: 王桂玲; 何佳; 刘俊; 冯宏庆
Original assignee: Hangzhou Hikmicro Sensing Technology Co Ltd
Current assignee: Hangzhou Hikmicro Sensing Technology Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-10-27
Anticipated expiration: 2033-04-28

Abstract

The application provides an integrator circuit which comprises an input end, an acquisition circuit, a first switching circuit, an integration operational amplifier circuit, a second switching circuit and a controller. The input terminal is used for inputting signals. The acquisition circuit is connected with the input end and is used for acquiring signals. The first switch circuit is connected with the acquisition circuit. The integrating operational amplifier circuit is connected with the first switch circuit. The second switching circuit is connected with the integrating operational amplifier circuit. The controller is connected with the first switch circuit and the second switch circuit. The controller respectively controls the first switch circuit and the second switch circuit to enable the acquisition circuit to acquire the input signals and input the signals to the integrating operational amplifier circuit. The application controls the first switch circuit and the second switch circuit through the controller, so that signal transmission paths of signals at the input end and the output end of the integral operational amplifier circuit are changed, the problems of direct current imbalance and low-frequency 1/f noise of the integral operational amplifier circuit can be solved, and the signal to noise ratio of the whole integrator circuit is improved.

Description

Integrator circuit

Technical Field

The application relates to the technical field of integrated circuits, in particular to an integrator circuit.

Background

In addition to quantization noise and thermal noise, the summing integral analog-to-digital conversion circuit also has non-ideal factors such as direct current offset of an integral operational amplifier circuit, low-frequency 1/f noise and the like. The integrator circuit may cause a reduction in the signal-to-noise ratio of the entire integrator circuit due to dc offset of the integrating op-amp circuit and the presence of low frequency 1/f noise.

Disclosure of Invention

The utility model provides an integrator circuit capable of improving DC offset and low-frequency 1/f noise of an integrating operational amplifier circuit.

The present utility model provides an integrator circuit comprising:

an input terminal for inputting a signal;

the acquisition circuit is connected with the input end and is used for acquiring the signals;

the first switch circuit is connected with the acquisition circuit;

the integrating operational amplifier circuit is connected with the first switch circuit;

the second switch circuit is connected with the integrating operational amplifier circuit; and

The controller is connected with the first switch circuit and the second switch circuit; the controller respectively controls the first switch circuit and the second switch circuit, so that the acquisition circuit acquires the input signals and inputs the signals to the integrating operational amplifier circuit.

Optionally, the input end includes a first acquisition input end and a second acquisition input end; the integrator circuit comprises a quantizer, and is connected with the integrating operational amplifier circuit through the second switch circuit;

the integrator circuit comprises a first feedforward branch connected between the first acquisition input end and the quantizer; and is connected between the second acquisition input end and the quantizer; and/or

The integrator circuit comprises a second feedforward branch connected between the second acquisition input end and the quantizer; and the quantizer is connected between the first acquisition input end and the quantizer.

Optionally, the input end includes a first acquisition input end and a second acquisition input end; the acquisition circuit comprises a first acquisition switch, an acquisition capacitor and a second acquisition switch, wherein the first acquisition switch is connected with the first acquisition input end, the second acquisition input end and the acquisition capacitor, and the second acquisition switch is connected with the acquisition capacitor; the controller is connected with the first acquisition switch and the second acquisition switch, and respectively controls the on-off of the first acquisition switch and the second acquisition switch, so that the acquisition capacitor alternately acquires signals input by the first acquisition input end and the second acquisition input end.

Optionally, the first acquisition switch comprises a first sub-acquisition switch and a second sub-acquisition switch; the second acquisition switch comprises a third sub-acquisition switch and a fourth sub-acquisition switch;

the controller is used for controlling the second sub-acquisition switch and the third sub-acquisition switch to be synchronously switched on or off; or (b)

The controller is used for controlling the first sub-acquisition switch and the fourth sub-acquisition switch to be synchronously disconnected or synchronously connected.

Optionally, the first collection switch includes a first sub-collection switch and a second sub-collection switch, and the collection capacitor includes a first collection capacitor and a second collection capacitor; the first sub-acquisition switch is respectively connected between the first acquisition input end and the first acquisition capacitor; the second acquisition input end is connected with the second acquisition capacitor; the second sub-acquisition switch is respectively connected between the second acquisition input end and the first acquisition capacitor; and between the first acquisition input and the second acquisition capacitor; the controller is used for controlling one of the first sub-acquisition switch and the second sub-acquisition switch to be connected and the other to be disconnected.

Optionally, the integrator circuit includes a reset node; the second acquisition switch comprises a third sub-acquisition switch and a fourth sub-acquisition switch; the third sub-acquisition switch is connected between the first acquisition capacitor and the reset node; and between the second acquisition capacitor and the reset node; the fourth sub-acquisition switch is connected between the first acquisition capacitor and the first input end of the first switching circuit; the second acquisition capacitor is arranged between the second input end of the first switch circuit; the controller is used for controlling one of the third sub-acquisition switch and the fourth sub-acquisition switch to be connected and the other to be disconnected.

Optionally, the integrator circuit further comprises an integrating capacitor connected with the integrating operational amplifier circuit; the input end comprises a first feedback input end and a second feedback input end; the integrator circuit comprises a feedback circuit connected with the first feedback input end and the second feedback input end, the feedback circuit comprises a first feedback switch, a feedback capacitor and a second feedback switch, the first feedback switch is connected with the first feedback input end, the second feedback input end and the feedback capacitor, the feedback capacitor is connected with the second feedback switch, and the second feedback switch is connected with the integration capacitor; the controller is connected with the first feedback switch and the second feedback switch, and respectively controls the on-off of the first feedback switch and the second feedback switch, so that the feedback capacitor alternately feeds back the feedback signals input by the first feedback input end and the second feedback input end.

Optionally, the second acquisition switch comprises a third sub-acquisition switch and a fourth sub-acquisition switch; the first feedback switch comprises a first sub feedback switch and a second sub feedback switch;

The controller is used for controlling the first sub-feedback switch to be turned on or turned off in a delayed manner after a preset period of time relative to the third sub-acquisition switch; or (b)

The controller is used for controlling the second sub-feedback switch to be turned off or turned on in a delayed mode after a preset period of time relative to the fourth sub-acquisition switch.

Optionally, the first feedback switch includes a first sub feedback switch and a second sub feedback switch, and the feedback capacitor includes a first feedback capacitor and a second feedback capacitor; the first sub-feedback switch is connected between the first feedback input end and the first feedback capacitor; and is connected between the second feedback input terminal and the second feedback capacitor; the second feedback switch is connected between the second feedback input end and the first feedback capacitor; the first feedback input end and the second feedback capacitor are connected; the controller is used for controlling one of the first sub-feedback switch and the second sub-feedback switch to be connected and the other to be disconnected.

Optionally, the integrating capacitor includes a first integrating capacitor and a second integrating capacitor; the integrator circuit includes a reset node; the second feedback switch comprises a third sub feedback switch and a fourth sub feedback switch; the third sub-feedback switch is connected between the first feedback capacitor and the first integrating capacitor; and between the second feedback capacitance and the second integration capacitance; the fourth sub-feedback switch is connected between the first feedback capacitor and the second integration capacitor; and between the second feedback capacitance and the first integrating capacitance; the controller is used for controlling one of the third sub-feedback switch and the fourth sub-feedback switch to be on, and the other sub-feedback switch to be off.

Optionally, the second acquisition switch includes a third sub-acquisition switch; the second feedback switch comprises a third sub feedback switch and a fourth sub feedback switch; the integrator circuit comprises a quantizer, and is connected with the integrating operational amplifier circuit through the second switch circuit; the quantizer includes a first output and a second output;

the controller controls the on-off of the third sub-feedback switch according to the signal switch or the NOT logic of the first output end and the third sub-acquisition switch; or (b)

The controller controls the on-off of the fourth sub-feedback switch according to the signal switch and the NAND logic of the second output end and the third sub-acquisition switch.

Optionally, the integrator circuit includes a reset node; the integrator circuit further comprises a reset switch connected with the reset node; the reset switch comprises a first reset switch and a second reset switch, the first reset switch and the second reset switch are connected with the controller and the reset node, and the controller is used for controlling the first reset switch and the second reset switch to be disconnected for resetting once when the collection quantity of the collection circuit reaches an upper limit threshold value.

According to the integrator circuit provided by the embodiment of the application, the first switch circuit and the second switch circuit are respectively arranged at the input end and the output end of the integrating operational amplifier circuit, and are connected with the first switch circuit and the second switch circuit through the controller so as to respectively control the first switch circuit and the second switch circuit, so that the acquisition circuit acquires an input signal and inputs the signal into the integrating operational amplifier circuit.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 shows a functional block diagram of one embodiment of the integrator circuit of the present application.

Fig. 2 is a circuit diagram of the integrator circuit shown in fig. 1.

Fig. 3 is a schematic diagram of the first switch circuit or the second switch circuit of the integrator circuit shown in fig. 2.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one location or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

The application provides an integrator circuit which comprises an input end, an acquisition circuit, a first switching circuit, an integration operational amplifier circuit, a second switching circuit and a controller. The input terminal is used for inputting signals. The acquisition circuit is connected with the input end and is used for acquiring signals. The first switch circuit is connected with the acquisition circuit. The integrating operational amplifier circuit is connected with the first switch circuit. The second switching circuit is connected with the integrating operational amplifier circuit. The controller is connected with the first switch circuit and the second switch circuit. The controller respectively controls the first switch circuit and the second switch circuit to enable the acquisition circuit to acquire the input signals and input the signals to the integrating operational amplifier circuit.

The application provides an integrator circuit capable of improving DC offset and low-frequency 1/f noise of an integrating operational amplifier circuit. The integrator circuit of the present application will be described in detail with reference to the accompanying drawings. The features of the examples and embodiments described below may be combined with each other without conflict.

The integrator circuit is applied to the summing integrating analog-to-digital conversion circuit. The summing integral analog-to-digital conversion circuit is mainly used for realizing high-precision analog-to-digital conversion of direct current or low-speed signals, and the application fields are instruments, meters, sensor readout circuits and the like. The summing integral analog-to-digital conversion circuit comprises 1-order, 2-order or higher-order structures. In terms of circuit structure, the summing integration analog-to-digital conversion circuit further comprises a reset operation, namely the summing integration analog-to-digital conversion circuit resets and clears the integrator circuit before each acquisition signal is transformed. Thus, the existence of a periodic reset operation is one of the main features of the summing integrating analog-to-digital conversion circuit. In this embodiment, the summing integrating analog-to-digital conversion circuit may be a Sigma-delta ADC.

Fig. 1 shows a functional block diagram of an embodiment of the integrator circuit 1 of the present application. As shown in fig. 1, the integrator circuit 1 includes an input terminal 11, an acquisition circuit 12, an integrating operational amplifier circuit 13, a switching circuit 14, and a controller 15. Wherein the input 11 is for inputting a signal. The acquisition circuit 12 is connected to the input 11 and is used for acquiring the signal. The switching circuit 14 includes a first switching circuit 141 and a second switching circuit 142, the first switching circuit 141 is connected to the acquisition circuit 12, the integrating operational amplifier circuit 13 is connected to the first switching circuit 141, and the second switching circuit 142 is connected to the integrating operational amplifier circuit 13. In this embodiment, the first switch circuit 141 and the second switch circuit 142 are respectively connected to the input terminal and the output terminal of the integrating operational amplifier circuit 13. The controller 15 is connected to the first switch circuit 141 and the second switch circuit 142, and the controller 15 controls the first switch circuit 141 and the second switch circuit 142, respectively, so that the acquisition circuit 12 acquires an input signal and inputs the acquired signal to the integrating operational amplifier circuit 13. The input end of the integrating operational amplifier circuit 13 receives the signal collected by the collection circuit 12 through the first switch circuit 141, and the output end of the integrating operational amplifier circuit 13 outputs the signal through the second switch circuit 142. In the present embodiment, the first and second switching circuits 141 and 142 may be chopper switches. The controller 15 is configured to control on/off of the chopper switch, so that both the signal transmission path of the input signal and the signal transmission path of the output signal of the integrating operational amplifier circuit 13 are changed, and the problems of dc offset and low-frequency 1/f noise of the integrating operational amplifier circuit 13 can be improved, thereby improving the signal-to-noise ratio of the whole integrator circuit 1.

The integrating operational amplifier circuit 13 includes two or more stages of integrating operational amplifier circuits. In this embodiment, the integrating operational amplifier circuit 13 may be an integrating operational amplifier circuit located at the head end. In addition, the integrating operational amplifier circuit 13 further includes an integrating operational amplifier circuit (not shown) and the like sequentially cascaded after the integrating operational amplifier circuit 13 located at the head end. The noise of the integrating operational amplifier circuit 13 located at the head end has the greatest influence on the performance of the integrator circuit 1, and thus it is necessary to improve the integrating operational amplifier circuit 13 to improve the influence of the low frequency noise of the integrator circuit 1 on the signal-to-noise ratio. In this embodiment, after receiving the signal, the input terminal 11 first transmits the collected signal from the integrating operational amplifier 13 through the first switch circuit 141, then transmits the collected signal through the second switch circuit 142, and then sequentially transmits the collected signal in the integrating operational amplifier circuit cascaded after the integrating operational amplifier circuit 13. In the above transmission process, the controller 15 controls the first switch circuit 141 and the second switch circuit 142, and under the combined action of the first switch circuit 141 and the second switch circuit 142, the signal transmission paths of the signal at the input end and the output end of the integrating operational amplifier circuit 13 are changed. The signal is synchronously changed in the signal transmission path of the input end of the integrating operational amplifier circuit which is cascaded behind the second switch circuit 142. In this way, the input end and the output end of the integrating operational amplifier circuit 13 are respectively provided with the first switch circuit 141 and the second switch circuit 142, and the first switch circuit 141 and the second switch circuit 142 are connected through the controller 15 so as to respectively control the first switch circuit 141 and the second switch circuit 142, so that the acquisition circuit 12 acquires an input signal and inputs the signal into the integrating operational amplifier circuit 13, and under the combined action of the first switch circuit 141 and the second switch circuit 142, the signal transmission paths of the signal at the input end and the output end of the integrating operational amplifier circuit 13 are changed, and the problems of direct current imbalance and low-frequency 1/f noise of the integrating operational amplifier circuit 13 can be improved, thereby improving the signal-to-noise ratio of the whole integrator circuit 1. In addition, the first switch circuit 141 and the second switch circuit 142 are respectively arranged at the input end and the output end of the integrating operational amplifier circuit 13, so that the design of the circuit can be reduced, the increase of the processing area or the detector area is avoided, the cost is reduced, the input voltage of the integrating operational amplifier circuit 13 can be brought, and the input impedance of the integrating operational amplifier circuit 13 is reduced.

Fig. 2 shows a circuit diagram of the integrator circuit 1 shown in fig. 1. Fig. 3 is a schematic diagram of the first switch circuit 141 or the second switch circuit 142 of the integrator circuit 1 shown in fig. 2. As shown in connection with fig. 1-3, the first switching circuit 141 may be a first chopper switch. The second switching circuit 142 may be a second chopper switch. The controller 15 is connected with the first chopper switch and the second chopper switch respectively, and controls the on-off of the first chopper switch and the second chopper switch respectively so as to switch the signal transmission paths of the input end and the output end of the integrating operational amplifier circuit 13. In this embodiment, the dc offset voltage of the integrating operational amplifier circuit 13 of the integrator circuit 1 is adjusted by continuously switching chopper switches in the first switch circuit 141 and the second switch circuit 142, which are disposed at the input end and the output end of the integrating operational amplifier circuit 13, by using chopper technology. The chopping technology demodulates the signal back to the fundamental frequency by modulating the low-frequency noise and the offset voltage to the high frequency, and then eliminates the influence of the low-frequency noise and the offset voltage through filtering. As shown in connection with fig. 1 to 3, the provided signal is a square wave signal with a duty cycle of 50%, and the fourier expression thereof is:

wherein the coefficients are

The chopper cancellation detuning process includes: the square wave M1 (t) modulates the input Vin, i.e. the two are multiplied in the time domain, i.e. only at f _chop There are components at odd harmonic frequencies. The modulated signal vin·m1 (t), the low-frequency noise VN, and the offset voltage Vos are amplified as input signals to the integrating operational amplifier circuit 13. The amplified output signal VA is then demodulated by multiplying with M2 (t), so that the amplified Vin.M1 (t) signal is demodulated to carry f only _chop Components of even harmonic frequencies, whereas VN and Vos are shifted to carry f only because they are modulated only once _chop On the high frequency components at odd harmonic frequencies. The output signal Vout is passed through a low-pass filter with a bandwidth slightly greater than the cut-off frequency fT of the input signal, so as to obtain the amplified initial signal Vin.

In this embodiment, the controller 15 controls the first switch circuit 141 and the second switch circuit 142, and under the combined action of the first switch circuit 141 and the second switch circuit 142, the signal transmission paths of the signal at the input end and the output end of the integrating operational amplifier circuit 13 are changed, so that the problems of direct current imbalance and low frequency 1/f noise of the integrating operational amplifier circuit 13 can be improved, and the signal-to-noise ratio of the whole integrator circuit 1 can be improved.

As shown in connection with fig. 1 and 2, the input 11 comprises a collecting input 111. Acquisition input 111 includes a first acquisition input VINP and a second acquisition input VINN. The acquisition circuit 12 is connected with the first acquisition input terminal VINP and the second acquisition input terminal VINN, and the acquisition circuit 12 receives the positive acquisition signal and the negative acquisition signal respectively through the first acquisition input terminal VINP and the second acquisition input terminal VINN.

In the embodiment shown in fig. 2, the acquisition circuit 12 comprises a first acquisition switch 121, an acquisition capacitor 122 and a second acquisition switch 123. The first acquisition switch 121 is connected to the first acquisition input terminal VINP, the second acquisition input terminal VINN, and the acquisition capacitor 122, and the second acquisition switch 123 is connected to the acquisition capacitor 122. The controller 15 is connected with the first collecting switch 121 and the second collecting switch 123, and controls the on-off of the first collecting switch 121 and the second collecting switch 123 respectively, so that the collecting capacitor 122 alternately collects signals input by the first collecting input end VINP and the second collecting input end VINN. The present embodiment uses the dual-acquisition and dual-linear integration technique to eliminate the capacitance mismatch of the acquisition capacitor 122, and improve the signal-to-noise ratio of the system, i.e. improve the accuracy of the system.

In the embodiment shown in fig. 2, the first acquisition switch 121 includes a first sub-acquisition switch S1 and a second sub-acquisition switch S2. The pickup capacitor 122 includes a first pickup capacitor CSP and a second pickup capacitor CSN. The first sub-acquisition switch S1 is respectively connected between the first acquisition input end VINP and the first acquisition capacitor CSP; and the second acquisition input end VINN is connected with the second acquisition capacitor CSN. The second sub-acquisition switch S2 is respectively connected between the second acquisition input end VINN and the first acquisition capacitor CSP; and between the first acquisition input terminal VINP and the second acquisition capacitor CSN. The controller 15 is used for controlling one of the first sub-collection switch S1 and the second sub-collection switch S2 to be turned on and the other to be turned off. In this embodiment, the first sub-collection switch S1 and the second sub-collection switch S2 are a pair of complementary switches. When the acquisition is performed, the controller 15 controls the first sub-acquisition switch S1 to be turned on, and controls the second sub-acquisition switch S2 to be turned off. The controller 15 controls the first sub-collection switch S1 to be turned off and controls the second sub-collection switch S2 to be turned on. In this embodiment, the controller 15 controls the two first sub-acquisition switches S1 and the two second sub-acquisition switches S2 to perform non-overlapping switching.

In the embodiment shown in fig. 2, integrator circuit 1 comprises a reset node VCM. The second acquisition switch 123 includes a third sub-acquisition switch Φ1 and a fourth sub-acquisition switch Φ2. The third sub-acquisition switch phi 1 is connected between the first acquisition capacitor CSP and the reset node VCM; and is connected between the second acquisition capacitor CSN and the reset node VCM. The fourth sub-collection switch phi 2 is connected between the first collection capacitor CSP and the first input end 141a of the first switch circuit 141; and is connected between the second collecting capacitor CSN and the second input terminal 141b of the first switch circuit 141. The controller 15 is used for controlling one of the third sub-acquisition switch phi 1 and the fourth sub-acquisition switch phi 2 to be turned on and the other to be turned off. In this embodiment, the third sub-acquisition switch Φ1 and the fourth sub-acquisition switch Φ2 are a pair of complementary switches. When the collection is performed, the controller 15 controls the third sub-collection switch phi 1 to be turned on, and controls the fourth sub-collection switch phi 2 to be turned off. In this embodiment, the controller 15 controls the two third sub-acquisition switches Φ1 and the two fourth sub-acquisition switches Φ2 to perform non-overlapping switching.

In this embodiment, the controller 15 is configured to control the second sub-collection switch S2 to be synchronously turned on or off with the third sub-collection switch Φ1. The controller 15 is configured to control the second sub-acquisition switch S2 to be turned on synchronously with the third sub-acquisition switch Φ1. The second sub-collection switch S2 is synchronously disconnected from the third sub-collection switch Φ1. In this embodiment, the controller 15 is configured to control the first sub-collection switch S1 and the fourth sub-collection switch Φ2 to be synchronously turned on or off. The controller 15 is configured to control the first sub-acquisition switch S1 and the fourth sub-acquisition switch Φ2 to be turned on synchronously. The first sub-collection switch S1 is synchronously disconnected from the fourth sub-collection switch Φ2.

In this embodiment, the acquisition is performed separately from the integration, for example, acquisition-first-integration-last-integration. In this embodiment, the first collection switch 121 and the second collection switch 123 are configured to separate the collection process from the integration process, so that the requirement on the performance of the operational amplifier can be reduced, and the design difficulty of the integrated operational amplifier is reduced.

In the embodiment shown in connection with fig. 1 and 2, the operation of the acquisition circuit 12 comprises: when the controller 15 controls the third sub-collection switch phi 1 to be closed, controls the second sub-collection switch S2 to be closed, and controls the first sub-collection switch S1 to be opened, the right pole plates of the first collection capacitor CIP and the second collection capacitor CIN are reset to a reset node VCM, and the voltage of the reset node is stable. The left electrode plates of the first acquisition capacitor CIP and the second acquisition capacitor CIN are respectively connected with the first acquisition input end VINP and the second acquisition input end VINN. When the controller 15 controls the fourth sub-collection switch phi 2 to be closed, controls the second sub-collection switch S2 to be opened, and controls the first sub-collection switch S1 to be closed, the voltages of the left electrode plates of the first collection capacitor CIP and the second collection capacitor CIN are exchanged with the voltage when the third sub-collection switch phi 1 is closed, and therefore the voltages of the left electrode plates of the first collection capacitor CIP and the second collection capacitor CIN are exchanged with the voltage when the third sub-collection switch phi 1 is closed. Thus, the voltage acquired by the acquisition circuit 12 is vinp+vinn each time, and thus the acquired voltage is ± (vinp+vinn), so the acquired voltage can be doubled by adopting the dual acquisition structure and dual linear integration of the embodiment.

In the above scheme, the controller 15 controls the chopper switches of the first switch circuit 141 and the second switch circuit 142, and controls the mutual matching of the first acquisition switch 121 and the second acquisition switch 123 in the acquisition circuit 12, and the acquisition capacitor 122 of the acquisition circuit 12 is utilized to double the amplitude of the input signal through the double-acquisition structure, so that the signal power is correspondingly increased, and the requirement on the system bottom noise can be greatly reduced under the condition of obtaining the same signal-to-noise ratio. Assume that the dominant thermal noise generated by the first acquisition switch 121, which limits the background noise, is KT/C noise. According to the signal-to-noise ratio = signal power/noise power, reducing the requirement for noise means that when the same signal-to-noise ratio is obtained, KT (constant)/C noise can be increased, that is, the acquisition capacitor C can be reduced, and the reduction of the acquisition capacitor can reduce the circuit power consumption on the one hand and the circuit area on the other hand.

In the embodiment shown in fig. 2, the integrator circuit 1 further comprises an integrating capacitor 16 connected to the integrating op-amp circuit 13. Input 11 also includes feedback input 112. The feedback input 112 includes a first feedback input VREFP and a second feedback input VREFN. The integrator circuit 1 further comprises a feedback circuit 17 connected to the first feedback input VREFP, the second feedback input VREFN, the feedback circuit 17 receiving a positive feedback signal and an inverted feedback signal via the first feedback input VREFP, the second feedback input VREFN, respectively. The feedback circuit 17 includes a first feedback switch 171, a feedback capacitor 172, and a second feedback switch 173, where the first feedback switch 171 is connected to the first feedback input VREFP, the second feedback input VREFN, and the feedback capacitor 172, the feedback capacitor 172 is connected to the second feedback switch 173, and the second feedback switch 173 is connected to the integrating capacitor 16. The controller 15 is connected to the first feedback switch 171 and the second feedback switch 173, and controls the on-off of the first feedback switch 171 and the second feedback switch 173 respectively, so that the feedback capacitor 172 alternately feeds back the feedback signals input by the first feedback input terminal VREFP and the second feedback input terminal VREFN. The present embodiment uses a dual feedback, bilinear integration technique to eliminate the capacitance mismatch of the feedback capacitor 172 and improve the system signal to noise ratio, i.e., improve the accuracy of the system.

In the embodiment shown in fig. 2, the first feedback switch 171 includes a first sub feedback switch S3 and a second sub feedback switch S4, and the feedback capacitor 172 includes a first feedback capacitor CFBP and a second feedback capacitor CFBN; the first sub-feedback switch S3 is connected between the first feedback input terminal VREFP and the first feedback capacitor CFBP; and is connected between the second feedback input terminal VREFN and the second feedback capacitor CFBN. The second sub-feedback switch S4 is connected between the second feedback input terminal VREFN and the first feedback capacitor CFBP; and is connected between the first feedback input terminal VREFP and the second feedback capacitor CFBN. The controller 15 is configured to control one of the first sub-feedback switch S3 and the second sub-feedback switch S4 to be turned on and the other to be turned off. In this embodiment, the first sub-feedback switch S3 and the second sub-feedback switch S4 are a pair of complementary switches. When feedback is performed, the controller 15 controls the first sub feedback switch S3 to be turned on, and controls the second sub feedback switch S4 to be turned off. The controller 15 controls the first sub-feedback switch S3 to be turned off and controls the second sub-feedback switch S4 to be turned on. In this embodiment, the controller 15 controls the two first sub-feedback switches S3 and the two second sub-feedback switches S4 to perform non-overlapping switching.

In the embodiment shown in fig. 2, the integrating capacitor 16 includes a first integrating capacitor CIP and a second integrating capacitor CIN. The second feedback switch 173 includes a third sub feedback switch RP and a fourth sub feedback switch LN. The third sub-feedback switch RP is connected between the first feedback capacitor CFBP and the first integration capacitor CIP; and is connected between the second feedback capacitor CFBN and the second integrating capacitor CIN. The fourth sub-feedback switch LN is connected between the first feedback capacitor CFBP and the second integrating capacitor CIN; and is connected between the second feedback capacitor CFBN and the first integration capacitor CIP. The controller 15 is configured to control one of the third sub-feedback switch RP and the fourth sub-feedback switch LN to be turned on and the other to be turned off. In this embodiment, the third sub-feedback switch RP and the fourth sub-feedback switch LN are a pair of complementary switches. When feedback is performed, the controller 15 controls the third sub feedback switch RP to be turned on and controls the fourth sub feedback switch LN to be turned off. The controller 15 controls the third sub-feedback switch RP to be turned off and controls the fourth sub-feedback switch LN to be turned on. In this embodiment, the controller 15 controls the two third sub-feedback switches RP and the two fourth sub-feedback switches LN to perform non-overlapping switching.

In this embodiment, the controller 15 is configured to control the first sub-feedback switch S3 to be turned on or off with respect to the third sub-collection switch Φ1 in a delay manner after a preset period. When the controller 15 controls the third sub-collection switch phi 1 to be turned on, the first sub-feedback switch S3 is turned on in a delayed manner after a preset period of time relative to the third sub-collection switch phi 1. When the controller 15 controls the third sub-collection switch phi 1 to be turned off, the first sub-feedback switch S3 is turned off in a delayed manner after a preset period of time relative to the third sub-collection switch phi 1. The controller 15 controls the first sub-feedback switch S3 to be turned on or turned off in a delayed manner after a preset period of time relative to the third sub-acquisition switch phi 1, so that feedback after acquisition is finished can be ensured, and the signal stability is better.

In the embodiment shown in fig. 2, the integrator circuit 1 further comprises a quantizer 18, which is connected with the integrating op-amp circuit 13 via a second switching circuit 142 and with the integrating capacitor 16. The quantizer 18 comprises a first output DN and a second output DH. The controller 15 controls the on-off of the third sub-feedback switch RP according to the first output DN and the switch signal or logic of the third sub-collection switch Φ1. The controller 15 controls the on-off of the fourth sub-feedback switch LN according to the signal switch and the nand logic of the second output terminal DH and the third sub-acquisition switch Φ1. In the present embodiment, the timing of the third sub-feedback switch RP is obtained by performing nor logic on the output signal of the first output terminal DN of the quantizer 18 and the complementary clock of the third sub-acquisition switch Φ1. The timing of the fourth sub-feedback switch LN is obtained by nand logic of the second output DH of the quantizer 18 and the complementary clock of the third sub-acquisition switch Φ1. The output end of the quantizer 18 controls the on or off of the third sub-feedback switch RP and the fourth sub-feedback switch LN of the second feedback switch 173 of the feedback circuit 17 to select the value of the feedback voltage through the logical operation with the timing sequence of the third sub-collection switch Φ1, so that the voltages when the left plate voltages of the first feedback capacitor CFBP and the second feedback capacitor CFBN are closed and the fourth sub-collection switch Φ2 are exchanged. In this way, the voltage fed back by the feedback circuit 17 is vrefp+vrefn each time, and thus the reference voltage fed back is ± (vrefp+vrefn), so the embodiment can double the reference voltage by using the dual-acquisition structure, and improve the dynamic range of the integrator circuit 1.

In the embodiment shown in fig. 2, integrator circuit 1 comprises a reset node VCM. The integrator circuit 1 further comprises a reset switch 19 connected to the reset node VCM. The reset switch 19 includes a first reset switch 191 and a second reset switch 192, and is connected to the controller 15 and the reset node VCM. The first reset switch 191 is connected in parallel with the first integration capacitance CIP, and the second reset switch 192 is connected in parallel with the first integration capacitance CIN. The controller 15 is configured to control the first reset switch 191 and the second reset switch 192 to be turned off for resetting once when the collection number of the collection circuits 12 reaches the upper limit threshold. In this embodiment, the reset switch 19 is used to reset once every acquisition of a certain number of pulse signals. By setting the reset switch 19 and controlling the reset switch 19 (the first reset switch 191 and the second reset switch 192) through the controller 15, the reset operation is performed after each quantization is completed, so that the collection between two adjacent times cannot interfere with each other, and the structure is applied to the application of multiplexing the same analog-digital conversion circuit by multiple channels.

In the embodiment shown in fig. 2, the integrator circuit 1 further comprises a feed forward branch 20 connected to the input 11 and to the quantizer 18. The feed-forward branch 20 comprises a first feed-forward branch 201 and a second feed-forward branch 202. The first feedforward branch 201 is connected between the first acquisition input VINP and the quantizer 18; and between the second acquisition input VINN and the quantizer 18. The second feedforward branch 202 is connected between the second acquisition input VINN and the quantizer 18; and is connected between the first acquisition input VINP and the quantizer 18. In this embodiment, the first feedforward branch 201 includes a first feedforward switch K1 connected between the first acquisition input VINP and the first input 18a of the quantizer 18, respectively; and is connected between the second acquisition input VINN and the second input 18b of the quantizer 18. The controller 15 is connected with the first feedforward switch K1, and is used for controlling the on-off of the first feedforward switch K1 to control whether the first feedforward branch 201 is connected, so that the swing of the integrator circuit 1 can be reduced, the stability of the multistage integration operational amplifier circuit 13 is improved, and the multistage integration operational amplifier circuit is more suitable for being used as a high-precision summation integration analog-digital conversion circuit. In this embodiment, the second feedforward branch 202 includes a second feedforward switch K2 connected between the second acquisition input VINN and the first input 18a of the quantizer 18, respectively; and is connected between the first acquisition input VINP and the second input 18b of the quantizer 18. The controller 15 is connected to the second feedforward switch K2, and is configured to control on/off of the second feedforward switch K2 to control whether the second feedforward branch 202 is connected, so that the swing of the integrator circuit 1 can be reduced, the stability of the multistage integrating operational amplifier circuit 13 is improved, and the multistage integrating operational amplifier circuit is more suitable for being used as a high-precision summation integrating analog-digital conversion circuit.

In the embodiment shown in fig. 2, the first feedforward branch 201 further includes a first feedforward capacitor CFFP connected between the first feedforward switch K1 and the first input terminal 18a of the quantizer 18, respectively; and is connected between the second feedforward switch K2 and the first input 18a of the quantizer 18. In the embodiment shown in fig. 2, the second feedforward branch 202 further includes a second feedforward capacitor CFFN connected between the first feedforward switch K1 and the second input terminal 18b of the quantizer 18, respectively; and between the second feedforward switch K2 and the second input 18b of the quantizer 18. The present embodiment provides better stability of the overall integrator circuit 1 by providing the feedback branch 20 (first feed forward branch 201 and second feed forward branch 202).

In the embodiment shown in fig. 2, the controller 15 includes a plurality of control ports 151, which are electrically connected to the various switches shown in the embodiment of fig. 2 (including, for example, the first chopper switch, the second chopper switch, the first acquisition switch 121, the second acquisition switch 123, the first feedback switch 171, the second feedback switch 173, the first feedforward switch K1, and the second feedforward switch K2), and the controller 15 is configured to control the on/off of the various switches shown in the embodiment of fig. 2 through the plurality of control ports 151. For the sake of brevity, only three control ports 151 of the controller 15 are shown in the embodiment shown in fig. 2, and are not limiting in the present application. In the embodiment shown in fig. 2, the electrical connection between the controller 15 and the various switches shown in the embodiment of fig. 2 through the plurality of control ports 151 is omitted, but the electrical connection is actually correspondingly connected, which is not described herein.

In this embodiment, the controller 15 may include any suitable programmable circuit or device, such as a digital signal processor (Digital Signal Processor, DSP), a field programmable gate array (Field Programmable Gate Array, FPGA), a programmable logic controller (Programmable Logic Controller, PLC), an application specific integrated circuit (APPlication SPecific Integrated Circuit, ASIC), and a single chip microcomputer, and may be controlled by a combination of software and hardware. The present application is not limited thereto.

The application combines the double acquisition technology and the double linear integration technology, realizes the high integration dynamic range, eliminates the capacitance mismatch of the acquisition capacitor, and is suitable for a high-precision summation integration analog-digital conversion circuit. The mismatch of the acquisition capacitor is eliminated through the first acquisition switch 121 (the first sub-acquisition switch S1 and the second sub-acquisition switch S2) of the acquisition circuit 12, and the first switch circuit 141 and the second switch circuit 142 before and after the integration operational amplifier circuit 13, under the combined action of the first switch circuit 141 and the second switch circuit 142, the signal transmission paths of the signal at the input end and the output end of the integration operational amplifier circuit 13 are changed, and the problems of direct current offset and low-frequency 1/f noise of the integration operational amplifier circuit can be improved, so that the signal-to-noise ratio of the whole integrator circuit is improved, and the signal-to-noise ratio of the whole integrator circuit is improved. In addition, in this embodiment, the integrating operational amplifier circuit 13 may be connected in series between two output ends of the integrating operational amplifier circuit 13 and the quantizer 18 to form a multistage cascade integrating operational amplifier circuit, which is not limited in the present application.

It should be noted that the quantizer 18 may be a comparator. The voltage may be the same or different for the reset node VCM connected to the two third sub-acquisition switches Φ1, the reset node VCM connected to the fourth sub-acquisition switch Φ2, and the reset node VCM connected to the first and second acquisition capacitors CIP and CIN. In this embodiment, the voltages of the reset nodes VCM are all the same, and are all 0V, which is not limited in the present application.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims. It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. An integrator circuit, comprising:

an input terminal for inputting a signal;

the first switch circuit is connected with the acquisition circuit;

2. The integrator circuit of claim 1, wherein the input comprises a first acquisition input and a second acquisition input; the integrator circuit comprises a quantizer, and is connected with the integrating operational amplifier circuit through the second switch circuit;

3. The integrator circuit of claim 1, wherein the input comprises a first acquisition input and a second acquisition input; the acquisition circuit comprises a first acquisition switch, an acquisition capacitor and a second acquisition switch, wherein the first acquisition switch is connected with the first acquisition input end, the second acquisition input end and the acquisition capacitor, and the second acquisition switch is connected with the acquisition capacitor; the controller is connected with the first acquisition switch and the second acquisition switch, and respectively controls the on-off of the first acquisition switch and the second acquisition switch, so that the acquisition capacitor alternately acquires signals input by the first acquisition input end and the second acquisition input end.

4. The integrator circuit of claim 3 wherein the first acquisition switch comprises a first sub-acquisition switch and a second sub-acquisition switch; the second acquisition switch comprises a third sub-acquisition switch and a fourth sub-acquisition switch;

5. The integrator circuit of claim 3 wherein the first acquisition switch comprises a first sub-acquisition switch and a second sub-acquisition switch, the acquisition capacitor comprises a first acquisition capacitor and a second acquisition capacitor; the first sub-acquisition switch is respectively connected between the first acquisition input end and the first acquisition capacitor; the second acquisition input end is connected with the second acquisition capacitor; the second sub-acquisition switch is respectively connected between the second acquisition input end and the first acquisition capacitor; and between the first acquisition input and the second acquisition capacitor; the controller is used for controlling one of the first sub-acquisition switch and the second sub-acquisition switch to be on, and the other sub-acquisition switch to be off; and/or

The integrator circuit includes a reset node; the second acquisition switch comprises a third sub-acquisition switch and a fourth sub-acquisition switch; the third sub-acquisition switch is connected between the first acquisition capacitor and the reset node; and between the second acquisition capacitor and the reset node; the fourth sub-acquisition switch is connected between the first acquisition capacitor and the first input end of the first switching circuit; the second acquisition capacitor is arranged between the second input end of the first switch circuit; the controller is used for controlling one of the third sub-acquisition switch and the fourth sub-acquisition switch to be connected and the other to be disconnected.

6. The integrator circuit of claim 3 further comprising an integrating capacitor connected to the integrating op-amp circuit; the input end comprises a first feedback input end and a second feedback input end; the integrator circuit comprises a feedback circuit connected with the first feedback input end and the second feedback input end, the feedback circuit comprises a first feedback switch, a feedback capacitor and a second feedback switch, the first feedback switch is connected with the first feedback input end, the second feedback input end and the feedback capacitor, the feedback capacitor is connected with the second feedback switch, and the second feedback switch is connected with the integration capacitor; the controller is connected with the first feedback switch and the second feedback switch, and respectively controls the on-off of the first feedback switch and the second feedback switch, so that the feedback capacitor alternately feeds back the feedback signals input by the first feedback input end and the second feedback input end.

7. The integrator circuit of claim 6, wherein the second acquisition switch comprises a third sub-acquisition switch and a fourth sub-acquisition switch; the first feedback switch comprises a first sub feedback switch and a second sub feedback switch;

8. The integrator circuit of claim 6, wherein the first feedback switch comprises a first sub-feedback switch and a second sub-feedback switch, and the feedback capacitance comprises a first feedback capacitance and a second feedback capacitance; the first sub-feedback switch is connected between the first feedback input end and the first feedback capacitor; and is connected between the second feedback input terminal and the second feedback capacitor; the second feedback switch is connected between the second feedback input end and the first feedback capacitor; the first feedback input end and the second feedback capacitor are connected; the controller is used for controlling one of the first sub-feedback switch and the second sub-feedback switch to be on, and the other is off; and/or

The integrating capacitor comprises a first integrating capacitor and a second integrating capacitor; the integrator circuit includes a reset node; the second feedback switch comprises a third sub feedback switch and a fourth sub feedback switch; the third sub-feedback switch is connected between the first feedback capacitor and the first integrating capacitor; and between the second feedback capacitance and the second integration capacitance; the fourth sub-feedback switch is connected between the first feedback capacitor and the second integration capacitor; and between the second feedback capacitance and the first integrating capacitance; the controller is used for controlling one of the third sub-feedback switch and the fourth sub-feedback switch to be on, and the other sub-feedback switch to be off.

9. The integrator circuit of claim 6 wherein the second acquisition switch comprises a third sub-acquisition switch; the second feedback switch comprises a third sub feedback switch and a fourth sub feedback switch; the integrator circuit comprises a quantizer, and is connected with the integrating operational amplifier circuit through the second switch circuit; the quantizer includes a first output and a second output;

the controller controls the on-off of the third sub-feedback switch according to the switch signals or the non-logic of the first output end and the third sub-acquisition switch; or (b)

10. The integrator circuit of claim 1, wherein the integrator circuit comprises a reset node; the integrator circuit further comprises a reset switch connected with the reset node; the reset switch comprises a first reset switch and a second reset switch, the first reset switch and the second reset switch are connected with the controller and the reset node, and the controller is used for controlling the first reset switch and the second reset switch to be disconnected for resetting once when the collection quantity of the collection circuit reaches an upper limit threshold value.