CN219918907U - Independent level conversion circuit and boundary scan board - Google Patents
Independent level conversion circuit and boundary scan board Download PDFInfo
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- CN219918907U CN219918907U CN202321309031.6U CN202321309031U CN219918907U CN 219918907 U CN219918907 U CN 219918907U CN 202321309031 U CN202321309031 U CN 202321309031U CN 219918907 U CN219918907 U CN 219918907U
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Abstract
The utility model discloses an independent level conversion circuit and a boundary scan board, and relates to the technical field of boundary scan boards. The utility model comprises an external control input unit, a digital-to-analog converter, an operational amplifier and a level conversion chip. The utility model has the beneficial effects that: and the high-precision digital-to-analog converter is used for setting the designated level value, so that the precision of the output level is ensured to a greater extent. And the configuration of the register is carried out by combining with the IIC communication protocol, so that the reliability of communication is ensured. The synchronous board card automatically converts the calibration output level, can be suitable for different use scenes, greatly reduces the limitation of the traditional mode at present, and reduces the cost of using hardware.
Description
Technical Field
The present utility model relates to the field of boundary scan panels, and in particular, to an independent level shifter circuit and a boundary scan panel.
Background
The boundary scan board is also called a TAPPort board, and the main function of the boundary scan board is to flexibly control the level of each input/output port of JTAG signals. The client configures the digital-to-analog converter through the external port according to actual requirements, so that each JTAG port can output a desired level value, the level value is used as a power supply end of the level conversion chip, the port inputs an original JTAG signal, and the level conversion chip outputs the desired JTAG level signal. JTAG is an acronym for Joint test action group (JointTestActionGroup) and is a common name in the IEEE Standard 1149.1 entitled Standard test Access Port and boundary Scan architecture. This standard is used to verify the functionality of the printed circuit board produced by the design and test.
The traditional JTAG technical method mostly adopts fixed level, can not flexibly configure the level value of each port, is limited in use, and needs to additionally add a level conversion chip when the level is required to be converted, thereby increasing the hardware cost. The technology can be flexibly configured through the port pins, so that the adaptation of different level occasions is realized, and the hardware cost of different level modes is saved.
Disclosure of Invention
This section is intended to outline some aspects of embodiments of the utility model and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the utility model and in the title of the utility model, which may not be used to limit the scope of the utility model.
The problem to be solved by the utility model is therefore how to adapt directly to different applications of different levels for different customers without adding extra level transitions.
In order to solve the technical problems, the utility model provides the following technical scheme: the independent level conversion circuit comprises an external control input unit, an input/output module, a signal and power input module and an internal boosting module, wherein the internal boosting module boosts a 5V direct current power supply to 6V; the digital-to-analog converter comprises an original input end and a conversion level output end, and the conversion level output end is connected with the signal and power input module; the operational amplifier comprises a conversion level input end and an amplification level output end, wherein the conversion level input end is connected with the conversion level output end; the level conversion chip comprises an amplified level input end, a 3.3V power supply end, an initial level input end and a target level output end, wherein the amplified level input end is connected with the amplified level output end, and the initial level input end is connected with the signal and power supply input module.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: the input/output module pin 10 is connected with a 5V direct current power supply, and a branch circuit is also connected with an LED indicator lamp, and the pin 13 receives a TDO level signal.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: pin 2 of the signal and power input module is connected with a 5V direct current power supply, pin 39/40 of the signal and power input module is connected with a 3.3V direct current power supply, pin 4/6/8 of the signal and power input module is respectively connected with pin SDA/SCL/_RESET of an original input end, pins 19-36 of the signal and power input module output initial JTAG level signals, and pins 1/37/38 of the signal and power input module are grounded.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: the conversion level output terminal is respectively connected with pins In2+/In1+/In4+/In3+ of the conversion level input terminal through pins VOUT6/VOUT7/VOUT12/VOUT 13.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: the amplified level output is connected to pin VCCB of the amplified level input via pin OUT 1.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: the 3.3V power supply end is connected with a 3.3V direct current power supply through a pin VCCA.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: the initial level input terminal is connected with pins 25/26 of the signal and power input module through pins A/DIR, respectively.
As a preferred embodiment of the independent level shift circuit of the present utility model, wherein: the target level output end outputs a target level signal through a pin B, and the level conversion chip is grounded through a pin GND.
The independent level conversion circuit has the beneficial effects that:
the utility model can carry out flexible configuration through the port pins, thereby realizing the adaptation of different level occasions and saving the hardware cost of different level modes.
Another problem to be solved by the utility model is how to automatically calibrate the output level.
In order to solve the technical problems, the utility model provides the following technical scheme: a boundary scan cell comprising the independent level shifter circuit described above; the comparator also comprises a comparison input part and a comparison output part, wherein the comparison input part is connected with the conversion level output end, and the comparison output part is connected with the signal and power supply input module.
As a preferable embodiment of the boundary scan panel according to the present utility model, wherein: the pin IN+ of the comparison input piece receives an initial TDO level signal, the pin IN-of the comparison input piece is connected with VOUT2 of the conversion level output end, the pin V+ of the comparison input piece is connected with a 5V direct current power supply, and the pin V-/SHDN of the comparison input piece is grounded; the pin A of the comparison output part is connected with the pin OUT of the comparison input part, the pin VCC of the comparison output part is connected with a 3.3V direct current power supply, the pin Y of the comparison output part is connected with the pin 10 of the signal and power supply input module, and the pin_OE/A/GND of the comparison output part is grounded.
The boundary scanning plate has the beneficial effects that:
the utility model uses the high-precision digital-to-analog converter to set the appointed level value, and ensures the precision of the output level to a greater extent. And the configuration of the register is carried out by combining with the IIC communication protocol, so that the reliability of communication is ensured. The synchronous board card automatically converts the calibration output level, can be suitable for different use scenes, greatly reduces the limitation of the traditional mode at present, and reduces the cost of using hardware.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a circuit diagram of an input/output module of an independent level shifter circuit according to the present utility model;
FIG. 2 is a circuit diagram of a signal and power input module of an independent level shifter circuit according to the present utility model;
FIG. 3 is a circuit diagram of an internal boost module of an independent level shifter circuit according to the present utility model;
FIG. 4 is a circuit diagram of a digital-to-analog converter of an independent level shift circuit according to the present utility model;
FIG. 5 is a circuit diagram of an operational amplifier of the independent level shifter circuit according to the present utility model;
FIG. 6 is a circuit diagram of a level shifting chip of an independent level shifting circuit according to the present utility model;
FIG. 7 is a circuit diagram of a comparator of a boundary scan panel according to the present utility model;
FIG. 8 is a flow chart of a boundary scan plate according to the present utility model;
FIG. 9 is a graph of the original JTAG signals and target output levels versus data for example 4.
Detailed Description
In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model, but the present utility model may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present utility model is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the utility model. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Example 1
Referring to fig. 1 to 6, an independent level conversion circuit is provided in a first embodiment of the present utility model, and includes an external control input unit 100, including an input/output module 101, a signal and power input module 102, and an internal boost module 103, where the internal boost module 103 boosts a 5V dc power supply to 6V; the digital-to-analog converter 200 comprises an original input end 201 and a conversion level output end 202, wherein the conversion level output end 202 is connected with the signal and power input module 102; an operational amplifier 300 including a transition level input 301 and an amplification level output 302, the transition level input 301 being connected to the transition level output 202; the level conversion chip 400 includes an amplified level input 401, a 3.3V power supply 402, an initial level input 403, and a target level output 404, where the amplified level input 401 is connected to the amplified level output 302, and the initial level input 403 is connected to the signal and power input module 102.
The pin 10 of the input/output module 101 is connected with a 5V direct current power supply, and a branch circuit of the input/output module is also connected with an LED indicator lamp, and the pin 13 of the input/output module receives a TDO level signal.
Pin 2 of signal and power input module 102 is connected to a 5V DC power supply, pins 39/40 are connected to a 3.3V DC power supply, pins 4/6/8 are connected to pins SDA/SCL/_RESET, respectively, of original input terminal 201, pins 19-36 output an initial JTAG level signal, and pins 1/37/38 are grounded.
Transition level output 202 is coupled to pins In2+/In1+/In4+/In1+ of transition level input 301 via pins VOUT6/VOUT7/VOUT12/VOUT13, respectively, to transmit DAC_VOUT6/DAC_VOUT7/DAC_VOUT12/DAC_VOUT13 signals, respectively.
The amplification level output terminal 302 is connected to the pin VCCB of the amplification level input terminal 401 through the pin OUT1, and transmits the amp1_out1 signal.
The 3.3V supply terminal 402 is connected to a 3.3V dc power supply via pin VCCA.
The initial level inputs 403 are connected to pins 25/26 of the signal and power input module 102 via pins A/DIR, respectively, and transmit FPGA_C2_A/FPGA_C2_DIR, respectively.
The target level output terminal 404 outputs a target level signal through the pin B, and the level shift chip 400 is grounded through the pin GND.
The signal and power input module 102 is powered by a 5V power supply and a 3V3 power supply, and the model number of the internal boosting module 103 is TPS55340WQFN.
The model of the digital-analog converter 200 is AD5673RBCPZ-1, and the model of the operational amplifier 300 is TLV9104IDR.
The level shift chip 400 is model SN74LVC1T45DBVR.
Example 2
Referring to fig. 1 to 6, a second embodiment of the present utility model is different from the first embodiment in that: the working flow comprises three steps: firstly, data is acquired through a port, then the original data is processed by the module in the board card, and finally the data is transmitted back through the port.
The working flow is specifically as follows:
in the first step, the port is connected to the external data output terminal, a fixed JTAG level signal value is input, and the digital-to-analog converter 200 is configured by the external port through the IIC communication protocol.
In the second step, after receiving the original data through the IIC communication protocol, the digital-to-analog converter 200 analyzes the data, outputs a specified level signal, outputs the signal to the subsequent operational amplifier 300, amplifies the received signal by 2 times, and transmits the output result to the level conversion chip 400 as a target conversion voltage of the level conversion chip 400. The input end of the level conversion chip inputs JTAG signals to be converted through the port, and JTAG signals with the amplitude of the level can be output through the level conversion chip, and the converted signals are output to the port. And TDO is used as an output signal, so that the TDO signal is output to a comparator, and the output of the comparator is transmitted to a level conversion chip and is converted back to an input end in the design.
And thirdly, finally, the output result of the level conversion chip 400 is transmitted to a port, and the data is returned.
Further preferably, different level usage designs can be implemented, and the output level of each JTAG port is changed according to the requirements, specifically: the digital-to-analog converter 200 is configured to output a desired level value as a power supply voltage of the level conversion chip 400 according to a user's use level, thereby realizing signal conversion of different scene levels.
In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows: an external input/output port is used as a control platform, and a digital-to-analog converter technology, an operational amplifier technology and a level conversion module are combined to construct a variable input/output port output plate. The method comprises the following steps:
first, the digital-to-analog converter module is configured from the external input port module and the JTAG signal of the initial level is input. While configuring the input power. The power input is directly input through an external input pin, is boosted into an internal power supply through a board internal level conversion chip, and is connected with the power module in the board.
And after the digital-to-analog converter 200 is configured, a certain level value is output through an output port of the digital-to-analog converter chip, and the level value is amplified and then is used as a target output power supply end of the level conversion chip. The initial JTAG signal is input to the input pin of the level shift chip 400 through the input port module pin, thereby completing the conversion of the signal from the initial level to the designated level inside the level shift chip.
Finally, the output of the level conversion chip 400 is connected to the user terminal for use.
The digital-to-analog converter and external communication adopt IIC communication protocol, a user can output appointed level voltage through the digital-to-analog converter only by configuring a register set value, and the digital-to-analog converter is a single power input type digital-to-analog conversion device and can receive digital signals and finish the output of corresponding level signals. The level value is output to the target output power supply end of the level conversion chip, wherein the target output power supply end is formed by amplifying twice of the level value to the operational amplifier. The external port outputs JTAG signals of the original level to the input end of the level conversion module, so that the specified level conversion is realized, and the conversion application under different occasions is satisfied.
Example 3
Referring to fig. 7 and 8, a third embodiment of the present utility model, which is different from the first two embodiments, provides a boundary scan cell: the independent level shift circuit including the above embodiments; the comparator 500 further comprises a comparison input part 501 and a comparison output part 502, wherein the comparison input part 501 is connected with the conversion level output end 202, and the comparison output part 502 is connected with the signal and power supply input module 102.
Pin IN+ of comparison input 501 receives the initial TDO level signal, its pin IN-is connected to VOUT2 of transition level output 202, its pin V+ is connected to a 5V DC power supply, and its pins V-/SHDN are grounded; pin A of the comparison output 502 is connected to pin OUT of the comparison input 501, its pin VCC is connected to 3.3V DC power, its pin Y is connected to pin 10 of the signal and power input module 102, and its pin_OE/A/GND is grounded.
Comparator 500 selects model SN74LV1T125DBVR.
When the actual application link is carried out, firstly, correcting the digital-to-analog conversion circuit:
the digital-to-analog converter 200 is configured through an external port, and a parameter value is set to designate a certain channel to output a designated level value. The high and low output values compared by the comparison input unit 501 are supplied to the comparison output unit 502, and a specified level waveform is output.
Then, conversion of the JTAG signal is performed:
the power supply value is set through the external port, and the power supply indicator lamp is turned on. The digital-to-analog converter is configured by an external port to output the desired voltage value. The voltage value is amplified by an operational amplifier and then transmitted to a level conversion chip as a target output level. The IO port inputs an original-level JTAG signal, and the signal is transmitted to an input pin of the level conversion chip and converted into a specified-level JTAG signal through the level conversion chip. And outputting the converted JTAG level signal to the user terminal through a port pin.
The circuit of the comparison input part 501 receives the output level value of the digital-to-analog converter and the initial TDO level signal, the comparison input part 501 generates high and low levels, the comparison output part 502 converts the high and low levels and feeds the converted high and low levels back to the circuit of the input and output port, so that the specified level output is realized, and the reliability of the output is ensured.
Example 4
Referring to fig. 9, a fourth embodiment of the present utility model is shown, which is different from the first three embodiments in that: the following experiments are adopted, all experiments are realized on the basis of a digital-to-analog conversion circuit based on AD5673RBCPZ-1, the digital-to-analog converter is 12 bits, and the relative precision is as follows: + -1 LSB, maximum offset error: maximum gain error of ±1.5 mv: + -0.06% FSR,2.5V reference voltage source temperature coefficient: 2 ppm/. Degree.C.
Meas2 measures the waveform of the initial level signal, and can see that the amplitude is 2.94V, and Meas1 is the output signal after the conversion of the design, and the amplitude is 1.72V level signal. According to the graph, a user can replace the input and output level range according to different use scenes, so that different requirements are met.
It should be noted that the above embodiments are only for illustrating the technical solution of the present utility model and not for limiting the same, and although the present utility model has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present utility model may be modified or substituted without departing from the spirit and scope of the technical solution of the present utility model, which is intended to be covered in the scope of the claims of the present utility model.
Claims (10)
1. An independent level shifter circuit, characterized by: comprising the steps of (a) a step of,
an external control input unit (100) comprising an input/output module (101), a signal and power input module (102) and an internal boost module (103), wherein the internal boost module (103) boosts a 5V direct current power supply to 6V;
the digital-to-analog converter (200) comprises an original input end (201) and a conversion level output end (202), wherein the conversion level output end (202) is connected with the signal and power input module (102);
an operational amplifier (300) comprising a transition level input (301) and an amplification level output (302), the transition level input (301) being connected to the transition level output (202);
the level conversion chip (400) comprises an amplification level input end (401), a 3.3V power supply end (402), an initial level input end (403) and a target level output end (404), wherein the amplification level input end (401) is connected with the amplification level output end (302), and the initial level input end (403) is connected with the signal and power supply input module (102).
2. The independent level shifter circuit of claim 1 wherein: the pin 10 of the input/output module (101) is connected with a 5V direct current power supply, and a branch circuit of the input/output module is also connected with an LED indicator lamp, and the pin 13 of the input/output module receives a TDO level signal.
3. The independent level shifter circuit of claim 2 wherein: pin 2 of the signal and power input module (102) is connected with a 5V direct current power supply, pins 39/40 of the signal and power input module are connected with a 3.3V direct current power supply, pins 4/6/8 of the signal and power input module are respectively connected with pins SDA/SCL/_RESET of an original input end (201), pins 19-36 of the signal and power input module output initial JTAG level signals, and pins 1/37/38 of the signal and power input module are grounded.
4. A stand alone level shifting circuit according to any one of claims 1 to 3, wherein: the transition level output (202) is connected to pins In2+/In1+/In4+/In3+ of the transition level input (301) through pins VOUT6/VOUT7/VOUT12/VOUT13, respectively.
5. The independent level shifter circuit of claim 4 wherein: the amplification level output (302) is connected to pin VCCB of the amplification level input (401) via pin OUT 1.
6. The independent level shifter circuit of claim 5 wherein: the 3.3V power supply end (402) is connected with a 3.3V direct current power supply through a pin VCCA.
7. An independent level shifter circuit according to any one of claims 1 to 3, 5 and 6, wherein: the initial level input (403) is connected to pins 25/26 of the signal and power input module (102) via pins A/DIR, respectively.
8. The independent level shifter circuit of claim 7 wherein: the target level output terminal (404) outputs a target level signal through a pin B, and the level conversion chip (400) is grounded through a pin GND.
9. A boundary scan panel, characterized by: comprising an independent level shifter circuit according to any one of claims 1-3, 5, 6 and 8; also included is a method of manufacturing a semiconductor device,
the comparator (500) comprises a comparison input part (501) and a comparison output part (502), wherein the comparison input part (501) is connected with the conversion level output end (202), and the comparison output part (502) is connected with the signal and power supply input module (102).
10. The boundary scan panel of claim 9, wherein: the pin IN+ of the comparison input piece (501) receives an initial TDO level signal, the pin IN-of the comparison input piece is connected with VOUT2 of the conversion level output end (202), the pin V+ of the comparison input piece is connected with a 5V direct current power supply, and the pin V-/SHDN of the comparison input piece is grounded;
pin A of the comparison output element (502) is connected with pin OUT of the comparison input element (501), pin VCC thereof is connected with a 3.3V direct current power supply, pin Y thereof is connected with pin 10 of the signal and power input module (102), and pin_OE/A/GND thereof is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321309031.6U CN219918907U (en) | 2023-05-26 | 2023-05-26 | Independent level conversion circuit and boundary scan board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321309031.6U CN219918907U (en) | 2023-05-26 | 2023-05-26 | Independent level conversion circuit and boundary scan board |
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