WO2024016519A1

WO2024016519A1 - Combined operational amplifier circuit, chip and signal processing apparatus

Info

Publication number: WO2024016519A1
Application number: PCT/CN2022/130231
Authority: WO
Inventors: 严波; 方超敏; 李建伟; 王悦
Original assignee: 普源精电科技股份有限公司
Priority date: 2022-07-18
Filing date: 2022-11-07
Publication date: 2024-01-25
Also published as: CN115118230A

Abstract

The present application relates to a combined operational amplifier circuit, a chip and a signal processing apparatus. The combined operational amplifier circuit comprises: a first operational amplifier, configured, when an in-phase input terminal and a reverse-phase input terminal of the first operational amplifier have the same electrical properties, to generate a signal to be calibrated; a second operational amplifier, connected to an output terminal of the first operational amplifier; and a calibration circuit, comprising: a judgment branch configured for judging an amplitude and a reference value of the signal to be calibrated generated by the first operational amplifier, and generating a judgment result; and a calibration branch, configured for generating a calibration signal according to the judgment result outputted by the judgment branch, and providing the calibration signal as feedback to the first operational amplifier. Utilizing the technical scheme of the present application allows for improving the precision and bandwidth of the combined operational amplifier circuit.

Description

Combination operational amplifier circuits, chips and signal processing devices

Technical field

The present application relates to the field of integrated circuits, and in particular to a combined operational amplifier circuit, chip and signal processing device.

Background technique

As a basic module of electronic design, operational amplifiers are widely used in different technical fields. For operational amplifiers, there are usually two dimensions of performance requirements: accuracy and speed. Among them, the indicators that characterize the accuracy usually include the offset voltage and temperature drift of the operational amplifier, etc. The indicators that characterize the speed mainly refer to a series of bandwidth indicators of the operational amplifier, such as -3dB bandwidth and full power bandwidth. Currently, for conventional operational amplifiers, there is a trade-off between accuracy and speed. That is to say, generally speaking, the bandwidth of operational amplifiers with higher precision (hereinafter referred to as "precision operational amplifiers") is relatively small, while the accuracy of operational amplifiers with larger bandwidths (hereinafter referred to as "wideband operational amplifiers") are relatively low. Among them, precision operational amplifiers generally refer to operational amplifiers whose offset voltage is lower than 1mV and at the same time, the offset voltage drift value with temperature changes is less than 100V; broadband operational amplifiers generally refer to the ratio of the upper limit operating frequency to the lower limit operating frequency is greater than 1 For operational amplifiers, it is customary to include amplifiers with a relative frequency bandwidth (B/Fs) greater than 20% to 30% in this category. In the field of oscilloscopes, the bandwidth of broadband operational amplifiers generally ranges from DC to more than ten GHz or even higher.

In order to solve this trade-off between the accuracy and speed of operational amplifiers, a combined operational amplifier circuit in which two operational amplifiers are connected in series is usually used in the prior art. Generally speaking, one operational amplifier is a precision operational amplifier, and the other operational amplifier is a precision operational amplifier. A wideband operational amplifier connected in series after a precision operational amplifier. When the frequency of the input signal is low, the input signal will be adjusted by the precision operational amplifier before entering the wideband operational amplifier. This can make the performance of the entire combined operational amplifier circuit in the DC and low frequency bands mainly determined by the performance of the precision operational amplifier. . When the frequency of the input signal is higher and larger than the bandwidth of the precision operational amplifier, the precision operational amplifier is responsible for providing a DC bias level to the wideband operational amplifier and directly inputting the signal to the wideband operational amplifier through the VIN input terminal, which ensures that the combined operation Overall high frequency performance of the amplifier circuit.

However, the above-mentioned combined operational amplifier circuit still has certain limitations, that is, the offset voltage of the precision operational amplifier has not been calibrated, which cannot meet the requirements of application scenarios with high precision requirements. For example, the combined operational amplifier circuit cannot meet the requirements of high-precision applications. Precision oscilloscope analog front-end requirements.

In order to solve this problem, as shown in Figure 1, the following two technical solutions are usually applied in the existing technology:

(1) Use dynamic elimination techniques such as automatic zero calibration to calibrate the combined operational amplifier circuit, but this requires additional clock input and will introduce spurs, which are not allowed in some application scenarios that require higher accuracy.

(2) Perform front-end calibration of the combined operational amplifier circuit, that is, use laser to calibrate the chip integrated with the combined operational amplifier circuit before leaving the factory. However, this requires the use of analog test equipment (such as multimeters and analog-to-digital converters, etc.) to calibrate it, and the calibration time is long; also because the chip is calibrated before leaving the factory, it is difficult to estimate the actual application scenarios of the chip in the later stage. The errors produced in the calibration results in inaccurate calibration results.

Contents of the invention

In view of this, embodiments of the present application provide a combined operational amplifier circuit, chip and signal processing device to solve at least one problem existing in the background art.

In the first aspect, embodiments of the present application provide a combined operational amplifier circuit, including:

a first operational amplifier configured to generate a signal to be calibrated if the non-inverting input terminal and the inverting input terminal of the first operational amplifier have the same electrical characteristics;

A second operational amplifier is connected to the output end of the first operational amplifier, and the bandwidth of the second signal output by the second operational amplifier is greater than the bandwidth of the first signal output by the first operational amplifier, wherein, The first signal includes the signal to be calibrated;

Calibration circuit, which includes:

- a discrimination branch configured to discriminate between the amplitude of the signal to be calibrated generated by the first operational amplifier and a reference value and to generate a discrimination result;

- a calibration branch configured to generate a calibration signal based on the discrimination result output by the discrimination branch and to feed the calibration signal back to the first operational amplifier.

Combined with the first aspect of the present application, in an optional implementation, the discrimination branch includes:

a signal converter configured to convert the signal to be calibrated into a level signal;

A first comparator configured to distinguish the logic value of the level signal from the reference value and generate a discrimination result.

In conjunction with the first aspect of the present application, in an optional implementation, if the signal to be calibrated includes a voltage signal, the discrimination branch includes:

An inverter, the input end and the output end of which are respectively connected to the output end of the first operational amplifier and the input end of the calibration branch;

The input end and the output end of the first digital buffer are respectively connected to the output end of the first operational amplifier and the input end of the calibration branch; or,

a level shifter and a second digital buffer, wherein the input end and the output end of the level shifter are respectively connected to the output end of the first operational amplifier and the input end of the second digital buffer, so The output terminal of the second digital buffer is connected to the input terminal of the calibration branch.

In conjunction with the first aspect of the present application, in an optional implementation, the discrimination branch further includes a reference signal generator and a second comparator, wherein,

The reference signal generator is configured to provide a reference signal having an amplitude of the reference value to the second comparator;

The second comparator is configured to distinguish the amplitude of the signal to be calibrated from the amplitude of the reference signal and generate a discrimination result.

In conjunction with the first aspect of the present application, in an optional implementation, the calibration branch includes a control unit and a calibration unit, wherein,

The control unit is configured to generate a control instruction for controlling the calibration unit according to the discrimination result received from the discrimination branch;

The calibration unit is configured to generate the calibration signal for calibrating the electrical characteristics of the first operational amplifier according to the control instruction sent by the control unit and send the generated calibration signal to the third operational amplifier. One operational amplifier input channel.

In conjunction with the first aspect of the present application, in an optional implementation, the control unit is specifically configured to perform the following operations:

After receiving the discrimination result, determine whether the discrimination result is received for the first time;

If so, use a preset algorithm corresponding to the output characteristics of the calibration unit to generate a control instruction corresponding to the discrimination result, and send the control instruction to the calibration unit;

If not, it is determined whether the discrimination result received this time is the same as the discrimination result received last time. If they are the same, a preset algorithm corresponding to the output characteristics of the calibration unit is used to generate an algorithm corresponding to the discrimination result. and send the control instruction to the calibration unit. If they are different, directly send the control instruction corresponding to the last received discrimination result to the calibration unit.

In conjunction with the first aspect of the present application, in an optional implementation, the control unit includes a micro control unit chip or a host computer.

In conjunction with the first aspect of the present application, in an optional implementation, the calibration unit includes a digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input channel of the first operational amplifier.

In conjunction with the first aspect of the present application, in an optional implementation, the input channel of the first operational amplifier includes the non-inverting input terminal and the inverting input terminal, or includes a differential signal inside the first operational amplifier. Signal transmission node.

Combined with the first aspect of this application, in an optional implementation, it also includes:

A switching unit configured to connect the non-inverting input terminal and the inverting input terminal of the first operational amplifier to ground or to a voltage source providing a common mode voltage.

In conjunction with the first aspect of the present application, in an optional implementation, the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, and the inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier. The inverting input terminal is connected.

In a second aspect, embodiments of the present application provide a chip including the combined operational amplifier circuit as described in any one of the above first aspects.

In a third aspect, embodiments of the present application provide a signal processing device, including the combined operational amplifier circuit as described in any one of the above first or second aspects.

By utilizing a combined operational amplifier circuit, chip, and signal processing device provided by embodiments of the present application, offset calibration of the combined operational amplifier circuit can be achieved without the need for laser trimming and additional clocks, and without introducing spurs. It can avoid errors caused by differences in operational amplifier circuit application scenarios faced by traditional front-end calibration of operational amplifier offsets. At the same time, the calibration circuit does not interfere with the main signal path of the combined operational amplifier circuit, which improves the DC performance of the combined operational amplifier circuit.

In addition, the embodiment of the present application performs offset calibration on the first operational amplifier by using a calibration circuit, which can improve the accuracy of the combined operational amplifier circuit, and by setting the output terminal of the first operational amplifier, the output bandwidth can be larger than the output of the first operational amplifier. The bandwidth of the first signal is the second operational amplifier of the second signal, which can increase the bandwidth of the combined operational amplifier circuit, thereby allowing the combined operational amplifier circuit to be used in application scenarios that require both accuracy and bandwidth.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a schematic diagram of a combined operational amplifier circuit in the prior art;

Figure 2 is a circuit schematic diagram of a combined operational amplifier circuit provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of a discrimination branch provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of another discrimination branch provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of another discrimination branch provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of yet another discrimination branch provided by an embodiment of the present application;

Figure 7 is a schematic structural diagram of another discrimination branch provided by an embodiment of the present application;

Figure 8 is a schematic structural diagram of the calibration branch provided by the embodiment of the present application;

Figure 9 is a circuit schematic diagram of another combined operational amplifier circuit provided by an embodiment of the present application;

FIG. 10 is a circuit schematic diagram of another combined operational amplifier circuit provided by an embodiment of the present application.

Detailed ways

In order to make the technical solutions and beneficial effects of the present application more obvious and easy to understand, detailed descriptions are given below by enumerating specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of local features; unless otherwise defined, the technical and scientific terms used herein are not consistent with the technical field to which this application belongs. Technical and scientific terms in have the same meaning.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a," "an," and "the" may also be intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the term "comprising" is used in this specification, the presence of stated features, integers, steps, operations, elements and/or components is identified but does not exclude the presence of one or more other features, integers, steps, The presence or addition of operations, components, parts, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items, and the term "plurality" includes two or more.

It will be understood that when a structure is referred to as being "connected" to other structures, it can be directly connected to the other structures or intervening structures may be present. In contrast, when a structure is said to be "directly connected" to another structure, there are no intervening structures present. It should be understood that although the terms first, second, third, etc. are used to describe various elements, components, and/or sections, these elements, components, and/or sections should not be limited by these terms, which are only used to distinguish One of them versus the other. Thus, a first element, component, or section discussed below could be termed a second element, component, or section, and when a second element, component, or section is discussed, and There is no indication that the first element, component, or part of the present application necessarily exists.

As shown in Figure 2, this embodiment of the present application provides a combined operational amplifier circuit, including:

A first operational amplifier 100 configured to generate a signal to be calibrated when the non-inverting input terminal and the inverting input terminal of the signal to be calibrated of the first operational amplifier 100 have the same electrical characteristics;

A second operational amplifier 200 is connected to the output end of the first operational amplifier 100 , and the bandwidth of the second signal output by the second operational amplifier 200 is greater than the bandwidth of the first signal output by the first operational amplifier 100 , wherein the first signal may include the signal to be calibrated;

Calibration circuit 300, which includes:

-The discrimination branch 310 is configured to discriminate the amplitude of the signal to be calibrated generated by the first operational amplifier and the reference value and generate a discrimination result;

- Calibration branch 320, which is configured to generate a calibration signal according to the discrimination result output by the discrimination branch and feed back the calibration signal to the first operational amplifier 100.

The calibration process of this combined operational amplifier circuit is as follows:

When the two input terminals of the first operational amplifier 100 are set to have the same electrical characteristics (ie, the same voltage or current, etc.), the first operational amplifier 100 generates a signal to be calibrated and sends it to the discrimination branch in the calibration circuit 300 path 310; the discrimination branch 310 distinguishes the amplitude (voltage or current, etc.) of the received signal to be calibrated from the reference value and generates the corresponding discrimination result; the calibration branch 320 generates a calibration signal according to the discrimination result output by the discrimination branch 310 , and the generated calibration signal is fed back to the first operational amplifier 100 to compensate the electrical characteristic offset of the first operational amplifier 100, thereby realizing the electrical characteristic offset calibration of the first operational amplifier 100.

Obviously, the embodiment of the present application mainly uses the calibration circuit provided in the combined operational amplifier circuit to calibrate the first operational amplifier, without the need for laser trimming and additional clocks, nor the introduction of spurious, and can also avoid the traditional front-end calibration operation. Amplifier offset is an error caused by differences in application scenarios of operational amplifier circuits. At the same time, the calibration circuit does not interfere with the main signal path of the combined operational amplifier circuit, which improves the DC performance of the combined operational amplifier circuit.

In addition, the embodiment of the present application performs offset calibration on the first operational amplifier by using a calibration circuit, which can improve the accuracy of the combined operational amplifier circuit, and by setting the output terminal of the first operational amplifier, the output bandwidth can be larger than the output of the first operational amplifier. The bandwidth of the first signal is the second operational amplifier of the second signal, which can increase the bandwidth of the combined operational amplifier circuit, thereby allowing the combined operational amplifier circuit to be used in application scenarios that require both accuracy and bandwidth (for example, oscilloscope front-end).

In at least one embodiment, the first operational amplifier 100 may be a first-stage operational amplifier among the multi-stage operational amplifiers included in the combined operational amplifier circuit, or may be an intermediate-stage operational amplifier; the second operational amplifier 200 may be combined with the third-stage operational amplifier. An operational amplifier 100 is connected in series, and it can be an intermediate operational amplifier in the multi-stage operational amplifier, or it can also be the last operational amplifier.

When the first operational amplifier 100 and the second operational amplifier 200 are the first-stage operational amplifier and the last-stage operational amplifier respectively, the two input terminals (ie, the non-inverting input terminal and the inverting input terminal) of the first operational amplifier 100 can As the input terminal of the combined operational amplifier circuit to receive external signals, the output terminal of the second operational amplifier 200 can be used as the output terminal of the combined operational amplifier circuit to output signals to the outside.

The first operational amplifier 100 and the second operational amplifier 200 may be devices that amplify differential signals according to a certain fixed gain, and they may be precision operational amplifiers and broadband operational amplifiers respectively, but are not limited thereto. For descriptions of precision operational amplifiers and broadband operational amplifiers, reference may be made to relevant descriptions in the prior art and will not be repeated here.

Moreover, the non-inverting input terminal of the second operational amplifier 200 may be connected to the output terminal of the first operational amplifier 100, and its inverting input terminal and the inverting input terminal of the first operational amplifier 100 may be connected in parallel to an external signal input terminal (for example, the combination The input terminal of the operational amplifier circuit or the output terminal of the upper-stage operational amplifier), which can improve the versatility of the interface of the combined operational amplifier circuit.

It should be noted that when the first operational amplifier 200 is calibrated, its two input terminals can be set to have the same electrical characteristics by floating, grounding, or connecting to a common-mode voltage. Moreover, when the first operational amplifier 200 is calibrated, since no signal is provided to the other input terminal of the second operational amplifier 200, it does not output any signal.

In at least one embodiment, as shown in Figure 3, the determination branch 310 may include:

Signal converter 311, which may be configured to convert the signal to be calibrated into a level signal;

The first comparator 312 may be configured to distinguish the logic value of the level signal from the reference value and generate a discrimination result.

The signal to be calibrated can be a voltage signal, a current signal, or other electrical signals. If the signal to be calibrated is a current signal, the signal converter 311 can convert it directly, or it can also convert it into a voltage signal through a resistor and then convert it.

The reference value can be a default level (0 or 1) preset in the signal converter 311, or it can be a voltage provided to the signal converter 311 using an external device (for example, a reference signal generator, as shown in Figure 7). The specific value can be set according to actual needs or application scenarios.

Signal converter 311 may include any circuit or device for converting analog signals to digital signals, such as an analog-to-digital converter (ADC).

The first comparator 312 may be any circuit or device capable of data comparison. For example, the first comparator 312 can be a voltage comparator or a current comparator, and its specific type can be determined according to the type of the received signal. For example, when the signal to be calibrated is a voltage signal, it can be a voltage comparator, and when the signal to be calibrated is a current signal, it can be a current comparator.

The signal converter 311 and the first comparator 312 can be set independently or integrated in the same module.

In this embodiment, the operation process of the discrimination branch 310 is as follows:

After the first operational amplifier 100 outputs the signal to be calibrated, the signal converter 311 in the discrimination branch 310 can convert the signal to be calibrated output by the first operational amplifier 100 into a level signal, and send the converted level signal to The first comparator 312. After receiving the level signal sent by the signal converter 311, the first comparator 312 determines whether the logic value of the level signal is the same as the reference value and generates a judgment result. The judgment result indicates the level signal. The relationship between the logical value and the base value. For example, when the logic value of the level signal is the same as the reference value, the discrimination result may be 1, and when the logic value of the level signal is different from the reference value, the discrimination result may be 0.

In at least one embodiment, as shown in FIG. 4 , when the signal to be calibrated output by the first operational amplifier 100 is a voltage signal, the discrimination branch 310 may include an inverter 315 , the input end and the output end of which are connected to the first operational amplifier 100 respectively. The output terminal of the operational amplifier 100 is connected to the input terminal of the calibration branch 320, and the inverter 315 can understand the functions of a 1-bit analog-to-digital converter and a comparator.

In at least one embodiment, as shown in Figure 5, when the signal to be calibrated output by the first operational amplifier 100 is a voltage signal, the discrimination branch 310 may also include a first digital buffer 316, the input end and the output end of which are respectively It is connected to the output terminal of the first operational amplifier 100 and the input terminal of the calibration branch 320, and it can usually be implemented by a logic gate circuit.

In at least one embodiment, as shown in FIG. 6 , when the signal to be calibrated output by the first operational amplifier 100 is a voltage signal, the discrimination branch 310 may further include a voltage shifter 317 and a second digital buffer 318 . The input terminal and the output terminal of the voltage shifter 317 can be connected to the output terminal of the first operational amplifier 100 and the input terminal of the second digital buffer 318 respectively, and are mainly used for calibrating the signal output by the first operational amplifier 100. The voltage is shifted to match the voltage range that the second digital buffer 318 can receive, that is, the signal to be calibrated generated by the first operational amplifier 100 can cover the power rail of the second digital buffer 318 . For example, the voltage range output by the first operational amplifier 100 is 1-3V, and the voltage range that the second digital buffer 318 can receive is 2-4V, then the voltage output by the first operational amplifier 100 can be converted to The range is shifted from 1~3V to 2~4V. The voltage shifter 317 can be implemented by a field effect transistor or a logic gate circuit. The output of the second digital buffer 318 may be connected to the input of the calibration branch 320 , which may be the same as or different from the first digital buffer 316 .

The inverter 315, the first digital buffer 316, and the second digital buffer 318 in the above embodiment can all perform the functions of the signal converter 311 and the first comparator 312 shown in FIG. 3 .

For detailed descriptions of the inverter, digital buffer, and voltage shifter, reference may be made to the corresponding descriptions in the prior art and will not be repeated here.

The structure of the discrimination branch can be simplified by arranging the discrimination branch to have the structure of an inverter or a digital buffer.

In at least one embodiment, as shown in FIG. 7 , the discrimination branch 310 may include: a reference signal generator 313 and a second comparator 314 , wherein the reference signal generator 313 may be configured to provide a signal to the second comparator 314 A reference signal whose amplitude is a reference value is provided, and the second comparator 314 may be configured to distinguish the amplitude of the signal to be calibrated from the amplitude of the reference signal and generate a discrimination result.

The reference signal can be a level signal or a periodic signal with a fixed amplitude (for example, a square wave signal), and its type is consistent with the type of the signal to be calibrated.

One input terminal of the second comparator 314 is connected to the output terminal of the first operational amplifier 100 , the other input terminal is connected to the reference signal generator 313 , and its output terminal is connected to the input terminal of the calibration branch 320 . The second comparator 314 may be configured to convert the signal to be calibrated into a level signal and compare the converted level signal with the reference signal. In this case, the reference signal generator 313 may be configured to provide the level signal as the reference signal to the second comparator 314 . In this case, the second comparator 314 can be understood as an integrated module that implements the functions of the signal converter 311 and the first comparator 312 . The second comparator 314 may also be configured to directly compare the amplitude of the signal to be calibrated with the amplitude of the reference signal. In this case, the reference signal generator 313 may be configured to provide the second comparator 314 with the periodic signal as the reference signal.

By configuring the discrimination circuit to include a reference signal generator and a second comparator, its structural complexity can be simplified, and the calibration speed can be accelerated. For example, the first operational amplifier 100 is a precision operational amplifier with an output voltage range of -2V to 2V, but its slew rate is very low and the conversion speed is not fast enough. Then a 1V level signal is generated through the reference signal generator. It can reduce the level ramp time by more than half, thereby speeding up calibration.

In at least one embodiment, as shown in FIG. 8 , the calibration branch 320 may include a control unit 321 and a calibration unit 322 , wherein the control unit 321 may be configured to generate a Controlling the control instructions of the calibration unit 322 , the calibration unit 322 may be configured to generate a calibration signal for calibrating the electrical characteristics of the first operational amplifier 100 according to the control instructions of the control unit 321 and send the generated calibration signal to the first operational amplifier 100 . Input channel of operational amplifier 100. specifically:

The control unit 321 may be configured to perform the following operations:

After receiving the discrimination result of the discrimination branch 310, it is determined whether the discrimination result is received for the first time; if so, a preset algorithm corresponding to the output characteristics of the calibration unit 322 is used to generate a control instruction corresponding to the discrimination result, and the generated The control instruction is sent to the calibration unit 322 to control the calibration unit 322 to generate the corresponding calibration signal; if not, determine whether the discrimination result received this time is the same as the discrimination result received last time, and if it is the same, use the calibration unit 322 The preset algorithm corresponding to the output characteristics generates a control instruction corresponding to the discrimination result, and sends the generated control instruction to the calibration unit 322 to control the calibration unit 322 to generate the corresponding calibration signal. If it is different, the control instruction will be directly compared with the last received one. The control instructions corresponding to the judgment results are sent to the calibration unit 322.

Regarding the specific manner in which the control unit 321 uses a preset algorithm corresponding to the output characteristics of the calibration unit 322 to generate a control instruction corresponding to the judgment result, an example is as follows:

For example, if the output characteristic of the calibration unit 322 is a monotonic linear output, the control unit 321 may be configured to use an algorithm such as the traversal method or the dichotomy method to search for a control code corresponding to the discrimination result in the pre-stored control code set, and use the found control code to The codes are sent to the calibration unit 322 as control instructions.

In the case where the calibration unit 322 has a monotonic linear output and the number of control code sets pre-stored in the control unit 321 is small, the control unit 321 can use the traversal method to find the control code, that is, the logical value of the judgment result is "1" or "0" to determine whether to search the control code upward or downward in the pre-stored control code set, and then search the control codes one by one in the pre-stored control code set according to the determined search direction until the best control code is determined. For example, if the judgment result is a logical value "1", it means searching upward for the control code; if the judgment result is a logical value "0", it means searching downward for the control code. This search method is applicable to the case where the calibration unit 322 is a digital-to-analog converter (DAC) with fewer bits.

In the case where the calibration unit 322 has a monotonic output and the control unit 321 has a large number of pre-stored control code sets, the control unit 321 can use the dichotomy method to find the control code, that is, the logical value of the judgment result is "1" or "0" determines whether to search for control codes upward or downward in the pre-stored control code set, and then searches for control codes in the pre-stored control code set according to the determined search direction and at preset intervals until the best control code is determined. This search method can be applied to the case where the calibration unit 322 is a DAC with a large number of bits.

The detailed process of calibrating the first operational amplifier 100 will now be described by taking the example that the calibration unit 322 includes a 3-bit DAC and its output characteristic is a monotonic linear output and uses the binary method to search for the control code.

The logic value of the level signal output by the first operational amplifier 100 is 0, and the target to be calibrated is to change the logic value of the level signal from “0” to “1”. The determination branch 310 converts the signal to be calibrated output by the first operational amplifier 100 to obtain a level signal, determines whether the logic value of the level signal is the same as the reference value (assuming its value is "1"), and generates a determination The result is "0". If the control unit 321 configures the control code to the intermediate codeword 3 in advance, when receiving the discrimination result "0" from the discrimination branch 310, this means that the control code "3" is too small, and the search can continue upward to find the codeword. Codeword 5 between 3 and codeword 7 is sent to the calibration unit 322 as a control instruction, and the calibration unit 322 generates a corresponding calibration signal. After that, the first operational amplifier 100 outputs a new signal to be calibrated in response to the received calibration signal, and the discriminating branch 310 converts the new signal to be calibrated and compares the logical value of the converted level signal with the reference value " 1" for comparison, if the judgment result "0" is still output, this still means that the previously found control code "5" is still too small, then the control unit 321 continues to search upward again, and finds between codeword 5 and codeword 7 The codeword 6 is output to the calibration unit 322 as a control instruction. After that, the judgment branch 310 compares the logic value of the updated level signal with the reference value "1". If the judgment result output by it changes from "0" to "1", this means that the control code "6" is If the control code is optimal, the control unit 321 directly sends the control code to the calibration unit 322 as a control instruction, and then keeps outputting the control code to the calibration unit 322.

For another example, if the output characteristic of the calibration unit 322 is a non-monotonic output, the control unit 321 may be configured to perform mapping processing on each control code in the pre-stored control code set to obtain a new control code set, and use the traversal method or the dichotomy method, etc. The algorithm searches for the control code corresponding to the discrimination result in the new control code set, and sends the found control code to the calibration unit 322 as a control instruction.

In a specific implementation, the calibration unit 322 may be a multi-bit analog-to-analog converter (DAC) whose output is a sawtooth wave with rollback characteristics. At this time, the control unit 321 may perform calibration based on the characteristics of the sawtooth wave output by the calibration unit 322 . Each control code in the pre-stored control code set is mapped to obtain a new control code set, and then the control code corresponding to the discrimination result is searched in the new control code set.

Taking the calibration unit 322 as a 5-bit DAC and outputting a sawtooth wave as an example to illustrate the process of the control unit 321 searching for the control code.

As shown in Table 1, it is the input and output table of the DAC. As can be seen from Table 1, the codeword input by the DAC is monotonically related to the voltage output by the DAC, but cannot be monotonically related to the voltage output by the DAC sawtooth waveform. Therefore, the codeword input by the DAC cannot be directly used for binary search. Based on this, it is necessary to first map the DAC codewords according to the output characteristics of the DAC sawtooth wave. For example, map the original codeword 6 to a new codeword 4, and discard the original codeword 4 and codeword 5, etc., so as to Make the mapped code words monotonous to facilitate search.

Table 1 DAC input and output table

DAC输入的码字DAC input code word	DAC单调输出(V)DAC monotonic output (V)	DAC锯齿波输出(V)DAC sawtooth wave output (V)
00	00	00
11	11	11
22	22	22
33	33	33
44	44	22
55	55	33
66	66	44
77	77	55
88	88	44
99	99	55
1717	1717	66
1818	1818	77
………	………	………
3131	3131	xxxx

Although the above description is that the control unit 321 generates the control instruction by searching, in fact, the control unit 321 may also be configured to directly generate the control instruction based on the determination result. For example, the control unit 321 can directly generate a control code corresponding to the discrimination result, send the control code to the calibration unit 322 as a control instruction, and store the control code for subsequent use. In addition, the control instruction is not limited to the form of the above control code, and may also be in other encoding forms, as long as the corresponding relationship between the control instruction of the control unit 321 and the output signal of the calibration unit 322 is set in advance.

Control unit 321 may include any suitable circuitry and/or device for generating digital signals. For example, the control unit 321 may take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (eg, software or firmware) executable by the (micro)processor, logic gates, switches, application specific integrated The control unit 321 may also include various logic circuits that perform functions such as search, comparison, signal conversion, and various arithmetic functions. In addition, the control unit 321 may include a micro control unit (MCU) chip and/or a host computer (for example, a PC with host computer software installed), etc., wherein when the control unit 321 is an MCU chip, it may be integrated in the combination. In an operational amplifier circuit, this can increase the calibration speed, and when the control unit 321 is a PC, it can be set up separately from various components in the combined operational amplifier circuit, which makes the combined operational amplifier circuit easy to implement. In addition, the control unit 321 may also include a memory (not shown), which may be configured to store the control code, the discrimination result transmitted by the discrimination branch, and the like.

By configuring the control unit as described above, precise control of the calibration unit can be achieved based on the discrimination results output by the discrimination branch, thereby ensuring the accuracy of the calibration results and improving the calibration speed.

The calibration unit 322 may be configured to, after receiving the control instruction from the control unit 321, generate a calibration signal corresponding to the control instruction according to a preset correspondence between the control instruction output by the control unit 321 and the output signal of the calibration unit 322, The calibration signal is sent to the first operational amplifier 100 for electrical characteristic offset calibration. The electrical characteristics may include voltage or current, but are not limited thereto.

The corresponding relationship between the control instruction and the output signal can be understood as the corresponding relationship between the digital signal and the analog signal, and the corresponding relationship can be set in advance according to the structure or function of the calibration unit 322 . For example, the control instruction output by the control unit 321 is a control code, and the calibration unit 322 is a 2-bit DAC that outputs a current signal of 0 to 3 mA. Then the control signal output by the control unit 321 and the output signal of the calibration unit 322 exist as shown in Table 2 below. The corresponding relationship shown:

Table 2 Correspondence between control instructions and output signals

控制指令Control instruction	输出信号output signal
00	0mA0mA
11	1mA1mA
22	2mA2mA
33	3mA3mA

Calibration unit 322 may include any suitable circuitry and/or devices that generate analog signals. For example, the calibration unit 322 may include a digital-to-analog converter (DAC) for converting a digital signal (eg, a control code sent by the control unit 321) into an analog signal (eg, a voltage signal or a current signal), and may further include a The voltage signal is reversely superimposed on the inverter or the like on the input channel of the first operational amplifier 100 . The input channel may include the input end of the first operational amplifier 100 (as shown in FIG. 9 ) or its internal differential signal transmission node (as shown in FIG. 10 ), etc.

In addition, the calibration unit 322 may include two output terminals, and the two output terminals may be respectively connected to the two input terminals of the first operational amplifier 100 or the differential signal transmission node inside the first operational amplifier 100, as shown in FIGS. 9-10 Show. Generally speaking, if the calibration signal is a voltage signal, the output terminal of the calibration unit 322 is connected to the input terminal of the first operational amplifier 100; if the calibration signal is a current signal, the output terminal of the calibration unit 322 is connected to the input terminal of the first operational amplifier 100. The input terminal or its internal differential signal transmission node can be connected. Regarding the description of the differential signal transmission node, reference may be made to the relevant descriptions in the prior art, which will not be described again here.

By configuring the calibration unit as above, the electrical characteristic offset calibration of the first operational amplifier can be achieved, thereby improving the accuracy of the combined operational amplifier circuit.

In at least one embodiment, as shown in Figures 2, 9 and 10, in addition to the configuration described in the above embodiments, the combined operational amplifier circuit provided by the embodiment of the present application may also include:

The switch unit 400 is connected to both the non-inverting input terminal and the inverting input terminal of the first operational amplifier 100 and is configured to ground the non-inverting input terminal and the inverting input terminal of the first operational amplifier 100 or connect it to a power supply. Voltage source for common mode voltage.

The switch unit 400 may be disposed on a path where the two input terminals, the non-inverting input terminal and the inverting input terminal of the first operational amplifier 100 are located. When the first operational amplifier needs to be calibrated, the switch unit 400 can be controlled so that the two input terminals of the first operational amplifier 100 are connected to ground (as shown in FIG. 9 ) or connected to a voltage source VCMO that provides a common mode voltage (as shown in FIG. 10 shown), this can make the two input terminals of the first operational amplifier 100 have the same electrical characteristics; if there is no need to calibrate the first operational amplifier, the switch unit 400 can be controlled so that the two input terminals of the first operational amplifier 100 They are respectively connected to two external signal input terminals (for example, the two input terminals of the combined operational amplifier circuit or the two input terminals of the upper stage operational amplifier, etc.).

In addition, the switch unit 400 may be connected to the control unit 321 or other control devices to control the on/off between the first operational amplifier 100 and the external signal input terminal under the control of the control unit 321 or other control devices. Of course, the switch unit 400 can also be controlled manually.

Optionally, the switch unit 400 may include common switches that control circuit on and off, and may also include switching devices such as field effect transistors or transistors, and any of the existing technologies may be used to turn on and off these switching devices. species, so they will not be described in detail here.

For example, the switch unit 400 may include a first single-pole double-throw switch K1 and a second single-pole double-throw switch K2. The fixed terminals of the first SPDT switch K1 and the second SPDT switch K2 are respectively connected to the non-inverting input terminal and the inverting input terminal of the first operational amplifier 100. The first SPDT switch K1 and the second SPDT switch The first active terminals of K2 are respectively connected to corresponding external signal input terminals, and the second active terminals of the first single-pole double-throw switch K1 and the second single-pole double-throw switch K2 are connected in parallel to ground or to a voltage source VCMO that provides a common mode voltage.

By controlling the switch unit 400 to ground the first operational amplifier 100, the operation and connection are relatively simple, and the input of the first operational amplifier 100 can also be ensured to be safe.

In at least one embodiment, the combined operational amplifier circuit may take the form of a system-on-chip. In other words, the components in all branches of the combined operational amplifier circuit are integrated into the chip, which allows the input switching of the combined operational amplifier circuit to occur inside the chip and has nothing to do with the external environment, which can avoid traditional front-end calibration. The calibration error caused by the change of usage scenarios faced by the operational amplifier offset solves the problem of calibration errors caused by the inability of the front-end calibration offset to take into account the usage scenarios, and improves the accuracy of calibration.

At the same time, in terms of calibration on the combined operational amplifier circuit in the form of a system-on-chip, its calibration speed block can automatically iterate feedback calibration, which solves the disadvantage of long front-end calibration time and makes the structure simpler.

Verificationally, by using the combined operational amplifier circuit provided by the embodiment of the present application, the bandwidth of the output signal can be made to reach the level of GHz to tens of GHz, and the offset voltage of the uV to tens of nV level can be calibrated.

In at least one embodiment, the components in all branches of the combined operational amplifier circuit can also be discrete devices, which can make the bandwidth of the output signal reach hundreds of MHz and calibrate the offset voltage of tens of uV.

Regarding the technical means of manufacturing an operational amplifier circuit by using an on-chip system or discrete devices, reference can be made to the corresponding descriptions in the prior art and will not be described again here.

Based on the same inventive concept, embodiments of the present application also provide a chip, which may include the combined operational amplifier circuit of any of the above embodiments, and may also include an analog-to-digital converter connected to the output end of the combined operational amplifier circuit. (ADC).

Based on the same inventive concept, an embodiment of the present application also provides a signal processing device, including the combined operational amplifier circuit or the above-mentioned chip of any of the above embodiments. The signal processing device may include but is not limited to an oscilloscope, a display, or a radio frequency system.

Each embodiment in this specification is described in a progressive manner. The same and similar parts between the various embodiments can be referred to each other. Each embodiment focuses on its differences from other embodiments.

It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, various technical features of the above embodiments may also be combined arbitrarily to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementation modes of the present application and do not limit the scope of protection of the patent of the present application.

Claims

A combined operational amplifier circuit, characterized by including:

a first operational amplifier configured to generate a signal to be calibrated if the non-inverting input terminal and the inverting input terminal of the first operational amplifier have the same electrical characteristics;

a second operational amplifier connected to the output end of the first operational amplifier;

Calibration circuit, which includes:

- a discrimination branch configured to discriminate between the amplitude of the signal to be calibrated generated by the first operational amplifier and a reference value and to generate a discrimination result;

- a calibration branch configured to generate a calibration signal based on the discrimination result output by the discrimination branch and to feed the calibration signal back to the first operational amplifier.
The combined operational amplifier circuit of claim 1, wherein the discriminating branch includes:

a signal converter configured to convert the signal to be calibrated into a level signal;

A first comparator configured to distinguish the logic value of the level signal from the reference value and generate a discrimination result.
The combined operational amplifier circuit of claim 1, wherein if the signal to be calibrated includes a voltage signal, the discriminating branch includes:

An inverter, the input end and the output end of which are respectively connected to the output end of the first operational amplifier and the input end of the calibration branch;

The input end and the output end of the first digital buffer are respectively connected to the output end of the first operational amplifier and the input end of the calibration branch; or,

a level shifter and a second digital buffer, wherein the input end and the output end of the level shifter are respectively connected to the output end of the first operational amplifier and the input end of the second digital buffer, so The output terminal of the second digital buffer is connected to the input terminal of the calibration branch.
The combined operational amplifier circuit of claim 1, wherein the discrimination branch includes a reference signal generator and a second comparator, wherein,

The reference signal generator is configured to provide a reference signal having an amplitude of the reference value to the second comparator;

The second comparator is configured to distinguish the amplitude of the signal to be calibrated from the amplitude of the reference signal and generate a discrimination result.
The combined operational amplifier circuit according to any one of claims 1 to 4, wherein the calibration branch includes a control unit and a calibration unit, wherein,

The control unit is configured to generate a control instruction for controlling the calibration unit according to the discrimination result received from the discrimination branch;

The calibration unit is configured to generate the calibration signal for calibrating the electrical characteristics of the first operational amplifier according to the control instruction sent by the control unit and send the generated calibration signal to the third operational amplifier. One operational amplifier input channel.
The combined operational amplifier circuit of claim 5, wherein the control unit is specifically configured to perform the following operations:

After receiving the discrimination result, determine whether the discrimination result is received for the first time;

If so, use a preset algorithm corresponding to the output characteristics of the calibration unit to generate a control instruction corresponding to the discrimination result, and send the control instruction to the calibration unit;

If not, it is determined whether the discrimination result received this time is the same as the discrimination result received last time. If they are the same, a preset algorithm corresponding to the output characteristics of the calibration unit is used to generate an algorithm corresponding to the discrimination result. and send the control instruction to the calibration unit. If they are different, directly send the control instruction corresponding to the last received discrimination result to the calibration unit.
The combined operational amplifier circuit of claim 5, wherein the control unit includes a micro control unit chip or a host computer.
The combined operational amplifier circuit of claim 5, wherein the calibration unit includes a digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input channel of the first operational amplifier.
The combined operational amplifier circuit of claim 8, wherein the input channel of the first operational amplifier includes the non-inverting input terminal and the inverting input terminal, or includes a differential signal inside the first operational amplifier. Signal transmission node.
The combined operational amplifier circuit of claim 1, further comprising:

A switching unit configured to connect the non-inverting input terminal and the inverting input terminal of the first operational amplifier to ground or to a voltage source providing a common mode voltage.
The combined operational amplifier circuit of claim 1, wherein the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, and the inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier. The inverting input terminal is connected.
A chip, characterized in that it includes the combined operational amplifier circuit according to any one of claims 1-11.
A signal processing device, characterized by comprising the combined operational amplifier circuit according to any one of claims 1-11.