CN102025326A - Digital self-zero calibration circuit applied for operational amplifier - Google Patents
Digital self-zero calibration circuit applied for operational amplifier Download PDFInfo
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- CN102025326A CN102025326A CN 201010606488 CN201010606488A CN102025326A CN 102025326 A CN102025326 A CN 102025326A CN 201010606488 CN201010606488 CN 201010606488 CN 201010606488 A CN201010606488 A CN 201010606488A CN 102025326 A CN102025326 A CN 102025326A
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Abstract
The invention discloses a digital self-zero calibration circuit applied for an operational amplifier, which is used for effectively improving influences of voltage drift on output. The digital self-zero calibration circuit comprises a zero-calibrated amplifier provided with a zero calibration end. The positive input end of the zero-calibrated amplifier is respectively connected with one end of a first switch and one end of a second switch, the other end of the first switch and the other end of the second switch are correspondingly connected with two ends of input voltage, and the other end of the second switch is also connected with the negative input end of the zero-calibrated amplifier; the output end of the zero-calibrated amplifier is connected with the input end of a self-zero calibration operational amplifier by an output voltage node; the output end of the self-zero calibration operational amplifier is connected with the input end of a window comparator, the output end of the window comparator is connected with a control logic circuit which controls the size of the window of the window comparator; and the zero calibration end is connected with a current-type digital-to-analog converter connected with a voltage reference circuit.
Description
Technical field
The present invention relates to the operational amplifier collimation technique, particularly a kind of digital self-correcting zero circuit that is used for operational amplifier.
Background technology
The small-signal operational amplifier is to offset voltage, voltage drift (temperature), and voltage stability (time) etc. has very high requirement; The precision amplifier that lacks self-correcting zero power energy has higher requirement (as ambient temperature) to using environment, and sexual needs system calibration steady in a long-term realizes.Therefore, the inventor thinks, is necessary to utilize the digital zero setting circuit that the small-signal operational amplifier is calibrated, with effective influence that improves voltage drift to output.
Summary of the invention
The present invention is directed to defective or deficiency that prior art exists, a kind of digital self-correcting zero circuit that is used for operational amplifier is provided, with effective influence that improves voltage drift to output.
Technical scheme of the present invention is as follows:
A kind of digital self-correcting zero circuit that is used for operational amplifier, it is characterized in that, comprise by the school nucleus amplifier, described had the zeroing end by the school nucleus amplifier, describedly connected an end of first switch and an end of second switch respectively by the positive input of school nucleus amplifier, the other end of described first switch and the corresponding two ends that are connected input voltage of the other end of second switch, the other end of described second switch also connects described by the negative input of school nucleus amplifier; Described by the input of the output of school nucleus amplifier process output voltage node connection from steady zero operational amplifier, the described input that connects window comparator from the output of steady zero operational amplifier, the output of described window comparator connects control logic circuit, and described control logic circuit is controlled the window size of described window comparator; Described zeroing end connects current mode digital-to-analog converter, and described current mode digital-to-analog converter connects voltage reference circuit, and described current mode digital-to-analog converter connects described control logic circuit by data/address bus.
What connect successively is described by the school nucleus amplifier, from steady zero operational amplifier, window comparator, control logic circuit and current mode digital-to-analog converter constitute nullring road, school: offset voltage is exported in being produced by the school nucleus amplifier of input offset voltage, the output offset voltage is after amplifying from steady zero operational amplifier, sending into window comparator compares and provides at present by the state of school nucleus amplifier, then by logic control circuit Control current type digital to analog converter output negative feedback current, adjusting is by the electric current of the imbalance adjustable side of school nucleus amplifier, thereby reduce by the output offset voltage of school nucleus amplifier, this process lasts till that always the output offset voltage enters in the window ranges of window comparator.
The window comparative level of described window comparator is undertaken digital control by logic control circuit.
Described input stage by the school nucleus amplifier has the zeroing end.
Technique effect of the present invention is as follows:
(1) digital zero setting of realization broadband small signal amplifier.The control line of DAC can be directly relevant with processor data bus, can realize the school remainder according to storage, operations such as modification.
(2) utilize the arrowband to realize that from steady nucleus amplifier and window comparator no-voltage detects, the analogue window with comparator can numeral be set.
(3) can the digital adjustable range of setting offset voltage.
(4) controlling of sampling of no-voltage does not constitute the output loading effect of amplifier.
(5) practical application effect is: this technology is applied in the output amplifier of Ultra-low Frenquency Voltage, has improved the influence of the output drift of Ultra-low Frenquency Voltage to output effectively.According to the test result under the different temperatures situation, voltage imbalance and drift thereof are reduced to original 0.2-0.1 doubly.
Description of drawings
Fig. 1 is a theory structure schematic diagram of the present invention.
Embodiment
The present invention will be described below in conjunction with accompanying drawing (Fig. 1).
As shown in Figure 1, a kind of digital self-correcting zero circuit that is used for operational amplifier, it is characterized in that, comprise by school nucleus amplifier A, described had the zeroing end by school nucleus amplifier A, described positive input "+" by the school nucleus amplifier connects an end of first switch S 1 and the end of second switch S2 respectively, the corresponding two ends that are connected input voltage vin of the other end of the other end of described first switch S 1 and second switch S2, the other end of described second switch S2 also connects described by the negative input "-" of school nucleus amplifier A; Describedly connected from steady zero operational amplifier promptly from the input of steady zero OPA (Operation Amplifier) through output voltage V out node by the output of school nucleus amplifier, the described input that connects window comparator from the output of steady zero operational amplifier, the output of described window comparator connects control logic circuit, and described control logic circuit is controlled the window size of described window comparator; It is current mode DAC (DAC:digital to analog converter) that described zeroing end connects current mode digital-to-analog converter, described current mode digital-to-analog converter connects voltage reference circuit, and described current mode digital-to-analog converter connects described control logic circuit by data/address bus.What connect successively is described by school nucleus amplifier A, from steady zero operational amplifier, window comparator, control logic circuit and current mode digital-to-analog converter constitute nullring road, school: offset voltage Vos is exported in being produced by school nucleus amplifier A of input offset voltage Vios, output offset voltage Vos is after amplifying from steady zero operational amplifier OPA (Operational Amplifier), sending into window comparator compares and provides at present by the state of school nucleus amplifier A, then by logic control circuit Control current type digital to analog converter output negative feedback current, adjusting is by the electric current of the imbalance adjustable side of school nucleus amplifier, thereby reduce by the output offset voltage Vos of school nucleus amplifier A, this process lasts till that always output offset voltage Vos enters in the window ranges of window comparator.Vos (output voltage imbalance: os-offset).The window comparative level of described window comparator is undertaken digital control by logic control circuit.Describedly constituted by the cascode level of the input stage of school nucleus amplifier by the difference symmetry.
Current mode DAC=current mode digital-to-analog converter.(DAC：digital?to?analog?converter)。
Nullring road, school: (disconnect S1, closed S2 enters school zero), input offset voltage be Vios by the output Vos of school nucleus amplifier A, after amplifying from steady zero OPA (Operational Amplifier), send into window comparator (the window comparative level can be undertaken digital control by logic control circuit) and compare the state that provides present amplifier A, then by logic control circuit Control current type DAC output negative feedback current, adjusting is by the electric current of the imbalance adjustable side of school nucleus amplifier, thereby reduces Vos (the output voltage imbalance: os-offset) of A.This process can last till always that Vos enters in the window ranges of window comparator.(nullring road, school is represented with the arrow of 4 Cheng Huan in Fig. 1).
From promptly steady certainly zero operational amplifier of steady zero OPA (Operation Amplifier).
Vios (the input voltage imbalance: ios-input offset)/Vin (input voltage)/Vos (output offset voltage)/± V
w(the comparator window level: w-window)/kVos (=k*Vos, the k of Vos are doubly)/Transistor-Transistor Logic level (standard digital circuitry logic level: be used for present most of digital circuit).
Regulation loop: current mode DAC output current directly is injected into the zeroing end of A.Feedback loop: from steady zero OPA＞window comparator＞logic control circuit＞regulation loop.
About know-why: being calibrated amplifier A input offset voltage is that Vos switch S 1 disconnects, when S2 is closed, enter the Vos calibration cycle: amplifier A output offset voltage is by having amplifying from steady nucleus amplifier of zero imbalance and zero shift, after window comparator provides the current Vos information of amplifier A, when kVos is outside window level, the state information of output Transistor-Transistor Logic level, indication control logic begin to carry out Vos and adjust.Nullring road, whole school drops in the window comparator output imbalance of amplifier A under the control of control logic, and the window size of window comparator can be set by control logic.Regulation loop forms feedback loop, as long as the output of A is not in the predetermined window, control logic will change the input code of current mode DAC, and the imbalance of being exported two-way complementary current control amplifier by DAC progresses in the window ranges of comparator.
If the gain of auto-zero OPA is G0, the window of comparator is ± V
w, then, the output imbalance of school zero back amplifier A:
Determine after the predetermined imbalance scope of amplifier and window comparator is set gain G from steady zero OPA together.
The input stage that generally has the operational amplifier of outside imbalance adjustable side is made of the cascode level of difference symmetry, and collector current is respectively I
C1, I
C2, then the output imbalance of being introduced by input stage can be expressed as:
K wherein, T, q is respectively physical constant.Is1, Is2 are respectively the reverse saturation current of input stage transistor.Quantitatively calculate and show: when collector current changed 3% than Ic1/Ic2, the output imbalance can change 1.5mV.Adopt common 8bit current mode DAC (0mA～2mA), maximum current ratio scope is: 0.4%～99%, have very wide adjustable range.
Indicate at this, more than narration helps those skilled in the art to understand the invention, but and the protection range of unrestricted the invention.Any do not break away from the invention flesh and blood to being equal to replacement, modify improving and/or deleting numerous conforming to the principle of simplicity and the enforcement carried out of above narration, all fall into the protection range of the invention.
Claims (4)
1. digital self-correcting zero circuit that is used for operational amplifier, it is characterized in that, comprise by the school nucleus amplifier, described had the zeroing end by the school nucleus amplifier, describedly connected an end of first switch and an end of second switch respectively by the positive input of school nucleus amplifier, the other end of described first switch and the corresponding two ends that are connected input voltage of the other end of second switch, the other end of described second switch also connects described by the negative input of school nucleus amplifier; Described by the input of the output of school nucleus amplifier process output voltage node connection from steady zero operational amplifier, the described input that connects window comparator from the output of steady zero operational amplifier, the output of described window comparator connects control logic circuit, and described control logic circuit is controlled the window size of described window comparator; Described zeroing end connects current mode digital-to-analog converter, and described current mode digital-to-analog converter connects voltage reference circuit, and described current mode digital-to-analog converter connects described control logic circuit by data/address bus.
2. the digital self-correcting zero circuit that is used for operational amplifier according to claim 1, it is characterized in that, what connect successively is described by the school nucleus amplifier, from steady zero operational amplifier, window comparator, control logic circuit and current mode digital-to-analog converter constitute nullring road, school: offset voltage is exported in being produced by the school nucleus amplifier of input offset voltage, the output offset voltage is after amplifying from steady zero operational amplifier, sending into window comparator compares and provides at present by the state of school nucleus amplifier, then by logic control circuit Control current type digital to analog converter output negative feedback current, adjusting is by the electric current of the imbalance adjustable side of school nucleus amplifier, thereby reduce by the output offset voltage of school nucleus amplifier, this process lasts till that always the output offset voltage enters in the window ranges of window comparator.
3. the digital self-correcting zero circuit that is used for operational amplifier according to claim 1 is characterized in that the window comparative level of described window comparator is undertaken digital control by logic control circuit.
4. the digital self-correcting zero circuit that is used for operational amplifier according to claim 1 is characterized in that, described input stage by the school nucleus amplifier has the zeroing end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010606488 CN102025326A (en) | 2010-12-24 | 2010-12-24 | Digital self-zero calibration circuit applied for operational amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010606488 CN102025326A (en) | 2010-12-24 | 2010-12-24 | Digital self-zero calibration circuit applied for operational amplifier |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103063929A (en) * | 2013-01-05 | 2013-04-24 | 苏州市静电设备研究所有限责任公司 | Oil product conductivity tester system |
| CN103066926A (en) * | 2012-12-11 | 2013-04-24 | 中国人民解放军海军工程大学 | Automatic digital zeroing circuit for integral circuit |
| CN103248423A (en) * | 2013-04-09 | 2013-08-14 | 中兴通讯股份有限公司 | Zero setting method and zero setting device for OTDR |
| CN104796680A (en) * | 2014-01-17 | 2015-07-22 | 马维尔国际有限公司 | Audio or video signal processing system, method and electronic equipment |
| CN107990992A (en) * | 2017-11-27 | 2018-05-04 | 电子科技大学 | Temperature sensors of high precision and precision adjusting method |
| CN109212448A (en) * | 2018-08-22 | 2019-01-15 | 中国科学院地质与地球物理研究所 | Auto zeroing circuit |
| CN110914653A (en) * | 2017-07-26 | 2020-03-24 | ams国际有限公司 | Optical sensor device and method for optical sensing |
| CN113726339A (en) * | 2021-08-19 | 2021-11-30 | 江苏润石科技有限公司 | Error feedback-based offset voltage reduction method and data converter |
| CN114336519A (en) * | 2022-01-10 | 2022-04-12 | 无锡市晶源微电子有限公司 | Control circuit of leakage protector |
| WO2024016519A1 (en) * | 2022-07-18 | 2024-01-25 | 普源精电科技股份有限公司 | Combined operational amplifier circuit, chip and signal processing apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1748362A (en) * | 2003-02-11 | 2006-03-15 | 皇家飞利浦电子股份有限公司 | Self zeroing for critical, continuous-time applications |
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2010
- 2010-12-24 CN CN 201010606488 patent/CN102025326A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1748362A (en) * | 2003-02-11 | 2006-03-15 | 皇家飞利浦电子股份有限公司 | Self zeroing for critical, continuous-time applications |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066926A (en) * | 2012-12-11 | 2013-04-24 | 中国人民解放军海军工程大学 | Automatic digital zeroing circuit for integral circuit |
| CN103066926B (en) * | 2012-12-11 | 2015-08-19 | 中国人民解放军海军工程大学 | The steady zero circuit of automatic digital for integrating circuit |
| CN103063929A (en) * | 2013-01-05 | 2013-04-24 | 苏州市静电设备研究所有限责任公司 | Oil product conductivity tester system |
| CN103248423A (en) * | 2013-04-09 | 2013-08-14 | 中兴通讯股份有限公司 | Zero setting method and zero setting device for OTDR |
| US9726574B2 (en) | 2013-04-09 | 2017-08-08 | Zte Corporation | Zeroing method and zeroing device for optical time-domain reflectometer |
| CN103248423B (en) * | 2013-04-09 | 2018-01-05 | 中兴通讯股份有限公司 | The adjusting zero method and balancing controls of a kind of optical time domain reflectometer |
| CN104796680A (en) * | 2014-01-17 | 2015-07-22 | 马维尔国际有限公司 | Audio or video signal processing system, method and electronic equipment |
| CN104796680B (en) * | 2014-01-17 | 2018-04-24 | 马维尔国际有限公司 | Audio or video signal processing system, method and electronic equipment |
| CN110914653A (en) * | 2017-07-26 | 2020-03-24 | ams国际有限公司 | Optical sensor device and method for optical sensing |
| US11326942B2 (en) | 2017-07-26 | 2022-05-10 | Ams International Ag | Optical sensor arrangement and method for light sensing |
| CN110914653B (en) * | 2017-07-26 | 2022-04-01 | ams国际有限公司 | Optical sensor device and method for optical sensing |
| CN107990992A (en) * | 2017-11-27 | 2018-05-04 | 电子科技大学 | Temperature sensors of high precision and precision adjusting method |
| CN107990992B (en) * | 2017-11-27 | 2019-10-11 | 电子科技大学 | Temperature sensors of high precision and precision adjusting method |
| CN109212448A (en) * | 2018-08-22 | 2019-01-15 | 中国科学院地质与地球物理研究所 | Auto zeroing circuit |
| CN113726339A (en) * | 2021-08-19 | 2021-11-30 | 江苏润石科技有限公司 | Error feedback-based offset voltage reduction method and data converter |
| CN114336519A (en) * | 2022-01-10 | 2022-04-12 | 无锡市晶源微电子有限公司 | Control circuit of leakage protector |
| CN114336519B (en) * | 2022-01-10 | 2023-08-22 | 无锡市晶源微电子股份有限公司 | Control circuit of leakage protector |
| WO2024016519A1 (en) * | 2022-07-18 | 2024-01-25 | 普源精电科技股份有限公司 | Combined operational amplifier circuit, chip and signal processing apparatus |
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Inventor after: Jiang Fangliang Inventor after: Ji Qizheng Inventor before: Jiang Fangliang |
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Free format text: CORRECT: INVENTOR; FROM: JIANG FANGLIANG TO: JIANG FANGLIANG JI QIZHENG |
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Application publication date: 20110420 |