CN104868701A

CN104868701A - Hybrid compensating circuit of power supply converter

Info

Publication number: CN104868701A
Application number: CN201410059782.6A
Authority: CN
Inventors: 唐健夫; 潘均宏; 陈曜洲
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2014-02-21
Filing date: 2014-02-21
Publication date: 2015-08-26

Abstract

The invention provides a hybrid compensating circuit of a power supply converter. A digital signal is generated according to a feedback signal and a reference value related to an output voltage of the power supply converter, the digital signal is converted into a first simulated signal, a second signal is generated in such a manner that the first signal is offset by means of a variable offset value, and a third signal is generated by filtering out a high frequency component of the second signal so as to stabilize the output voltage. A large capacitor is not needed in the hybrid compensating circuit, so that the hybrid compensating circuit can be integrated into an integrated circuit.

Description

The hybrid compensating circuit of power supply changeover device

Technical field

The present invention relates to a kind of power supply changeover device, particularly about a kind of hybrid compensating circuit of power supply changeover device.

Background technology

In the feedback loop of power supply changeover device, compensating circuit is needed to compensate to make loop stability to phase margin (phasemargin).Traditional analog compensating circuit comprises EA type compensating circuit 10 as shown in Figure 1 or the gm type compensating circuit 14 shown in Fig. 2.With reference to Fig. 1, EA type compensating circuit 10 comprises error amplifier 12, between the inverting input that electric capacity C1 and resistance R3 is connected on error amplifier 12 and output, resistance R4 is in parallel with electric capacity C1 and resistance R3, error amplifier 12 difference of amplifying between feedback signal Vfb and reference value Vref produces signal Vcomp for power supply changeover device regulated output voltage Vo, and resistance R3, R4 and electric capacity C1 are in order to compensating signal Vcomp.In some applications, the resistance R4 of Fig. 1 can omit.With reference to Fig. 2, gm type compensating circuit 14 comprises transduction amplifier 16, resistance R3 and electric capacity C1 be connected on transduction amplifier 16 output and ground end GND between, electric capacity C2 is in parallel with resistance R3 and electric capacity C1, difference between feedback signal Vfb and reference value Vref is converted to electric current I comp by transduction amplifier, and resistance R3 and electric capacity C1, C2 produce the signal Vcomp compensated according to electric current I comp.Using circumscribed compensating circuit to need to take a branch connecting pin of control IC, in order to reduce pin count, having increasing scheme to be incorporated in IC by compensating circuit, such as U.S. Patent number 7,504,888.Generally speaking, gm type compensating circuit 14 is easier to be incorporated in integrated circuit (IC), but these schemes also have many restrictions, in general, high switching frequency direct current, is therefore easier to compensating circuit to be incorporated in IC owing to limit and zero point being greater than 10KHz to the control IC of DC power converter.And in low frequency range application, such as power factor correction (Power Factor Correction; PFC) the control IC of power supply changeover device or other similar PFC or power supply changeover device, compensating circuit 14 needs bulky capacitor C1 and C2, but because the consideration of cost and area, bulky capacitor C1 and C2 is difficult to all be incorporated in IC.More specifically, the input voltage of PFC power supply changeover device is the alternating voltage with 60Hz a-c cycle, therefore its control IC needs the limit of low gain and low frequency and zero point and reaches low frequency range loop with filtering a-c cycle, therefore compensating circuit 14 needs bulky capacitor C1 and C2 to compensate, make the change of signal Vcomp comparatively slow, could this a-c cycle of filtering.But bulky capacitor C1 and C2 meeting demand cannot be realized in IC, therefore external bulky capacitor C1 and C2 of use one branch connecting pin is needed, reducing electric capacity C1 and C2 if want makes it can be incorporated in IC, then need electric current I comp to drop to and receive (nano) amp steps or skin (pico) amp steps, but so little electric current is easy to be subject to processing procedure impact and cannot accurately control, and is therefore difficult to realize.

Because analog compensating circuit is not easily integrated; therefore many digital compensating circuits are had to be suggested; such as U.S. Patent number 7; 743; 266 and 7,894,218; although these digital compensating circuits can be incorporated in the control IC of PFC power supply changeover device, usually need complicated Digital Signal Processing (digital signal Processing; DSP) algorithm, thus needs to take larger chip area, causes cost increase and chip size to increase.On the other hand, change signal Vcomp slowly and can cause power supply changeover device cannot fast reaction load instantaneous, cause output voltage Vo that large voltage step (drop) or overshoot (overshoot) occur.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art and defect, propose a kind of hybrid compensating circuit of power supply changeover device.

For reaching above-mentioned purpose, with regard to one of them viewpoint, the present invention proposes a kind of hybrid compensating circuit of power supply changeover device, comprise: digital signal processor, in order to provide one first limit, this digital signal processor produces digital signal according to feedback signal and reference value, and wherein this feedback signal is relevant to the output voltage of this power supply changeover device; And digital analog converter, couple this digital signal processor, this digital signal is converted to the first signal of simulation.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: skew injector, couple this digital analog converter, in order to provide a zero point, this skew injector provides variable offset values to produce secondary signal to offset this first signal, and wherein this variable offset values is determined by the difference between this feedback signal and this reference value.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: low pass filter, couples this digital analog converter, and in order to provide one second limit, the radio-frequency component that this digital analog converter filters this first signal produces secondary signal.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: skew injector, couple this digital analog converter, provide variable offset values to produce secondary signal to offset this first signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; And low pass filter, couple this skew injector, the radio-frequency component of this secondary signal of filtering produces the 3rd signal and stablizes this output voltage for this power supply changeover device.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: low pass filter, couples this digital analog converter, and the radio-frequency component of this first signal of filtering produces secondary signal; And skew injector, couple this low pass filter, provide variable offset values to stablize this output voltage to offset this secondary signal generation the 3rd signal for this power supply changeover device, wherein this variable offset values is determined by the difference between this feedback signal and this reference value.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: skew injector, couple this digital signal processor, provide variable offset values to produce secondary signal to offset this digital signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; And adder, this first signal is added with this secondary signal, produces the 3rd signal and stablize this output voltage for this power supply changeover device.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: skew injector, couple this digital signal processor, provide variable offset values to produce secondary signal to offset this digital signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; Low pass filter, couples this skew injector, and the radio-frequency component of this secondary signal of filtering produces the 3rd signal; And adder, by this first signal and the 3rd signal plus, produce the 4th signal and stablize this output voltage for this power supply changeover device.

For reaching above-mentioned purpose, with regard to another viewpoint, the present invention proposes a kind of hybrid compensating circuit of power supply changeover device, comprise: digital signal processor, produce first and second digital signal according to output voltage feedback signal and reference value, wherein this output voltage credit is number relevant to the output voltage of this power supply changeover device; Digimigration injector, couples this digital signal processor, to produce variable offset values according to this second digital signal; Adder, is added this first digital signal with this variable offset values, maybe this first digital signal is added with the coherent signal of this variable offset values; And digital analog converter, couple this adder, the coherent signal of the output of this adder or the output of this adder is converted to analog signal.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: low pass filter, couples this digital analog converter, in order to the radio-frequency component of this analog signal of filtering.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: digital filter, is coupled between this digimigration injector and this adder, produces the coherent signal of this variable offset values in order to filter this variable offset values.

In one embodiment, above-mentioned hybrid compensating circuit can more comprise: digital filter, is coupled between this adder and this digital analog converter, in order to filter the output of this adder and to produce the coherent signal of the output of this adder.

In one embodiment, the back coupling of this digimigration injector controls a frequency of operation of this digital signal processor.

For reaching above-mentioned purpose, with regard to another viewpoint, the present invention proposes a kind of hybrid compensating circuit of power supply changeover device, comprise: digital signal processor, produce first and second digital signal according to output voltage feedback signal and reference value, wherein this output voltage credit is number relevant to the output voltage of this power supply changeover device; Digimigration injector, couples this digital signal processor, to produce variable offset values according to this second digital signal; First digital analog converter, couples this digital signal processor, and this first digital signal is converted to the first analog signal; Second digital analog converter, couples this digimigration injector, this variable offset values is converted to the second analog signal; And adder, this first analog signal is added with this second analog signal, is maybe added with the second analog signal by the coherent signal of this first analog signal.

In one embodiment, this hybrid compensating circuit more can comprise low pass filter, is coupled between this first digital analog converter and this adder or is coupled to the output of this adder.

For reaching above-mentioned purpose, with regard to another viewpoint, the present invention proposes a kind of hybrid compensating circuit of power supply changeover device, comprising: digital signal processor, produce the first digital signal according to output voltage feedback signal and reference value, wherein this feedback signal is relevant to the output voltage of this power supply changeover device; Digital filter, couples this digital signal processor, to filter this first digital signal; And digital analog converter, couple this digital filter, the output of this digital filter is converted to analog signal.

In one embodiment, this digital signal processor comprises: successively ask nearly buffer memory analogue-digital converter (SAR-ADC, Successive Approximation Register Analog toDigital Converter), produce a lifting signal according to this output voltage feedback signal and this reference value; And lifting counting circuit, wherein the output signal of this lifting counting circuit is controlled by this lifting signal and rises accordingly or decline.

In one embodiment, this digimigration injector produces numeral or the coding that corresponds to α (Vfb1-Vref1), and wherein α is arithmetic number, and Vfb1 is this output voltage feedback signal, and Vref1 is this reference value.

In one embodiment, this digital filter comprises a D flip-flop or a rolling average circuit.

Accompanying drawing explanation

Fig. 1 is traditional EA type compensating circuit;

Fig. 2 is traditional gm type compensating circuit;

Fig. 3 A is an embodiment according to hybrid compensating circuit of the present invention;

Fig. 3 B-3H is other embodiment according to hybrid compensating circuit of the present invention;

Fig. 4 is a specific embodiment of the hybrid compensating circuit of Fig. 3 A;

Fig. 5 is the current-voltage characteristic curve of the transduction amplifier of Fig. 2;

Fig. 6 is that the voltage change ratio dVa1/dt of the first signal Va1 of Fig. 4 is to the characteristic curve of voltage Vref1-Vfb1;

Fig. 7 is another specific embodiment of the hybrid compensating circuit of Fig. 3 A;

Fig. 8 is the frequency signal of Fig. 7 and the sequential chart of pulse signal;

Fig. 9 is that the voltage change ratio dVa1/dt of the first signal Va1 of Fig. 7 is to the characteristic curve of voltage Vref1-Vfb1;

Figure 10 is another specific embodiment of the hybrid compensating circuit of Fig. 3 A;

Figure 11 is output voltage and the signal Vcomp of the power supply changeover device using the gm type simulated formula compensating circuit of Fig. 2 and hybrid compensating circuit of the present invention to produce;

Figure 12 A-12G is other several specific embodiment of hybrid compensating circuit;

Figure 13 is a specific embodiment of digital signal processor 122;

Figure 14 A-14D is for successively to ask nearly buffer (SAR, Successive ApproximationRegister) analog-digital converter (ADC, Analog to Digital Converter) 132, be called for short several specific embodiments of SAR-ADC;

Figure 15 is a specific embodiment of lifting counting circuit 134;

Figure 16 A-16I is several specific embodiments of digimigration injector 126;

Figure 17 A-17B is two specific embodiments of digital filter 128.

Symbol description in figure

10 EA type compensating circuits

12 error amplifiers

14 gm type compensating circuits

16 transduction amplifiers

The hybrid compensating circuit of 20,20a-20g

22 digital signal processor

24 digital analog converters

26 skew injectors

28 low pass filters

29 adders

30 comparators

32 inverters

34 hysteresis comparators

36 hysteresis comparators

38 computing transduction amplifiers

40 oscillators

42 controllers

44 up-down counters

46 current sources

48 current sources

50 current sources

52 current sources

The first end of 54 resistance Rof

Second end of 56 resistance Rof

60 multiplexers

62 comparators

64 pulse generators

70 comparators

72 comparators

74 comparators

76 comparators

78 comparators

80 controllers

82 frequency eliminators

84 frequency eliminators

86 frequency eliminators

88 frequency eliminators

90 operational amplifiers

The output voltage of 92 power supply changeover devices

The output voltage of 94 power supply changeover devices

96 feedback signals

98 feedback signals

The hybrid compensating circuit of 120,120a ~ 120f

122 digital signal processor

123 adders

124,124a DAC

126 digimigration injectors

128 digital filters

129 LPF

132 SAR-ADC

134 lifting counting circuits

136 OSC

141 error amplifiers

142 ~ 144 comparators

146 controllers and digital generator

148 DAC

152 controllers

154 up-down counters

162 addition/subtraction devices

164 digital multipliers

166 frequency eliminating circuits

168 DAC

Embodiment

With reference to Fig. 3, hybrid compensating circuit 20 according to the present invention can be applied in various types of power supply changeover device, and such as direct current is to DC power converter and PFC power supply changeover device.In hybrid compensating circuit 20, digital signal processor 22 produces digital signal Sd according to the feedback signal Vfb1 relevant to the output voltage of power supply changeover device and reference value Vref1, digital analog converter (Digital-to-Analog Converter; DAC) 24 the first signal Va1 digital signal Sd being converted to simulation; skew injector (offset injector) 26 provides variable offset values to offset the first signal Va1 and produces secondary signal Va2, low pass filter (Low Pass Filter; LPF) radio-frequency component of 28 filtering secondary signal Va2 produces the output voltage of the 3rd signal Vcomp for stabilized power supply transducer.Gm type compensating circuit 14 as shown in Figure 2 simulated by hybrid compensating circuit 20.As everyone knows, gm type compensating circuit 14 provides two limits and a zero point, hybrid compensating circuit 20 can provide two limits and a zero point equally, in detail, digital signal processor 22 and DAC24 can be considered first limit generator/compensator, in order to provide the first limit, skew injector 26 can be considered generator/compensator at zero point, in order to provide zero point, LPF28 can be considered second limit generator/compensator, in order to provide the second limit.

It should be noted that: according to the present invention, definitely must not produce/compensate two limits and a zero point that is the pole and zero number that produces/compensate can change.Such as, in some applications, a limit or a limit and a zero point or two limits can only be produced/compensate.Fig. 3 B-3D illustrates and shows hybrid compensating circuit 20a-20c of these application of cooperation.In addition, in generation/compensation two limits and the embodiment at a zero point, LPF28 must not be arranged on the rear of skew injector 26 yet and connect with digital signal processor 22 and DAC24, and can be other type of attachment.For example, Fig. 3 E shows the embodiment that LPF28 is arranged on skew injector 26 front; In Fig. 3 F embodiment, skew injector 26 and LPF28 are arranged on another paths, and to provide the compensation at a zero point and the second limit, and the compensating signal that another path of the output and this of DAC24 produces is added by adder 29; Fig. 3 G shows the embodiment similar to Fig. 3 F, but eliminates LPF28.Except above-mentioned arrangement, LPF28 also can be arranged on other position, such as but not limited in the embodiment of Fig. 3 H, LPF28 is arranged on the rear of adder 29.

Fig. 4 is a specific embodiment of hybrid compensating circuit 20.In order to realize the first limit of low frequency, digital signal processor 22 and DAC24 is used to simulate the transduction amplifier 16 of gm type compensating circuit 14.The digital signal processor 22 of Fig. 4 comprises comparator 30 and compares feedback signal Vfb1 and reference value Vref1 generation comparison signal Sc1, inverter 32 by anti-phase for comparison signal Sc1 generation signal Sc2 to controller 42, oscillator 40 provides frequency signal Clk to controller 42 and up-down counter 44, controller 42 samples signal Sc2 in response to frequency signal Clk, when sampling result represents that feedback signal Vfb1 is greater than reference value Vref1, controller 42 sends control signal Down to up-down counter 44 to downgrade digital signal Sd position, and then downgrade the power output of power supply changeover device.When sampling result represents feedback signal Vfb1 lower than reference value Vref1, controller 42 sends control signal Up to up-down counter 44 to increase digital signal Sd position, and then increases the power output of power supply changeover device.The control signal Up that up-down counter 44 exports according to frequency signal Clk sampling controller 42 and Down is to adjust digital signal Sd.Digital signal Sd is converted to the first signal Va1 by DAC24.DAC24 is quite common circuit, its internal circuit and operate in this and repeat no more.When frequency signal Clk is low frequency, the frequency of sampling is lower, and the change of digital signal Sd is comparatively slow, and the 3rd signal Vcomp causing hybrid compensating circuit 20 to export changes slowly, and this effect is as gm type compensating circuit 14 uses bulky capacitor C1 and C2.

When power supply changeover device generation load instantaneous, if the 3rd signal Vcomp that hybrid compensating circuit 20 exports still slowly changes, cannot fast reaction, cause output voltage Vo that large voltage step or overshoot occur.In order to improve this problem, the digital signal processor 22 of Fig. 4 also comprises hysteresis comparator 34 and compares feedback signal Vfb1 and critical value VH1 generation comparison signal SH to controller 42, hysteresis comparator 36 compares feedback signal Vfb1 and critical value VL1 and produces comparison signal SL to controller 42, and the computing transduction amplifier 38 difference DELTA V amplified between feedback signal Vfb1 and reference value Vref1 produces frequency adjusted signal Sfm to oscillator 40 with the frequency of the signal Clk that adjusts frequency.When difference DELTA V between feedback signal Vfb1 and reference value Vref1 increases, frequency adjusted signal Sfm will heighten the frequency of frequency signal Clk to accelerate sampling frequency, and then accelerate the change of digital signal Sd and accelerate the torsion rate (slew rate) of the 3rd signal Vcomp, when feedback signal Vfb1 is greater than critical value VH1 or is less than critical value VL1, hysteresis comparator 34 or 36 sends comparison signal SL or SH to oscillator 40, to make the frequency of frequency signal Clk rise to maximum, and then digital signal Sd is made to increase with peak frequency or downgrade.In addition, when feedback signal Vfb1 is greater than critical value VH1, controller 42 also sends control signal Down_limit to up-down counter 44 according to comparison signal SL, make this up-down counter 44, with peak frequency, digital signal Sd is cut to minimum value to improve the torsion rate of the 3rd signal Vcomp, the power output of power supply changeover device is reduced fast, makes output voltage drop to default level rapidly.Same, when feedback signal Vfb1 is less than critical value VL1, controller 42 sends control signal Up_limit to up-down counter 44 according to comparison signal SH, make this up-down counter 44, with peak frequency, digital signal Sd be increased maximum, thus the torsion rate of the 3rd signal Vcomp is improved, make the power output of power supply changeover device increase, make output voltage be climbed to default level.In other embodiments, when feedback signal VFB1 is greater than or less than critical value VH1 or VL1, make up-down counter 44 also immediately digital signal Sd can be increased minimum value or maximum.When there is load instantaneous, difference DELTA V between feedback signal Vfb1 and reference value Vref1 increases, therefore the sampling frequency of controller 42 and up-down counter 44 is accelerated, therefore the torsion rate (slew rate) of the 3rd signal Vcomp is accelerated, and digital signal Sd can be made immediately or with the fastest frequency decrease to minimum value or rise to maximum when feedback signal Vfb1 is greater than critical value VH1 or be less than critical value VL1, therefore effectively can improve the load instantaneous response of power supply changeover device.

The current-voltage characteristic curve of the transduction amplifier 16 of Fig. 2 as shown in Figure 5, can obtain from Fig. 2

Ce × Vcomp=Icomp × T, formula 1

Wherein Ce is the equivalent capacity of electric capacity C1 and C2, and T is the time of generation current Icomp.Can push away further from formula 1

Icomp/Ce=Vcomp/T, formula 2

Determine a voltage change ratio dVcomp/dt by the known electric current I comp of formula 2 and electric capacity Ce, electric capacity Ce is definite value again, therefore electric current I comp is proportional to voltage change ratio dVcomp/dt, and therefore the Y-axis of Fig. 5 also can be considered as voltage change ratio dVcomp/dt.The digital signal processor 22 of Fig. 3 A and DAC24 simulation transduction amplifier 16 also can obtain similar voltage change ratio, such as Fig. 6 is that the voltage change ratio dVa1/dt (i.e. torsion rate) of the first signal Va1 of the DAC24 of Fig. 4 is to the characteristic curve of the input voltage Vfb1 of digital signal processor 22, the same with the curve of Fig. 5 between critical value VL1 and VH1, then hysteresis zone is had at two ends, when feedback signal Vfb1 rise to be greater than critical value VH1 time, digital signal Sd is downgraded with the fastest sampling frequency, therefore the first signal Va1 has the fastest negative voltage rate of change-dVa1/dt_max, until feedback signal Vfb1 drops to be less than magnetic hysteresis critical value Vhy1, the voltage change ratio dVa1/dt of the first signal Va1 just gets back to original level, same, when feedback signal Vfb1 drop to be less than critical value VL1 time, digital signal Sd is increased with the frequency of the fastest frequency signal Clk, therefore the first signal Va1 has the fastest forward voltage rate of change dVa1/dt_max, until feedback signal Vfb1 rises to be greater than magnetic hysteresis critical value Vhy2, the voltage change ratio dVa1/dt of the first signal Va1 just gets back to original level.

In the fig. 4 embodiment, skew injector 26 comprises current source 46 and switch M1 is connected between the first end 54 of power end Vcc and resistance Rof, current source 48 and switch M2 be connected on resistance Rof first end 54 and ground end GND between, current source 50 and switch M3 are connected between second end 56 of power end Vcc and resistance Rof, current source 52 and switch M4 be connected on resistance Rof the second end 56 and ground end GND between.Switch M1 and M4 is controlled by come the control signal Down of self-controller 42, and switch M2 and M3 is controlled by come the control signal Up of self-controller 42, by control switch M1, M2, M3 and M4, can determine the direction of electric current Iof on resistance Rof.Current source 46,48,50 and 52 determines the size of electric current I of according to the frequency adjusted signal Sfm from computing transduction amplifier 38, and then determines that variable offset values Vof produces secondary signal Va2 to offset the first signal Va1.Because frequency adjusted signal Sfm is relevant with the difference DELTA V between feedback signal Vfb1 and reference value Vref1, therefore variable offset values Vof also changes with difference DELTA V.In other embodiments, current source 46,48,50 and 52 also can change the signal relevant to difference DELTA V according to other into and decide electric current I of.The low pass filter 28 of Fig. 4 comprises the RC filter be made up of resistance Rf and electric capacity Cf, produces the 3rd signal Vcomp to secondary signal Va2 filtering.From the physical significance of control loop, the zero point of gm compensating circuit 14 compensates as phase-lead (phase lead), second limit is similar low pass filter then, therefore hybrid compensating circuit 20 of the present invention utilizes skew injector 26 to provide the change in voltage of moment to simulate the effect at zero point, and realizes the second limit with RC filter.

Fig. 7 is another specific embodiment of the hybrid compensating circuit 20 of Fig. 3 A, digital signal processor 22 comprises multiplexer 60 according to pulse signal Sp1 ~ Sp5 sequentially by critical value VH1, critical value VH2, reference value Vref1, critical value VL2 and critical value VL1 is supplied to the non-inverting input of comparator 62, wherein VH1>VH2>Vref1> VL2>VL1, the inverting input of comparator 62 receives feedback signal Vfb1, feedback signal Vfb1 is compared critical value VH1 by comparator 62 respectively, VH2, VL1 and VL2 and reference value Vref1, and send comparison signal to controller 42, the comparison signal sampling that controller 42 exports comparator 62 according to frequency signal Clk and pulse signal Sp1 ~ Sp5, determine control signal Up or Down according to this to up-down counter 44 to increase or to downgrade digital signal Sd, according to comparative result, controller 42 also judges whether feedback signal Vfb1 is greater than maximum critical value VH1 or is less than minimum critical value VL1, if feedback signal Vfb1 is greater than critical value VH1, controller 42 sends control signal Down_limit makes up-down counter 44 immediately or with peak frequency digital signal Sd be downgraded minimum value to strengthen the torsion rate of the 3rd signal Vcomp, if feedback signal Vfb1 is less than critical value VL1, controller 42 sends control signal Up_limit makes up-down counter 44 increase to maximum digital signal Sd to strengthen the torsion rate of the 3rd signal Vcomp immediately or with peak frequency.Controller 42 also determines frequency adjusted signal Sfm to oscillator 40 with the frequency of the signal Clk that adjusts frequency according to comparative result, when difference between feedback signal Vfb1 and reference value Vref1 is larger, the frequency of frequency signal Clk is higher, to strengthen the torsion rate of the 3rd signal Vcomp, improve load instantaneous response.When feedback signal Vfb1 is greater than critical value VH1 or is less than critical value VL1, frequency adjusted signal Sfm increases to maximum by making the frequency of frequency signal Clk, to accelerate the sampling frequency of controller 42 and up-down counter 44.Pulse generator 64 produces pulse signal Sp1 ~ Sp5 as shown in Figure 8 according to frequency signal Clk, and in each cycle T of frequency signal Clk, pulse generator 64 sequentially produces pulse signal Sp1 ~ Sp5 to multiplexer 60.

The skew injector 26 of Fig. 7 changes into by the variable resistor of switch control rule by the resistance Rof of Fig. 4, its resistance changes with the difference DELTA V between feedback signal Vfb1 and reference value Vref1, current source 46,48,50 and 52 provides fixed current, therefore is definite value by the electric current I of of variable resistor Rof.In this implements, variable resistor Rof comprises resistance Ra, Rb and Rc of three series connection, each resistance Ra, Rb and Rc are each in parallel with switch Ma, Mb and Mc, respectively control switch Ma, Mb and Mc is adjust the resistance of variable resistor Rof for signal Sa, Sb and Sc of producing according to difference DELTA V, and then the variable offset values Vof produced with difference DELTA V change is to offset the first signal Va1 generation secondary signal Va2.

Fig. 9 is that the voltage change ratio dVa1/dt of the first signal Val of the DAC24 of Fig. 7 is to the characteristic curve of the input voltage Vfb1 of digital signal processor 22, when feedback signal Vfb1 rise to be greater than critical value VH1 time, digital signal Sd is downgraded with the fastest frequency, therefore the first signal Va1 has the fastest negative voltage rate of change-dVa1/dt_max, until feedback signal Vfb1 drops to be less than critical value VH2, the voltage change ratio of the first signal Va1 just gets back to original level; Same, when feedback signal Vfb1 drop to be less than critical value VL1 time, digital signal Sd is increased with the fastest frequency, therefore the first signal Va1 has the fastest forward voltage rate of change dVa1/dt_max, until feedback signal Vfb1 rises to be greater than magnetic hysteresis critical value VL2, the pace of change of the first signal Va1 just gets back to original level.In the embodiment of Fig. 7, along with the increase of critical value number of setting, the characteristic curve of Fig. 9 will level off to the characteristic curve of Fig. 6.

Figure 10 is another specific embodiment of the hybrid compensating circuit 20 of Fig. 3 A, digital signal processor 22 comprises comparator 70 and compares feedback signal Vfb1 and critical value VH1 generation comparison signal SB1, comparator 72 compares feedback signal Vfb1 and critical value VH2 and produces comparison signal SB2, comparator 74 compares feedback signal Vfb1 and reference value Vref1 and produces comparison signal SB3, comparator 76 compares feedback signal Vfb1 and critical value VL2 and produces comparison signal SB4, comparator 78 compares feedback signal Vfb1 and critical value VL1 and produces comparison signal SB5, controller 80 is according to comparison signal SB1, SB2, SB3, SB4 and SB5 is from frequency signal Clk1, Clk2, Clk3, one of them be selected as frequency Clk to up-down counter 44 in Clk4 and Clk5, when feedback signal Vfb1 is greater than maximum critical value VH1 or is less than minimum critical value VL1, the frequency signal Clk1 that controller 80 selects frequency the highest is to up-down counter 44, up-down counter 44 samples comparison signal SB3 in response to frequency signal Clk, and increase or downgrade digital signal Sd position according to sampling result, when feedback signal Vfb1 is greater than maximum critical value VH1 or is less than minimum critical value VL1, digital signal Sd is downgraded minimum value in response to comparison signal SB1 or SB5 or increases to maximum to strengthen the torsion rate of the 3rd signal Vcomp by up-down counter 44 immediately or with maximum again and again, oscillator 40 provides the frequency signal Clk1 with frequency f, frequency eliminator 82 pairs of frequency signal Clk1 frequency eliminations produce the frequency signal Clk2 with frequency f/2, frequency eliminator 84 pairs of frequency signal Clk2 frequency eliminations produce the frequency signal Clk3 with frequency f/4, frequency eliminator 86 pairs of frequency signal Clk3 frequency eliminations produce the frequency signal Clk4 with frequency f/8, frequency eliminator 88 pairs of frequency signal Clk4 frequency eliminations produce the frequency signal Clk5 with frequency f/16.In this hybrid compensating circuit, the voltage change ratio dVa1/dt of the first signal Va1 of DAC24 to the characteristic curve of the input voltage Vfb1 of digital signal processor 22 as shown in Figure 9.

The operational amplifier 90 that the LPF28 of Figure 10 comprises low frequency range has inverting input and receives secondary signal Va2 from skew injector 26, and non-inverting input connects the output Vcomp of LPF28, resistance R5 and building-out capacitor C3 is connected between the output of operational amplifier 90 and the output Vcomp of LPF28, in order to stablize the 3rd signal Vcomp, transistor M5 is connected between the output Vcomp of power end Vcc and LPF28, the output of the grid concatenation operation amplifier 90 of transistor M5, between the output Vcomp that resistance R6 is connected to LPF28 and ground end GND.

It should be noted that: although Fig. 4,7,10 are hybrid compensating circuit 20 according to Fig. 3 A and citing illustrates several specific embodiment, but obviously the hybrid compensating circuit 20a-20g shown in Fig. 3 B-3H also can use Fig. 4,7, circuit element in 10 is formed, therefore the circuit of Fig. 3 B-3H also can specifically be implemented certainly, and its details repeats no more.

Figure 11 shows effect of the present invention, the output voltage Vo of the power supply changeover device using the gm type simulated formula compensating circuit 14 of Fig. 2 to produce and signal Vcomp is respectively as shown in waveform 92 and 96, the output voltage Vo of the power supply changeover device using hybrid compensating circuit 20 of the present invention to produce and the 3rd signal Vcomp is respectively as shown in waveform 94 and 98, it is almost identical with using the effect of gm type simulated formula compensating circuit 14, and when the load instantaneous shown in time t1 occurs, also good transient response is had, therefore hybrid compensating circuit 20 can replace traditional analog compensating circuit 14 really.Hybrid compensating circuit 20 can reduce the frequency of frequency signal Clk to reach the effect of bulky capacitor C1 and C2 stabilization signal Vcomp in analog compensating circuit 14, therefore hybrid compensating circuit 20 is without the need to using bulky capacitor C1 and C2, can be incorporated into easily in control IC to reduce pin count.Hybrid compensating circuit 20 is hybrid analog-digital simulation circuit and digital circuit, therefore relative to digital compensating circuit, hybrid compensating circuit 20 is comparatively simple, therefore takies less chip area, and without the need to using complicated DSP algorithm, can simplified design and reducing costs.

Figure 12 A illustrates the hybrid compensating circuit 120 of another embodiment of the present invention; Figure 12 B-12G shows the hybrid compensating circuit 120a-120f of the other several embodiment of the present invention, and these circuit are the versions illustrating hybrid compensating circuit 120.

With reference to Figure 12 A, hybrid compensating circuit 120 comprises digital signal processor 122, adder 123, digital analog converter (DAC) 124, digimigration injector 126 and digital filter 128, wherein digital signal processor 122 can be considered first limit generator/compensator, in order to provide the first limit, digimigration injector 126 can be considered generator/compensator at zero point, in order to provide zero point, digital filter 128 can be considered second limit generator/compensator, in order to provide the second limit.The present embodiment and not existing together of Fig. 3 A embodiment comprise: zero point generator/compensator and the second limit generator/compensator implemented by digital circuit, and be arranged on the front of DAC124.But, the present embodiment is only citing; Zero point generator/compensator and the second limit generator/compensator must all do not implemented by digital circuit, and can only to be implemented by one digital circuit, such as but not limited to changing second limit generator/compensator into simulation low-pass filter.As shown in Figure 12 B, wherein the digital filter 128 of Figure 12 A is changed as LPF129.

Get back to Figure 12 A, digital signal processor 122 produces digital signal Sd according to reference value Vref1 and the feedback signal Vfb1 relevant with power supply changeover device output voltage.Another output signal Sfd that digimigration injector 126 exports according to digital signal processor 122 and produce a variable deviant, explanation after this point holds.The output signal So(variable offset values of digital filter 128 filter digital skew injector 126) and produce the deviant Sfo after filtering, the deviant Sfo after this filtration is the coherent signal of output signal So.Digital signal Sd is added with the deviant Sfo after filtration and produces digital signal Sd1 by adder 123, and digital signal Sd1 is converted to signal Vcomp by DAC124.

It should be noted that: according to the present invention, definitely must not produce/compensate two limits and a zero point that is the pole and zero number that produces/compensate can change.Such as, in some applications, a limit or a limit and a zero point or two limits can only be produced/compensate.When only needing to produce/compensate a limit and a zero point, can omit digital filter 128, this will become the circuit of Figure 12 C.When only needing to produce/compensate two limits, can omit adder 123 and digimigration injector 126, this will become the circuit of Figure 12 D.In addition please note that the position of digital filter 128 is not limited to shown in Figure 12 A; Such as, digital filter 128 can position at the rear of adder 123, as shown in figure 12e (in this example, signal Sfd1 is the signal of gained after signal Sd1 filters, and therefore signal Sfd1 can be considered the coherent signal of signal Sd1).

Except above-mentioned arrangement, certainly, the addition of all digital signals, also be added again after can being all converted to analog signal, such as but not limited to such as shown in Figure 12 F and 12G, be added again after the output signal So of the output signal Sd of digital signal processor 122 and digimigration injector 126 is changed to analog signal with DAC124,124a respectively; The difference of Figure 12 F and 12G is the position (in Figure 12 F embodiment, the output signal of LPF129 is the filtered signal of DAC124 output signal, can be considered the coherent signal that DAC124 outputs signal) of LPF129.

Figure 13 shows a specific embodiment of digital signal processor 122.As shown in the figure, in the present embodiment, digital signal processor 122 comprises one and successively asks nearly buffer (SAR, Successive Approximation Register) analog-digital converter (ADC, Analog toDigital Converter) 132, be called for short SAR-ADC, and a lifting counting circuit 134.SAR-ADC132 produces lifting signal U/D according to feedback signal Vfb1 and reference value Vref1.Lifting signal U/D controls lifting counting circuit 134 and rises accordingly to make the output signal (i.e. digital signal Sd) of lifting counting circuit 134 or decline.Lifting counting circuit 134 operates according to frequency signal CLK.In the embodiment of Figure 12 A-12C and 12E, advantageously but not necessarily, the frequency of control frequency signal CLK optionally feedback by digimigration injector 126, such as, can produce frequency signal CLK by digimigration injector 126; Or produce frequency signal CLK by the oscillator (not shown) of in digital signal processor 122, and send signal to control this oscillator by digimigration injector 126.

SAR-ADC132 produces an output signal Sfb in addition.Output signal Sfb is the digital signal corresponding to feedback signal Vfb1, or corresponds to feedback signal Vfb1 and reference value Vr _ethe digital signal of the difference between f1, describes in detail after this point holds.

Figure 14 A-14D shows several specific embodiments of SAR-ADC132.In the embodiment of Figure 14 A, reference value Vref1 is digital signal and SAR-ADC132 comprises comparator 144, controller and digital generator 146 and DAC148.The simulation feedback signal that feedback signal Vfb1 and DAC148 produces by comparator 144 is compared; In response to the output signal of comparator 144, controller and digital generator 146 produce the digital coding (N is positive integer) of a N position, and are sent to DAC148, and the simulation feedback signal that DAC148 produces corresponds to this N position digital coding.The N position digital coding that mode produces according to this is a digital signal being relevant to feedback signal Vfb1 convergence gradually, and therefore circuit is called SAR-ADC.Controller and digital generator 146 separately produce a digital signal Sfb, this digital signal Sfb can be identical or different signal with aforementioned N position digital coding, that is digital signal Sfb can be N position or other any digit, and identical or different presentation format can be adopted with this N position digital coding.Wherein in an embodiment, digital signal Sfb also corresponds to feedback signal Vfb1, or can be considered the digital representation of feedback signal Vfb1.By the feedback loop that comparator 144, controller and digital generator 146 and DAC148 are formed, digital signal Sfb can convergence and Precise Representation feedback signal Vfb1 in digital form gradually.In addition, controller and digital generator 146 separately receive reference value Vref1, and produce lifting signal U/D according to the comparative result between feedback signal Vfb1 and reference value Vref1.In detail, because reference value Vref1 is digital signal, and N position digital coding and digital signal Sfb are all the digital representation of feedback signal Vfb1, therefore above-mentioned " comparing between feedback signal Vfb1 with reference value Vref1 " can compare in a digital manner with reference to any one of value Vref1 and N position digital coding or digital signal Sfb, such as subtract each other.When feedback signal Vfb1 is greater than reference value Vref1, that is, when N position digital coding or digital signal Sfb are greater than reference value Vref1, lifting signal U/D instruction lifting counting circuit 134 increases digital signal Sd(such as increases numeral 1).When feedback signal Vfb1 is less than reference value Vref1, that is, when N position digital coding or digital signal Sfb are less than reference value Vref1, lifting signal U/D instruction lifting counting circuit 134 falls low level signal Sd(and such as reduces numeral 1).

In another embodiment, digital signal Sfb corresponds to the difference of feedback signal Vfb1 and reference value Vref1, and can be considered the digital representation of the difference of feedback signal Vfb1 and reference value Vref1.Similarly, because reference value Vref1 is digital signal, and N position digital coding is the digital representation of feedback signal Vfb1, therefore above-mentioned " difference between feedback signal Vfb1 with reference value Vref1 " can compare with N position digital coding in a digital manner with reference to value Vref1, such as, subtract each other.Or digital signal Sfb can be a digital coding of this difference.The other parts of circuit are similar to the embodiment of aforementioned " digital signal Sfb corresponds to feedback signal Vfb1 ".

In Figure 14 B embodiment, reference value Vref1 is digital signal, and inputs DAC148 as initial number.Similarly, digital signal Sfb can correspond to feedback signal Vfb1 or correspond to the difference (that is, digital signal Sfb can be the digital representation of the digital representation of feedback signal Vfb1 or the difference of feedback signal Vfb1 and reference value Vref1) of feedback signal Vfb1 and reference value Vref1.The other parts of circuit are similar to Figure 14 A embodiment.

In Figure 14 C embodiment, reference value Vref1 is analog signal, and SAR-ADC132 comprises error amplifier 141, comparator 142, controller and digital generator 146 and DAC148.Error amplifier 141 compares feedback signal Vfb1 and reference value Vref1 and produces error and amplifies signal.Comparator 142, controller and digital generator 146 and DAC148 form SAR, and its mode of operation is similar in appearance to the embodiment of Figure 14 A, but digital signal Sfb is the digital representation of the difference of feedback signal Vfb1 and reference value Vref1.

In Figure 14 D embodiment, reference value Vref1 is analog signal, and SAR-ADC132 comprises two comparators 143 and 144, controller and digital generator 146 and DAC148.The simulation feedback signal that DAC148 produces by comparator 143 compares with reference value Vref1, and by comparative result input control device and digital generator 146.The present embodiment is similar to the embodiment of Figure 14 A, but controller and digital generator 146 receive the output signal of comparator 143 and non-numeric reference value Vref1.

Figure 15 illustrates the embodiment of lifting counting circuit 134.Lifting counting circuit 134 comprises controller 152 and up-down counter 154.Controller 152 is controlled by lifting signal U/D, and operates in the frequency that frequency signal CLK determines.Relation between controller 152 to up-down counter 154 and the relation between controller 42 to up-down counter 44 similar, be not therefore repeated herein this.

Figure 16 A illustrates an embodiment of digimigration injector 126.As previously mentioned, the effect of digimigration injector 126 is to provide a variable offset values, and using as generator/compensator at zero point, and this variable offset values is relevant to the difference of feedback signal Vfb1 and reference value Vref1.According to more than, digimigration injector 126 can be implemented in various manners, as long as one can be produced correspond to the numeral of α (Vfb1-Vref1) or the digital representation of coding or generation α (Vfb1-Vref1), wherein α is arithmetic number, represent a proportionality constant, this proportionality constant corresponds in the analog circuit representing Fig. 2, and the transduction coefficient of transduction amplifier 16 is multiplied by the resistance of resistance R3.As shown in Figure 16 A, wherein in an embodiment, digimigration injector 126 can be implemented as digital multiplier, digital signal Sfb is multiplied by factor-beta and produces variable offset values So, and wherein β is arithmetic number.(or, if factor-beta be less than 1 arithmetic number, then digital multiplier also can be digital divider, by digital signal Sfb divided by (1/ β).) in the present embodiment digital signal Sfb correspond to the difference of feedback signal Vfb1 and reference value Vref1, or be the digital representation of difference of feedback signal Vfb1 and reference value Vref1.Factor-beta can come given by the designer of hybrid compensating circuit.The variable offset values So that digital multiplier exports equals β Sfb, corresponding to α (Vfb1-Vref1).

In Figure 16 B embodiment, digital signal Sfb corresponds to feedback signal Vfb1 or be the digital representation of feedback signal Vfb1, and digimigration injector 126 comprises addition/subtraction device 162 and digital multiplier 164.Addition/subtraction device 162 deducts digital signal Sref1(or adds the negative value of digital signal Sref1 in digital signal Sfb), wherein digital signal Sref1 corresponds to reference value Vref1, or is the digital representation of reference value Vref1.The difference of digital signal Sfb and digital signal Sref1 is multiplied by factor-beta by digital multiplier 164.The variable offset values So exported by digital multiplier 164 equals β (Sfb-Sref1), corresponding to α (Vfb1-Vref1).

Except above embodiment, digimigration injector 126 also has other execution mode multiple; Such as, digimigration injector 126 can be embodied as an internal memory, store multiple deviant in advance within it, and digital signal Sfb can represent the address of this internal memory or the address in order to determine this internal memory, as shown in figure 16 c in multiple address.Digital signal Sfb may correspond in feedback signal Vfb1 or the difference corresponding to feedback signal Vfb1 and reference value Vref1.

Other three embodiments of Figure 16 D-16F display word offset injector 126.With reference to Figure 16 D, digimigration injector 126 comprises digital multiplier 164 and frequency eliminating circuit 166 in the present embodiment.The mode of operation of digital multiplier 164 is similar to Figure 16 A embodiment.Frequency eliminating circuit 166 receiving frequency signals CLK_132, this frequency signal be SAR-ADC132 operation frequency (such as, this frequency signal be in SAR-ADC132 DAC148 operate institute according to frequency).Frequency signal CLK_132 frequency elimination is produced the frequency signal CLK after frequency elimination by frequency eliminating circuit 166.The value of the frequency signal CLK viewable numbers signal Sfb produced and have different frequency f 1, f2 ...That is the frequency of frequency signal CLK is determined by digital signal Sfb.Frequency signal CLK is transferred into lifting counting circuit 134 (with reference to Figure 12 A-12C, Figure 12 E, Figure 13 and Figure 15), and controller 152 is operated according to frequency signal CLK.Mode according to this, digimigration injector 126 can the frequency of operation of modulation statoscope number circuit 134, and reaches the effect that the electric capacity C1 be similar in Fig. 2 provides.

Figure 16 E and Figure 16 F corresponds respectively to Figure 16 B and Figure 16 C, and difference is that digimigration injector 126 separately comprises frequency eliminating circuit 166 to produce the frequency signal CLK after frequency elimination.Frequency eliminating circuit 166 mode of operation is similar to the embodiment of Figure 16 D.Please note in Figure 16 E embodiment, except according to digital signal Sfb by except frequency signal CLK_132 frequency elimination, another kind of mode is (not shown, to can refer to Figure 16 H), and frequency eliminating circuit 166 also can come frequency signal CLK_132 frequency elimination according to the output of addition/subtraction device 162.Below in this mode, because digital signal Sref1 corresponds to reference value Vref1, reference value Vref1 is known signal, and therefore the frequency of frequency signal CLK remains and determined by digital signal Sfb.

Other three embodiments of Figure 16 G-16I display word offset injector 126.With reference to Figure 16 G, digimigration injector 126 comprises digital multiplier 164 and DAC168 in the present embodiment.The mode of operation of digital multiplier 164 is similar to Figure 16 A embodiment.Digital signal Sfb is converted to analog signal by DAC168, can be curtage signal.In addition, digital signal processor 122 also comprises an oscillator (OSC) 136, can be Current Control or voltage-controlled oscillator, and what produce depending on DAC168 is curtage signal.The signal controlling OSC136 that DAC168 produces is with the frequency of the frequency signal CLK determining OSC136 and produce.Frequency signal CLK for lifting counting circuit 134 operate institute according to frequency.Mode according to this, digimigration injector 126 also can the frequency of operation of modulation statoscope number circuit 134, and reaches the effect that the electric capacity C1 be similar in Fig. 2 provides.

Figure 16 H and Figure 16 I corresponds respectively to Figure 16 B and Figure 16 C, and difference is that digimigration injector 126 separately comprises DAC168 and digital signal processor 122 also comprises OSC136.The mode of operation of DAC168 with OSC136 is similar to the embodiment of Figure 16 G.Please note that the output of addition/subtraction device 162 is converted to analog signal by DAC168 in Figure 16 H embodiment, with control OSC136.In another embodiment, digital signal Sfb can be converted to analog signal by DAC168, with control OSC136.

Figure 17 A and 17B shows two embodiments of digital filter 128.With reference to Figure 17 A, in a better simply form, digital filter 128 can be implemented as a D flip-flop.For the embodiment of Figure 12 E, wherein digital filter 128 is connected between adder 123 and DAC124, produces the digital signal Sfd1 after filtration in order to receiving digital signals Sd1, and in this embodiment, digital signal Sd1 can input in this D flip-flop.D flip-flop operates according to frequency signal CLK_128, the frequency of frequency signal CLK_128 operates the frequency of institute's foundation lower than frequency signal CLK_132(SAR-ADC132), and be preferably the frequency more operating institute's foundation lower than frequency signal CLK(lifting counting circuit 134).It should be noted that the actual ratio of numeral 128 and 132 and frequency has nothing to do; It is which circuit uses this frequency signal that the object of these digital notes just conveniently contrasts.Because the frequency of operation of D flip-flop is comparatively slow, the effect that the electric capacity C1 be similar in Fig. 2 provides therefore can be provided.

With reference to Figure 17 B, in a more complicated form, digital filter 128 can be implemented as a rolling average circuit.Also be for the embodiment of Figure 12 E, rolling average circuit receiving digital signals Sd1 also calculates according to rolling average and produces the digital signal Sfd1 after filtering.Rolling average account form has many kinds, all can use, lift wherein one such as under:

Sfd1 _t=sum _t/ n=(sum _(t-1)-Sfd1 _(t-1)+ Sfd _t)/n formula 3

Wherein Sfd1 _twith Sfd1 _(t-1)be respectively the digital signal Sfd1 of current time point and the digital signal Sfd1 of last time point; Sfd _tfor the digital signal Sfd of current time point; Sum _twith Sum _(t-1)be respectively the Cumulate Sum of current time point and the Cumulate Sum of last time point; N is divisor, is generally positive integer, to determine smoothness and the velocity of approach of rolling average.

Although Figure 17 A and Figure 17 B is for the embodiment of Figure 12 E, the circuit of obvious Figure 17 A and Figure 17 B also can be applicable to other embodiment.

Below for preferred embodiment, the present invention is described, just the above, be only and make those skilled in the art be easy to understand content of the present invention, be not used for limiting interest field of the present invention.Under same spirit of the present invention, those skilled in the art can think and various equivalence change.Such as, the positive and negative terminal of error amplifier, transduction amplifier or comparator can exchange, the meaning of digital signal high-low-position standard can be exchanged, and relevant circuit can make corresponding amendment; The circuit directly connected in embodiment or element, can plant wherein other circuit or element of not affecting signal major significance, etc.Scope of the present invention should contain above-mentioned and other all equivalence change.

Claims

1. a hybrid compensating circuit for power supply changeover device, is characterized in that, comprising:

Digital signal processor, in order to provide one first limit, this digital signal processor produces digital signal according to feedback signal and reference value, and wherein this feedback signal is relevant to the output voltage of this power supply changeover device; And

Digital analog converter, couples this digital signal processor, this digital signal is converted to the first signal of simulation.

2. hybrid compensating circuit as claimed in claim 1, wherein, also comprise: skew injector, couple this digital analog converter, in order to provide a zero point, this skew injector provides variable offset values to produce secondary signal to offset this first signal, and wherein this variable offset values is determined by the difference between this feedback signal and this reference value.

3. hybrid compensating circuit as claimed in claim 1, wherein, also comprises: low pass filter, couples this digital analog converter, and in order to provide one second limit, the radio-frequency component that this low pass filter filters this first signal produces secondary signal.

4. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Skew injector, couples this digital analog converter, and provide variable offset values to produce secondary signal to offset this first signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; And

Low pass filter, couples this skew injector, and the radio-frequency component of this secondary signal of filtering produces the 3rd signal and stablizes this output voltage for this power supply changeover device.

5. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Low pass filter, couples this digital analog converter, and the radio-frequency component of this first signal of filtering produces secondary signal; And

Skew injector, couples this low pass filter, and provide variable offset values to stablize this output voltage to offset this secondary signal generation the 3rd signal for this power supply changeover device, wherein this variable offset values is determined by the difference between this feedback signal and this reference value.

6. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Skew injector, couples this digital signal processor, and provide variable offset values to produce secondary signal to offset this digital signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; And

Adder, is added this first signal with this secondary signal, produces the 3rd signal and stablizes this output voltage for this power supply changeover device.

7. hybrid compensating circuit as claimed in claim 6, wherein, also comprises low pass filter, couples the output of this adder.

8. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Skew injector, couples this digital signal processor, and provide variable offset values to produce secondary signal to offset this digital signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value;

Low pass filter, couples this skew injector, and the radio-frequency component of this secondary signal of filtering produces the 3rd signal; And

Adder, by this first signal and the 3rd signal plus, produces the 4th signal and stablizes this output voltage for this power supply changeover device.

9. the hybrid compensating circuit of any one as described in claim 1 to 8, wherein, this digital signal processor comprises:

Comparator, compares this feedback signal and this reference value produces comparison signal;

Controller, couples this comparator, and respective frequencies signal samples this comparison signal to determine control signal; And

Up-down counter, couples this controller, provides this digital signal and samples this control signal to adjust this digital signal according to this frequency signal.

10. hybrid compensating circuit as claimed in claim 9, wherein, also comprises:

Second comparator, couples this controller, produces the second comparison signal to this controller when this feedback signal is greater than the first critical value; And

3rd comparator, couples this controller, produces the 3rd comparison signal to this controller when this feedback signal is less than the second critical value;

Wherein, this controller, according to this second comparison signal and the 3rd comparison signal, makes this digital signal be cut to minimum value or increase maximum.

11. hybrid compensating circuits as claimed in claim 9, wherein, also comprise:

Oscillator, couples this controller, provides this frequency signal; And

Computing transduction amplifier, couples this oscillator, and the difference of amplifying between this feedback signal and this reference value produces frequency adjusted signal to this oscillator, to adjust the frequency of this frequency signal;

Wherein, when the difference between this feedback signal and this reference value increases, the frequency of this frequency signal increases.

12. hybrid compensating circuits as claimed in claim 11, wherein, also comprise:

Second comparator, couples this oscillator, produces the second comparison signal to this oscillator when this feedback signal is greater than the first critical value; And

3rd comparator, couples this oscillator, produces the 3rd comparison signal to this oscillator when this feedback signal is less than the second critical value;

Wherein, this oscillator is according to this second comparison signal and the 3rd comparison signal, and the frequency increasing this frequency signal, to maximum, increases to maximum with peak frequency to make this digital signal or downgrades minimum value.

13. as described in claim 1 to 8 the hybrid compensating circuit of any one, wherein, this digital signal processor comprises:

Comparator, the signal comparing its two input produces comparison signal, and wherein the first input end of this two input receives this feedback signal;

Oscillator, provides frequency signal, and adjusts the frequency of this frequency signal according to frequency adjusted signal;

Multiplexer, couples this comparator, in each cycle of this frequency signal, sequentially multiple critical value and this reference value is fed to the second input of this two input;

Controller, couples this comparator and oscillator, determines control signal and this frequency adjusted signal according to this comparison signal;

Up-down counter, couples this controller and oscillator, provides this digital signal and samples this control signal to adjust this digital signal according to this frequency signal; And

Pulse generator, couples this oscillator and multiplexer, to producing multiple pulse signal to this multiplexer, with the second input making this multiplexer sequentially the plurality of critical value and this reference value are fed to this comparator by frequency signal.

14. hybrid compensating circuits as claimed in claim 13, wherein, the frequency of this frequency signal, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, is adjusted to peak.

15. hybrid compensating circuits as claimed in claim 13, wherein, this digital signal, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, is cut to minimum value or increases maximum by this up-down counter immediately or with peak frequency.

16. as described in claim 1 to 8 the hybrid compensating circuit of any one, wherein, this digital signal processor comprises:

First comparator, compares generation first comparison signal by this feedback signal with this reference value;

Multiple second comparator, compares this feedback signal with multiple critical value respectively and produces multiple second comparison signal;

Controller, couples this first comparator and the plurality of second comparator, selects one of them to export according to this first comparison signal and the plurality of second comparison signal from multiple frequency signal; And

Up-down counter, couples this first comparator and this controller, provides this digital signal, samples, and adjust this digital signal according to sampling result according to the frequency signal that this controller exports to this first comparison signal.

17. hybrid compensating circuits as claimed in claim 16, wherein, this controller, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, selects the frequency signal that frequency is the highest.

18. hybrid compensating circuits as claimed in claim 16, wherein, this digital signal, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, is cut to minimum value or increases maximum by this up-down counter immediately or with peak frequency.

19. hybrid compensating circuits as claimed in claim 4, wherein, this skew injector comprises:

Resistance, has first end and couple this digital analog converter, and the second end couples this low pass filter, provide this variable offset values;

First current source, provides the electric current changed with this difference;

First switch, is connected in series to this first end with this first current source, is controlled by the first control signal;

Second current source, provides the electric current changed with this difference;

Second switch, is connected in series to this first end with this second current source, is controlled by the second control signal;

3rd current source, provides the electric current changed with this difference;

3rd switch, is connected in series to this second end with the 3rd current source, is controlled by this second control signal;

4th current source, provides the electric current changed with this difference; And

4th switch, is connected in series to this second end with the 4th current source, is controlled by this first control signal.

20. hybrid compensating circuits as claimed in claim 4, wherein, this skew injector comprises:

Variable resistor, has first end and couple this digital analog converter, and the second end couples this low pass filter, provide this variable offset values, and wherein this variable-resistance resistance changes with this difference;

First current source, provides and determines electric current;

Second current source, provides and determines electric current;

3rd current source, provides and determines electric current;

4th current source, provides and determines electric current; And

21. hybrid compensating circuits as claimed in claim 1, wherein, this low pass filter comprises the RC filter be made up of resistance and electric capacity.

22. hybrid compensating circuits as claimed in claim 1, wherein, this low pass filter comprises:

The operational amplifier of low frequency range, has first input end and receives secondary signal that this skew injector exports and the second input couples the output of this low pass filter; And

Building-out capacitor.

The hybrid compensating circuit of 23. 1 kinds of power supply changeover devices, is characterized in that, comprising:

Digital signal processor, produces first and second digital signal according to output voltage feedback signal and reference value, and wherein this output voltage feedback signal is relevant to the output voltage of this power supply changeover device;

Digimigration injector, couples this digital signal processor, to produce variable offset values according to this second digital signal;

Adder, is added this first digital signal with this variable offset values, maybe this first digital signal is added with the coherent signal of this variable offset values; And

Digital analog converter, couples this adder, and the coherent signal of the output of this adder or the output of this adder is converted to analog signal.

24. hybrid compensating circuits as claimed in claim 23, wherein, also comprise: low pass filter, couple this digital analog converter, in order to the radio-frequency component of this analog signal of filtering.

25. hybrid compensating circuits as claimed in claim 23, wherein, also comprise: digital filter, are coupled between this digimigration injector and this adder, produce the coherent signal of this variable offset values in order to filter this variable offset values.

26. hybrid compensating circuits as claimed in claim 23, wherein, also comprise: digital filter, are coupled between this adder and this digital analog converter, in order to filter the output of this adder and to produce the coherent signal of the output of this adder.

27. hybrid compensating circuits as claimed in claim 23, wherein, the back coupling of this digimigration injector controls a frequency signal of this digital signal processor.

The hybrid compensating circuit of 28. 1 kinds of power supply changeover devices, is characterized in that, comprising:

First digital analog converter, couples this digital signal processor, and this first digital signal is converted to the first analog signal;

Second digital analog converter, couples this digimigration injector, this variable offset values is converted to the second analog signal; And

Adder, is added this first analog signal with this second analog signal, is maybe added with the second analog signal by the coherent signal of this first analog signal.

29. hybrid compensating circuits as claimed in claim 28, wherein, also comprise: low pass filter, are coupled between this first digital analog converter and this adder or are coupled to the output of this adder.

The hybrid compensating circuit of 30. 1 kinds of power supply changeover devices, is characterized in that, comprising:

Digital signal processor, produces the first digital signal according to output voltage feedback signal and reference value, and wherein this voltage feedback signal is relevant to the output voltage of this power supply changeover device;

Digital filter, couples this digital signal processor, to filter this first digital signal; And

Digital analog converter, couples this digital filter, and the output of this digital filter is converted to analog signal.

31. as described in claim 23 to 30 the hybrid compensating circuit of any one, wherein, this digital signal processor comprises:

Successively ask nearly buffer memory analogue-digital converter, produce a lifting signal according to this output voltage feedback signal and this reference value; And

Lifting counting circuit, wherein the output signal of this lifting counting circuit is controlled by this lifting signal and rises accordingly or decline.

32. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to comprise:

Comparator, successively asks this output voltage feedback signal and compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and produces an output signal;

Controller and digital generator, couple this comparator, and produce the digital coding of a N position in response to the output signal of this comparator, and wherein N is positive integer, and produce this lifting signal; And

Digital analog converter, couple this controller and digital generator, and produce this according to the digital coding of this N position and successively ask nearly buffer memory analogue-digital converter internal simulation feedback signal, thus, make this N position digital coding be relevant to this output voltage feedback signal and convergence gradually.

33. hybrid compensating circuits as claimed in claim 32, wherein, this reference value inputs this controller and digital generator, or inputs this digital analog converter, as initial number.

34. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to comprise:

Error amplifier, compares this output voltage feedback signal with this reference value and produces an error amplification signal;

Comparator, successively asks this error amplification signal and compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and produces an output signal;

35. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to comprise:

First comparator, successively asks this output voltage feedback signal and and produces one first compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and output signal;

Second comparator, successively asks this reference value and this and produces one second compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and output signal;

Controller and digital generator, couple this first and second comparator, and produce the digital coding of a N position in response to this first and second output signal, and wherein N is positive integer, and produces this lifting signal; And

36. as described in claim 32 to 35 the hybrid compensating circuit of any one, wherein, this controller and digital generator separately produce this second digital signal, and this second digital signal corresponds to this output voltage feedback signal or corresponds to the difference of this output voltage feedback signal and this reference value.

37. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector produces numeral or the coding that corresponds to α (Vfb1-Vref1), and wherein α is arithmetic number, Vfb1 is this output voltage feedback signal, and Vref1 is this reference value.

38. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector comprises: digital multiplier, and this second digital signal is multiplied by Graph One factor β and produces this variable offset values, wherein β is arithmetic number.

39. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector comprises:

Addition/subtraction device, deducts corresponding to the three digital signal of this reference value and obtains difference in this second digital signal; And

Digital multiplier, is multiplied by Graph One factor β by this difference and produces this variable offset values, and wherein β is arithmetic number.

40. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector comprises: an internal memory, there is multiple address, and store multiple deviant in advance in the plurality of address, and this second digital signal represents the address of this internal memory or the address in order to determine this internal memory.

41. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal, and this lifting counting circuit operates according to a second frequency signal, and this digimigration injector comprises:

Digital multiplier, this second digital signal is multiplied by Graph One factor β and produces this variable offset values, wherein β is arithmetic number; And

Frequency eliminating circuit, according to this second digital signal by this first frequency signal frequency elimination, to obtain this second frequency signal.

42. hybrid compensating circuits as claimed in claim 31, wherein this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal, and this lifting counting circuit operates according to a second frequency signal, and this digimigration injector comprises:

Addition/subtraction device, deducts corresponding to the three digital signal of this reference value and obtains difference in this second digital signal;

Digital multiplier, is multiplied by Graph One factor β by this difference and produces this variable offset values, and wherein β is arithmetic number; And

Frequency eliminating circuit, according to this second digital signal or this three digital signal by this first frequency signal frequency elimination, to obtain this second frequency signal.

43. hybrid compensating circuits as claimed in claim 31, wherein this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal, and this lifting counting circuit operates according to a second frequency signal, and this digimigration injector comprises:

One internal memory, has multiple address, and stores multiple deviant in advance in the plurality of address, and this second digital signal represents the address of this internal memory or the address in order to determine this internal memory; And

44. hybrid compensating circuits as claimed in claim 27, wherein, this digital signal processor also comprises an oscillator to produce this frequency signal, and this digimigration injector comprises:

D/A conversion circuit, is converted to analog signal by this second digital signal, to control the frequency of this oscillator.

45. hybrid compensating circuits as claimed in claim 27, wherein, this digital signal processor also comprises an oscillator to produce this frequency signal, and this digimigration injector comprises:

D/A conversion circuit, is converted to analog signal by this second digital signal or this three digital signal, to control the frequency of this oscillator.

46. hybrid compensating circuits as claimed in claim 27, wherein, this digital signal processor also comprises an oscillator to produce this frequency signal, and this digimigration injector comprises:

47. hybrid compensating circuits as described in claim 25,26 or 30, wherein, this digital filter comprises a D flip-flop.

48. hybrid compensating circuits as claimed in claim 47, wherein, this digital signal processor comprises:

Successively ask nearly buffer memory analogue-digital converter, produce a lifting signal according to this output voltage feedback signal and this reference value, this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal; And

Lifting counting circuit, wherein the output signal of this lifting counting circuit is controlled by this lifting signal and rises accordingly or decline, and this lifting counting circuit operates according to a second frequency signal;

And this D flip-flop operates according to one the 3rd frequency signal, the frequency of this 3rd frequency signal is lower than this first and second frequency signal.

49. as described in claim 25,26 or 30 the hybrid compensating circuit of any one, wherein, this digital filter comprises a rolling average circuit.