CN111490783B - Delta-sigma analog-to-digital converter - Google Patents
Delta-sigma analog-to-digital converter Download PDFInfo
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- CN111490783B CN111490783B CN201910071250.7A CN201910071250A CN111490783B CN 111490783 B CN111490783 B CN 111490783B CN 201910071250 A CN201910071250 A CN 201910071250A CN 111490783 B CN111490783 B CN 111490783B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1023—Offset correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
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Abstract
The invention provides a delta-sigma analog-to-digital converter, comprising: a subtractor for subtracting the feedback signal from the analog input signal; a loop filter for processing the output signal of the subtractor to produce a filtered signal; a signal comparison circuit selectively operable in an offset detection mode or a signal comparison mode, wherein the signal comparison circuit generates an error signal independent of the relative magnitudes of the filtered signal and the reference signal when operating in the offset detection mode and generates a comparison signal corresponding to the relative magnitudes of the filtered signal and the reference signal when operating in the signal comparison mode; an offset correction circuit for correcting an offset of the signal comparison circuit and controlling the signal comparison circuit to alternately switch between an offset detection mode and a signal comparison mode; and the digital-to-analog converter is used for generating a feedback signal according to the comparison signal.
Description
Technical Field
The present invention relates to analog-to-digital converters (ADCs), and more particularly, to a sigma-delta ADC (ADC) for alternately performing signal conversion and comparator offset correction while reducing idle tone generation.
Background
Although the application of the delta-sigma adc is quite extensive, the internal comparator often has an offset (offset) due to process variation (process deviation). Without correcting the offset of the comparator of the delta-sigma adc, the signal-to-Noise (SNR) and total harmonic Distortion plus Noise (THDN) related performance of the delta-sigma adc are seriously affected.
In addition, the circuit characteristics of the conventional delta-sigma analog-to-digital converter are also prone to generate idle tones (idle tones). The prior art usually arranges an additional jitter signal generating circuit in the delta-sigma analog-to-digital converter to suppress the generation of idle sound, but the complexity of the circuit is increased.
Disclosure of Invention
Therefore, it is an object of the present invention to reduce or eliminate the comparator offset of the delta-sigma adc and reduce idle tones by using a simplified circuit.
This specification provides an embodiment of a delta-sigma analog-to-digital converter, comprising: a subtractor arranged to subtract a feedback signal from an analogue input signal; a loop filter, coupled to the subtractor, configured to process an output signal of the subtractor to generate a filtered signal; a first signal comparison circuit, coupled to the loop filter and a first reference signal, configured to selectively operate in an offset detection mode or a signal comparison mode, wherein the first signal comparison circuit generates a first error signal independent of the relative magnitudes of the filtered signal and the first reference signal when operating in the offset detection mode, and generates a first comparison signal corresponding to the relative magnitudes of the filtered signal and the first reference signal when operating in the signal comparison mode; an offset correction circuit, coupled to the first signal comparison circuit, configured to correct an offset condition of the first signal comparison circuit according to the first error signal, and control the first signal comparison circuit to switch between the offset detection mode and the signal comparison mode alternately; and a digital-to-analog converter, coupled to the output terminal of the first signal comparison circuit and the subtractor, configured to generate the feedback signal according to the first comparison signal.
One advantage of the above embodiments is that the offset calibration circuit can effectively calibrate the signal offset of the first signal comparator circuit, thereby improving the overall performance of the delta-sigma adc.
Another advantage of the above-mentioned embodiments is that the offset correction circuit can simultaneously suppress the generation of idle tones when performing the offset correction of the first signal comparison circuit, so that an additional jitter signal generation circuit is not required, and the circuit architecture of the delta-sigma adc can be simplified.
Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.
Drawings
Fig. 1 is a simplified functional block diagram of a delta-sigma adc according to a first embodiment of the present invention.
Fig. 2 is a simplified operation timing diagram of the delta-sigma adc of fig. 1 according to the first embodiment.
Fig. 3 is a simplified functional diagram of the first embodiment of the signal comparison circuit in fig. 1.
Fig. 4 to 6 are simplified operation diagrams of the signal comparison circuit in fig. 2 operating in different modes.
Fig. 7 is a simplified operation timing diagram of the delta-sigma adc of fig. 1 according to a second embodiment.
Fig. 8 is a simplified functional diagram of a second embodiment of the signal comparison circuit in fig. 1.
Fig. 9 is a simplified functional diagram of a third embodiment of the signal comparison circuit of fig. 1.
Description of the symbols
100. Delta analog-to-digital converter (Sigma-Delta analog-to-digital converter)
110. Subtractor (subcoctor)
120. Loop filter (loop filter)
130. First signal comparing circuit (first signal comparing circuit)
132. First comparator (first comparator)
134. First signal selection circuit (first signal selection circuit)
136. First compensation circuit (first compensation circuit)
140. Second signal comparing circuit (second signal comparing circuit)
142. Second comparator (second comparator)
144. Second signal selection circuit (second signal selection circuit)
146. Second compensation circuit (second compensation circuit)
150. Offset correction circuit (offset calibration circuit)
160. Digital-to-analog converter (digital-to-analog converter)
322. First input terminal (first input terminal)
324. Second input terminal (second input terminal)
326. Third input terminal (third input terminal)
328. Fourth input terminal (four input terminal)
342. First switch circuit (first switch circuit)
344. Second switch circuit (second switch circuit)
362. Compensation capacitor (compensator)
364. First adjusting circuit (first adjusting circuit)
366. Second adjusting circuit (second adjusting circuit)
368. Third switch circuit (third switch circuit)
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.
Fig. 1 is a simplified functional block diagram of a delta-sigma adc 100 according to a first embodiment of the present invention. The delta-sigma adc 100 is configured to convert an analog input signal Sin into a corresponding digital output signal.
As shown in fig. 1, the delta-sigma adc 100 includes a subtractor 110, a loop filter 120, one or more signal comparison circuits (e.g., the exemplary first signal comparison circuit 130 and the second signal comparison circuit 140 of fig. 1), an offset correction circuit 150, and a digital-to-analog converter 160.
The subtractor 110 is coupled to the analog input signal Sin and configured to subtract a feedback signal Sfb from the analog input signal Sin.
The loop filter 120 is coupled to the subtractor 110 and configured to process an output signal of the subtractor 110 to generate a filtered signal SF.
The first signal comparing circuit 130 is coupled to the loop filter 120 and a first reference signal VR1, and is configured to selectively operate in an offset detection mode or a signal comparing mode. The first signal comparing circuit 130 generates a first error signal ERR1 independent of the relative magnitudes of the filtered signal SF and the first reference signal VR1 when operating in the offset detection mode. The first signal comparing circuit 130 generates a first comparison signal CMP1 corresponding to the relative magnitudes of the filtered signal SF and the first reference signal VR1 when operating in the signal comparing mode.
The second signal comparison circuit 140 is coupled to the loop filter 120 and a second reference signal VRn, and is also configured to selectively operate in an offset detection mode or a signal comparison mode. The second signal comparison circuit 140 generates a second error signal ERRn independent of the relative magnitudes of the filtered signal SF and the second reference signal VRn when operating in the offset detection mode. The second signal comparing circuit 140 generates a second comparison signal CMPn corresponding to the relative magnitudes of the filtered signal SF and the second reference signal VRn when operating in the signal comparing mode.
The offset calibration circuit 150 is coupled to the first signal comparison circuit 130 and the second signal comparison circuit 140, and configured to calibrate the offset of the first signal comparison circuit 130 according to the first error signal ERR1, and calibrate the offset of the second signal comparison circuit 140 according to the second error signal ERRn. Furthermore, the offset correction circuit 150 is also arranged to control the first signal comparison circuit 130 to alternately switch between the offset detection mode and the signal comparison mode, and to control the second signal comparison circuit 140 to alternately switch between the offset detection mode and the signal comparison mode.
The digital-to-analog converter 160 is coupled to the output terminal of the first signal comparing circuit 130, the output terminal of the second signal comparing circuit 140 and the subtractor 110, and configured to generate the feedback signal Sfb according to the first comparing signal CMP1 and the second comparing signal CMPn.
In practice, the subtractor 110 can be implemented by using various suitable circuits based on an operational amplifier architecture or other conventional circuits with analog signal subtraction function. The loop filter 120 may be implemented using various suitable integration circuits with noise shaping. The offset correction circuit 150 may be implemented using various suitable circuits that interpret digital signals, perform digital operations, and generate control signals. The digital-to-analog converter 160 may be implemented using any suitable conventional digital-to-analog conversion circuitry.
In addition, all signal comparison circuits in the delta-sigma adc 100 can be designed to have similar circuit architecture and operation. For example, in the embodiment of fig. 1, the first signal comparing circuit 130 includes a first comparator 132, a first signal selecting circuit 134, and a first compensating circuit 136. Similarly, the second signal comparing circuit 140 includes a second comparator 142, a second signal selecting circuit 144, and a second compensating circuit 146.
In the first signal comparing circuit 130, the first comparator 132 includes four input terminals and is configured to generate corresponding output signals according to signals of the four input terminals. The first signal selecting circuit 134 is coupled to the loop filter 120, the first comparator 132, the offset correction circuit 150, the first reference signal VR1, and a first fixed-potential signal VF1, and configured to selectively switch the signal coupled to the input terminal of the first comparator 132 according to the control of the offset correction circuit 150. The first compensation circuit 136 is coupled to the first comparator 132 and the offset correction circuit 150, and configured to compensate a signal of at least one input terminal of the first comparator 132 according to the control of the offset correction circuit 150. The first fixed-potential signal VF1 can be a common-mode voltage signal of the first comparator 132 or other reference signals with a fixed voltage value.
In the second signal comparison circuit 140, a second comparator 142 is arranged to compare signals at its inputs to generate an output signal. The second signal selection circuit 144 is coupled to the loop filter 120, the second comparator 142, the offset correction circuit 150, the second reference signal VRn, and a second constant voltage signal VFn, and configured to selectively switch the signal coupled to the input terminal of the second comparator 142 according to the control of the offset correction circuit 150. The second compensation circuit 146 is coupled to the second comparator 142 and the offset correction circuit 150, and configured to compensate a signal of at least one input terminal of the second comparator 142 according to the control of the offset correction circuit 150. The second constant voltage signal VFn may be a common mode voltage signal of the second comparator 142 or other reference signal with a constant voltage value.
In practice, the first fixed-potential signal VF1 and the second fixed-potential signal VFn may have the same voltage value or different voltage values.
Please refer to fig. 2, which illustrates a simplified operation timing diagram of the delta-sigma adc 100 of fig. 1 according to a first embodiment.
In operation, the offset calibration circuit 150 operates according to an operating clock CLK, and controls each signal comparison circuit to switch to the offset detection mode at least once and to switch to the signal comparison mode at least once every predetermined number of operating cycles of the operating clock CLK. The predetermined number may be one, two, three, or other fixed integer.
For example, as shown in fig. 2, the offset calibration circuit 150 may control the first signal comparison circuit 130 and the second signal comparison circuit 140 to switch to the offset detection mode for a period of time (e.g., a period T21) and then switch to the signal comparison mode for a period of time (e.g., a period T22) synchronously in each duty cycle of the clock CLK. In the present embodiment, the lengths of the period T21 and the period T22 are both half the duty cycle of the operation clock CLK.
In the offset detection mode, the first signal selection circuit 134 couples the input terminal of the first comparator 132 to the first fixed-potential signal VF1, so that the first comparator 132 generates the first error signal ERR1, and the second signal selection circuit 144 couples the input terminal of the second comparator 142 to the second fixed-potential signal VFn, so that the second comparator 142 generates the second error signal ERRn.
In the signal comparison mode, the first signal selection circuit 134 instead couples the input terminal of the first comparator 132 to the filtered signal SF and the first reference signal VR1 respectively, so that the first comparator 132 generates the first comparison signal CMP1, and the second signal selection circuit 144 instead couples the input terminal of the second comparator 142 to the filtered signal SF and the second reference signal VRn respectively, so that the second comparator 142 generates the second comparison signal CMPn.
The offset calibration circuit 150 can adjust the signal compensation amount of the first compensation circuit 136 according to the first error signal ERR1 to calibrate the signal offset of the first comparator 132. Similarly, the offset correction circuit 150 can adjust the signal compensation amount of the second compensation circuit 146 according to the second error signal ERRn to correct the signal offset of the second comparator 142.
As can be seen from the foregoing description, each signal comparison circuit in the delta-sigma adc 100 intermittently performs a comparison operation between the filtered signal SF and the corresponding reference signal, so as to realize the analog-to-digital conversion function of the delta-sigma adc 100.
On the other hand, each signal comparison circuit in the delta-sigma adc 100 is also intermittently switched to the offset detection mode, so that the offset correction circuit 150 can determine the signal offset of each comparator according to the error signal output by each comparator in the offset detection mode, and control the compensation circuit to correct the signal offset of the corresponding comparator.
The signal comparison circuits in the delta-sigma adc 100 collectively function as a quantizer (quantizer), and the comparison signals generated by the signal comparison circuits (e.g., the first comparison signal CMP1 and the second comparison signal CMPn) collectively form a digital output signal of the delta-sigma adc 100, which can be further processed by a subsequent digital processing circuit (not shown).
The loop filter 120 operates to noise shape the quantization noise (noise) of the delta-sigma adc 100, and to shift the quantization noise to a high frequency band that is less perceptible to the human ear, thereby improving the quality of the output audio.
The length of time that the same signal comparison circuit operates in the offset detection mode in each duty cycle is not limited to be equal to the length of time that the same signal comparison circuit operates in the signal comparison mode. For example, in some embodiments, the length of time that the same signal comparison circuit is operated in the offset detection mode in each duty cycle may be adjusted to be longer than the length of time that the same signal comparison circuit is operated in the signal comparison mode. For another example, in other embodiments, the length of time that the same signal comparison circuit is operated in the offset detection mode in each duty cycle may be adjusted to be shorter than the length of time that the same signal comparison circuit is operated in the signal comparison mode.
As mentioned above, all signal comparison circuits in the delta-sigma adc 100 can be designed to have similar circuit architecture and operation. The first signal comparator 130 is taken as an example, and an embodiment and an operation of each signal comparator are further described with reference to fig. 3 to 5.
Fig. 3 is a simplified functional diagram of a first embodiment of the first signal comparing circuit 130 in fig. 1. Fig. 4 is a simplified operation diagram of the first signal comparison circuit 130 operating in the offset detection mode. Fig. 5 is a simplified operation diagram of the first signal comparing circuit 130 operating in the signal comparing mode.
In the embodiment of fig. 3, the first comparator 132 of the first signal comparing circuit 130 includes a first input terminal 322, a second input terminal 324, a third input terminal 326, and a fourth input terminal 328. The first signal selecting circuit 134 includes a first switch circuit 342 and a second switch circuit 344. The first compensation circuit 136 includes a compensation capacitor 362, a first adjustment circuit 364, a second adjustment circuit 366, and a third switch circuit 368.
In the first comparator 132, the first input terminal 322 and the second input terminal 324 are coupled to the first signal selection circuit 134, the third input terminal 326 is coupled to the first compensation circuit 136, and the fourth input terminal 328 is coupled to a first common mode signal VCM1. The first comparator 132 is arranged to compare the signals at the first input 322 and the second input 324, and simultaneously the signals at the third input 326 and the fourth input 328, to generate a corresponding output signal. Each input signal of the first comparator 132 may be implemented in the form of a single-ended signal (single-ended signal) or a differential signal (differential). In operation, the signals at the first input 322, the second input 324, the third input 326 and the fourth input 328 affect the output signal generated by the first comparator 132. In practice, the first comparator 132 may be implemented by various suitable existing four-input comparators, and the first common-mode signal VCM1 may be implemented by a common-mode voltage (common mode voltage) signal between the third input 326 and the fourth input 328.
In the first signal selecting circuit 134, the first switch circuit 342 is coupled between the loop filter 120, the first fixed-potential signal VF1 and a first input terminal 322 of the first comparator 132, and configured to switch the signal coupled to the first input terminal 322 according to the control of the offset correcting circuit 150. The second switch circuit 344 is coupled between the first reference signal VR1, the first fixed-potential signal VF1, and a second input terminal 324 of the first comparator 132, and configured to switch the signal coupled to the second input terminal 324 according to the control of the offset calibration circuit 150.
In the first compensation circuit 136, a first terminal of the compensation capacitor 362 is coupled to the third input terminal 326, and a second terminal of the compensation capacitor 362 is coupled to a fixed potential terminal (e.g., ground terminal). The first adjusting circuit 364 is coupled to a first end of the compensation capacitor 362 and configured to charge the compensation capacitor 362 under the control of the offset correction circuit 150. The second adjusting circuit 366 is coupled to a first end of the compensation capacitor 362 and configured to discharge the compensation capacitor 362 under the control of the offset correction circuit 150. The third switching circuit 368 is configured to selectively couple the third input 326 of the first comparator 132 to the aforementioned first common-mode signal VCM1 under the control of the offset correction circuit 150.
In practice, the first comparator 132 described above can be implemented with any of a variety of suitable existing four-input comparators. The first common mode signal VCM1 may be implemented with a common mode voltage (common mode voltage) signal between the third input 326 and the fourth input 328. The first switch circuit 342 and the second switch circuit 344 can be implemented by various suitable combinations of transistors. The compensation capacitance 362 may be implemented with various suitable capacitors or parasitic capacitances within the circuit. The third switching circuit 368 may be implemented with various suitable single transistors or combinations of transistors. The first adjustment circuit 364 may be implemented with a suitable current source circuit. The second adjusting circuit 366 can be implemented with a suitable current sink circuit.
As shown in fig. 4, when the delta-sigma adc 100 starts to operate, the offset correction circuit 150 may first set the first signal comparison circuit 130 to operate in the offset detection mode for a period of time (e.g., a period T21). During this period, the offset correction circuit 150 may control the first switch circuit 342 to couple the first input terminal 322 to the first fixed-potential signal VF1, and control the second switch circuit 344 to couple the second input terminal 324 to the first fixed-potential signal VF1. During the first time that the first signal comparing circuit 130 operates in the offset detecting mode, the offset calibrating circuit 150 also turns on (turn on) the third switch circuit 368 to couple the third input terminal 326 to the aforementioned first common mode signal VCM1. Therefore, the first input terminal 322 and the second input terminal 324 of the first comparator 132 are short-circuited during the period, and the third input terminal 326 and the fourth input terminal 328 are short-circuited during the period. In this case, the first comparator 132 compares the signal at the first input 322 with the signal at the second input 324, and also compares the signal at the third input 326 with the signal at the fourth input 328, and generates a corresponding error signal, i.e., the first error signal ERR1, according to the two comparison results, regardless of the relative magnitudes of the filtered signal SF and the first reference signal VR 1.
During the period (e.g., the period T21) that the first signal comparing circuit 130 operates in the offset detecting mode, the offset calibration circuit 150 controls the first adjusting circuit 364 to charge the compensation capacitor 362 or controls the second adjusting circuit 366 to discharge the compensation capacitor 362 according to the polarity of the first error signal ERR1 generated in the current operation, so as to apply a compensation signal to the third input terminal 326 of the first comparator 132 to calibrate the signal offset of the first comparator 132. In operation, the offset correction circuit 150 may set the amount of charge per time by the first adjustment circuit 364 to a fixed amount and/or the amount of discharge per time by the second adjustment circuit 366 to a fixed amount.
Next, as shown in fig. 5, the offset correction circuit 150 may switch the first signal comparison circuit 130 to the signal comparison mode for a period of time (e.g., a period T22). During this period, the offset calibration circuit 150 can control the first switch circuit 342 to couple the first input terminal 322 to the filtered signal SF, control the second switch circuit 344 to couple the second input terminal 324 to the first reference signal VR1, and turn off (turn off) the third switch circuit 368. On the other hand, the offset correction circuit 150 is controlled to stop the charging/discharging operations of the compensation capacitor 362 during this period by the first adjusting circuit 364 and the second adjusting circuit 366. In the signal comparison mode, the first comparator 132 compares the filtered signal SF with the first reference signal VR1 to generate a first comparison signal CMP1 corresponding to the relative magnitudes of the filtered signal SF and the first reference signal VR 1. During this period, the first compensation circuit 136 continuously compensates the signal at the third input terminal 326, so the polarity of the first comparison signal CMP1 generated by the first comparator 132 reflects the signal offset of the third input terminal 326 after the compensation signal is applied thereto to some extent.
Thereafter, as shown in fig. 6, the offset correction circuit 150 may switch the first signal comparison circuit 130 to the offset detection mode for a period of time (e.g., a period T23). During this period, the offset correction circuit 150 controls the first signal selection circuit 134 and the first compensation circuit 136 in a manner substantially similar to that of the previous time the first signal comparison circuit 130 is set to the offset detection mode. The difference is that the offset correction circuit 150 turns on the third switch circuit 368 when the first signal comparison circuit 130 is set to the offset detection mode for the first time, but turns off the third switch circuit 368 each time the offset correction circuit 150 switches the first signal comparison circuit 130 to the offset detection mode thereafter. In other words, in the period T23, the third switch circuit 368 is in the off state.
In the time period T23, the first input terminal 322 and the second input terminal 324 of the first comparator 132 are also shorted, but the third input terminal 326 and the fourth input terminal 328 are not shorted. During this period, the first compensation circuit 136 continuously compensates the signal of the third input terminal 326.
Similarly, the first comparator 132 compares the signal at the first input terminal 322 with the signal at the second input terminal 324 and the signal at the third input terminal 326 with the signal at the fourth input terminal 328 during the period T23, and generates the first error signal ERR1 according to the comparison result regardless of the relative magnitudes of the filtered signal SF and the first reference signal VR 1.
The offset correction circuit 150 determines the compensation direction of each time by detecting the polarity of the first error signal ERR1 output by the first signal comparison circuit 130 in each offset detection mode, for example, when the polarity of the first error signal ERR1 generated in the current offset detection mode is negative, the offset correction circuit 150 controls the first adjustment circuit 364 to charge the compensation capacitor 362; if the polarity of the first error signal ERR1 generated in the current offset detection mode is positive, the offset calibration circuit 150 controls the second adjusting circuit 366 to discharge the compensation capacitor 362, so as to adjust the signal compensation amount applied to the third input terminal 326 of the first comparator 132, thereby reducing the signal offset of the first comparator 132.
Next, during the subsequent signal processing of the delta-sigma adc 100 for analog-to-digital conversion, the offset correction circuit 150 may repeat the operations of the foregoing time period T22 and time period T23 to intermittently detect and dynamically correct the signal offset of the first comparator 132 in the first signal comparison circuit 130.
Similarly, the offset correction circuit 150 may intermittently detect the signal offset condition of the second comparator 142 in the second signal comparison circuit 140 and dynamically control the second compensation circuit 146 to apply the compensation signal to the input terminal of the second comparator 142 to correct the signal offset condition of the second comparator 142 in the manner described above.
As can be seen from the foregoing description, the offset correction circuit 150 intermittently detects the signal offset of the comparator in each signal comparison circuit, and dynamically controls the respective compensation circuit to apply the compensation signal to the input terminal of the corresponding comparator, so as to correct the signal offset of the comparator in the delta-sigma adc 100.
Since the signal offset of different comparators is different, the amount of the compensation signal applied to the input terminal of the first comparator 132 by the first compensation circuit 136 at the same time point is likely to be different from the amount of the compensation signal applied to the input terminal of the second comparator 142 by the second compensation circuit 146.
On the other hand, since the offset correction circuit 150 adjusts the compensation circuit in the signal comparison circuit each time the signal comparison circuit operates in the offset detection mode, the adjustment direction may be the same as or different from the previous time. Therefore, the compensation amount of the input signal received by the same comparator is not constant, but shows a variation that fluctuates slightly with time, and the variation manner is similar to noise.
For example, the operation of the first compensation circuit 136 to apply the compensation signal to the input terminal of the first comparator 132 may be equivalent to applying a noise-like dither signal (dither signal) to the input terminal of the first comparator 132.
For another example, the operation of the second compensation circuit 146 for applying the compensation signal to the input terminal of the second comparator 142 may be equivalent to applying a noise-like dither signal to the input terminal of the second comparator 142.
Therefore, on the signal path between the first signal comparing circuit 130 of the delta-sigma adc 100 and the loop filter 120, there is no need to couple any conventional dither signal generating circuit, so that the possibility of the first comparator 132 outputting idle tone (idle tone) can be effectively avoided or reduced.
Similarly, the signal path between the second signal comparing circuit 140 and the loop filter 120 does not need to be coupled with any conventional jitter signal generating circuit, so that the possibility of outputting idle tones by the second comparator 142 can be effectively avoided or reduced.
In the aforementioned embodiment, the offset calibration circuit 150 switches the first signal comparator 130 and the second signal comparator 140 to the offset detection mode synchronously, and also switches the first signal comparator 130 and the second signal comparator 140 to the signal comparison mode synchronously. This is only an exemplary mode of operation and is not limiting of the actual embodiments of the invention.
For example, fig. 7 is a simplified second embodiment of the delta-sigma adc 100 of fig. 1.
In the embodiment of fig. 7, the offset correction circuit 150 controls all signal comparison circuits to operate in the signal comparison mode synchronously in the same period, but sets the periods in which different signal comparison circuits operate in the offset detection mode to be different. For example, as shown in fig. 7, the offset correction circuit 150 may set the first signal comparison circuit 130 to operate in the offset detection mode for a period T71, and set the second signal comparison circuit 140 to operate in the offset detection mode for a period T72 thereafter. Next, in the period T73, the offset correction circuit 150 controls all the signal comparison circuits to operate in the signal comparison mode. In another embodiment, the offset correction circuit 150 may set the first signal comparison circuit 130 to operate in the offset detection mode during a period T71, then control all the signal comparison circuits to operate in the signal comparison mode during a period T73, and set the second signal comparison circuit 140 to operate in the offset detection mode only during a period T74 in the next clock cycle.
Next, the offset correction circuit 150 may set the first signal comparison circuit 130 to operate in the offset detection mode for a period T74, and set the second signal comparison circuit 140 to operate in the offset detection mode for a period T75 thereafter.
In other words, the timing at which the first signal comparing circuit 130 and the second signal comparing circuit 140 are switched to the offset detecting mode may be different, and the time length in the offset detecting mode may also be different. Such an operation mode can reduce the operation burden of the offset correction circuit 150 in the same period, and can reduce the operation capability requirement of the offset correction circuit 150, so that the offset correction circuit 150 can be implemented by a relatively simplified circuit architecture.
In addition, in the aforementioned embodiment, the first compensation circuit 136 includes a compensation capacitor 362, a first adjustment circuit 364, a second adjustment circuit 366, and a third switch circuit 368. This is merely an exemplary architecture and is not intended to limit embodiments of the present invention.
For example, fig. 8 is a simplified functional diagram of a second embodiment of the first signal comparing circuit 130 in fig. 1. In the embodiment of fig. 8, the aforementioned third switching circuit 368 is omitted in the first compensation circuit 136.
In this case, the offset correction circuit 150 may control the first adjustment circuit 364 to charge the compensation capacitor 362 or the second adjustment circuit 366 to discharge the compensation capacitor 362 when the first signal comparison circuit 130 is set to the offset detection mode for the first time, so as to apply a predetermined signal compensation amount to the third input 326 of the first comparator 132. By repeating the operations of the time periods T22 and T23, the signal offset of the first comparator 132 in the first signal comparing circuit 130 can be effectively corrected, but the time required for reaching the steady state may be slightly longer than that of the previous embodiment of fig. 3.
For another example, fig. 9 is a simplified functional diagram of a third embodiment of the first signal comparing circuit 130 in fig. 1. In the embodiment of fig. 9, the second adjusting circuit 366 and the third switching circuit 368 are omitted from the first compensating circuit 136.
In this case, the offset correction circuit 150 may control the first adjustment circuit 364 to charge the compensation capacitor 362 to apply a predetermined signal compensation amount to the third input 326 of the first comparator 132 when the first signal comparison circuit 130 is set to the offset detection mode for the first time. By repeating the operations of the time periods T22 and T23, the signal offset of the first comparator 132 in the first signal comparing circuit 130 can be corrected, but the time required for reaching the steady state may be slightly longer than that of the embodiment of fig. 8.
Note that the number of signal comparison circuits in the delta-sigma adc 100 is not limited to the foregoing embodiments. In practice, the number of signal comparison circuits in the delta-sigma adc 100 can be increased according to circuit requirements. In some embodiments, the number of signal comparison circuits in the delta-sigma adc 100 can be reduced to only one, so as to simplify the overall circuit structure.
In addition, the number of the input terminals of the comparators (e.g., the first comparator 132 and the second comparator 142) in each signal comparison circuit can be expanded to a larger number according to the circuit requirements, and is not limited to 4 in the foregoing embodiments.
In some embodiments, a compensation circuit having the same structure as the first compensation circuit 136 but with the opposite compensation direction may be additionally coupled to the fourth input 328 of the first comparator 132. In some embodiments, the first compensation circuit 136 may be modified to be coupled to the fourth input terminal 328 of the first comparator 132. In some embodiments, the third input 326 and the fourth input 328 of the first comparator 132 may be coupled to a switched-capacitor (switched-capacitor) circuit capable of providing a signal compensation function similar to the first compensation circuit 136. Similarly, the compensation circuit coupled to the input terminal of the comparator in the other signal comparison circuits can also be modified according to the above variation.
As can be seen from the foregoing description, the offset calibration circuit 150 can effectively calibrate the signal offset of each signal comparison circuit in the delta-sigma adc 100, so that the overall performance of the delta-sigma adc 100 can be improved.
The offset correction circuit 150 controls the operation of the compensation circuit to apply the compensation signal to the input terminal of the correlation comparator, and is equivalent to applying a noise-like dither signal to the input terminal of the comparator, so that the possibility of the comparator in the delta-sigma analog-to-digital converter 100 outputting idle noise can be effectively avoided or reduced at the same time. Therefore, an additional dither signal generating circuit is not required to be provided in the delta-sigma adc 100, and the complexity of the circuit can be simplified.
Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to like elements by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or indirectly connected to the second element through other elements or connection means.
The description of "and/or" as used in this specification is inclusive of any combination of one or more of the items listed. In addition, any singular term shall include the plural unless the specification specifically states otherwise.
The "voltage signal" in the specification and the claims can be realized in a voltage form or a current form. The "current signal" in the specification and claims may be implemented in a voltage form or a current form.
The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.
Claims (10)
1. A delta-sigma analog-to-digital converter (100), comprising:
-a subtractor (110) arranged to subtract a feedback signal (Sfb) from an analog input signal (Sin);
a loop filter (120), coupled to the subtractor (110), configured to process an output signal of the subtractor (110) to generate a filtered Signal (SF);
a first signal comparison circuit (130), coupled to the loop filter (120) and a first reference signal (VR 1), configured to selectively operate in an offset detection mode or a signal comparison mode, wherein the first signal comparison circuit (130) operates in the offset detection mode to generate a first error signal (ERR 1) independent of the relative magnitudes of the filtered Signal (SF) and the first reference signal (VR 1), and operates in the signal comparison mode to generate a first comparison signal (CMP 1) corresponding to the relative magnitudes of the filtered Signal (SF) and the first reference signal (VR 1);
an offset calibration circuit (150), coupled to the first signal comparison circuit (130), configured to calibrate an offset of the first signal comparison circuit (130) according to the first error signal (ERR 1), and control the first signal comparison circuit (130) to alternately switch between the offset detection mode and the signal comparison mode; and
a digital-to-analog converter (160), coupled to an output of the first signal comparison circuit (130) and the subtractor (110), configured to generate the feedback signal (Sfb) according to the first comparison signal (CMP 1),
wherein the first signal comparison circuit (130) comprises:
a first comparator (132) having a first input (322), a second input (324), a third input (326), and a fourth input (328), arranged to compare signals at the first input (322) and the second input (324), and to compare signals at the third input (326) and the fourth input (328) to generate a corresponding output signal, wherein the fourth input (328) is coupled to a first common mode signal (VCM 1); and
a first signal selection circuit (134) coupled to the loop filter (120), the first input terminal (322) of the first comparator (132), the second input terminal (324) of the first comparator (132), the offset correction circuit (150), the first reference signal (VR 1), and a first fixed-potential signal (VF 1), wherein in the offset detection mode, the first signal selection circuit (134) couples both the first input terminal (322) and the second input terminal (324) to the first fixed-potential signal (VF 1), so that the first comparator (132) generates the first error signal (ERR 1), and in the signal comparison mode, the first signal selection circuit (134) instead couples the first input terminal (322) and the second input terminal (324) to the filtered Signal (SF) and the first reference signal (VR 1), respectively, so that the first comparator (132) generates the first comparison signal (CMP 1).
2. The delta-sigma analog-to-digital converter (100) of claim 1, wherein the first signal comparison circuit (130) further comprises:
a first compensation circuit (136) coupled to the third input (326) of the first comparator (132) and the offset correction circuit (150) and configured to compensate the signal at the third input (326) of the first comparator (132) according to the control of the offset correction circuit (150);
wherein the offset correction circuit (150) is further configured to control the first signal selection circuit (134) to switch to the offset detection mode at least once and to switch to the signal comparison mode at least once every predetermined number of duty cycles of an operating Clock (CLK), and the offset correction circuit (150) is further configured to adjust the signal compensation amount of the first compensation circuit (136) according to the first error signal (ERR 1).
3. The delta-sigma analog-to-digital converter (100) of claim 2, wherein the first signal selection circuit (134) comprises:
a first switch circuit (342) coupled between the loop filter (120), the first fixed-potential signal (VF 1), and the first input terminal (322), and controlled by the offset correction circuit (150); and
a second switch circuit (344), coupled between the first reference signal (VR 1), the first fixed-potential signal (VF 1), and the second input terminal (324), and controlled by the offset correction circuit (150);
wherein, in the offset detection mode, the offset correction circuit (150) controls the first switch circuit (342) to couple the first input terminal (322) to the first fixed potential signal (VF 1), and controls the second switch circuit (344) to couple the second input terminal (324) to the first fixed potential signal (VF 1); in the signal comparison mode, the offset correction circuit (150) controls the first switch circuit (342) to couple the first input (322) to the filtered Signal (SF) and controls the second switch circuit (344) to couple the second input (324) to the first reference signal (VR 1).
4. The delta-sigma analog-to-digital converter (100) of claim 3, wherein the first compensation circuit (136) comprises:
a compensation capacitor (362), wherein a first terminal of the compensation capacitor (362) is coupled to the third input terminal (326), and a second terminal of the compensation capacitor (362) is coupled to a fixed potential terminal; and
a first tuning circuit (364), coupled to a first end of the compensation capacitor (362), is configured to charge the compensation capacitor (362) under the control of the offset correction circuit (150).
5. The delta-sigma analog-to-digital converter (100) of claim 4, wherein the first compensation circuit (136) further comprises:
a second adjusting circuit (366) coupled to the first end of the compensation capacitor (362) and configured to discharge the compensation capacitor (362) under the control of the offset correction circuit (150).
6. The delta-sigma analog-to-digital converter (100) of claim 5, wherein the first compensation circuit (136) further comprises:
a third switching circuit (368) configured to selectively couple the third input (326) of the first comparator (132) to the first common-mode signal (VCM 1) under control of the offset correction circuit (150).
7. The delta-sigma analog-to-digital converter (100) of claim 4, wherein the first compensation circuit (136) further comprises:
a third switching circuit (368) configured to selectively couple the third input (326) of the first comparator (132) to the first common-mode signal (VCM 1) under control of the offset correction circuit (150).
8. The delta-sigma analog-to-digital converter (100) of claim 2, further comprising:
a second signal comparison circuit (140), coupled to the loop filter (120), the offset correction circuit (150), the digital-to-analog converter (160), and a second reference signal (VRn), configured to selectively operate in the offset detection mode or the signal comparison mode, wherein the second signal comparison circuit (140) is operable in the offset detection mode to generate a second error signal (ERRn) independent of the relative magnitudes of the filtered Signal (SF) and the second reference signal (VRn), and operable in the signal comparison mode to generate a second comparison signal (CMPn) corresponding to the relative magnitudes of the filtered Signal (SF) and the second reference signal (VRn);
wherein the offset correction circuit (150) is further configured to correct an offset condition of the second signal comparison circuit (140) according to the second error signal (ERRn) and control the second signal comparison circuit (140) to alternately switch between the offset detection mode and the signal comparison mode, and the digital-to-analog converter (160) is further configured to generate the feedback signal (Sfb) according to the second comparison signal (CMPn).
9. The delta-sigma analog-to-digital converter (100) of any of claims 2 to 8, wherein no dither signal generation circuit is coupled in a signal path between the first comparator (132) and the loop filter (120).
10. The delta-sigma analog-to-digital converter (100) of any of claims 2 to 8, wherein the first input (322), the second input (324), the third input (326), and the fourth input (328) of the first comparator (132) are not coupled to any dither signal generating circuit.
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| DE102006004212A1 (en) * | 2006-01-30 | 2007-08-09 | Xignal Technologies Ag | Delta-sigma-analog-digital-converter, has calibrating device connected with quantizer, and designed to determine and compensate offset error of comparator at predetermined time point |
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