CN219918900U - Driving circuit topological structure for PMOS (P-channel metal oxide semiconductor) tube - Google Patents
Driving circuit topological structure for PMOS (P-channel metal oxide semiconductor) tube Download PDFInfo
- Publication number
- CN219918900U CN219918900U CN202320715978.0U CN202320715978U CN219918900U CN 219918900 U CN219918900 U CN 219918900U CN 202320715978 U CN202320715978 U CN 202320715978U CN 219918900 U CN219918900 U CN 219918900U
- Authority
- CN
- China
- Prior art keywords
- circuit
- level shift
- voltage
- push
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 239000004065 semiconductor Substances 0.000 title abstract description 3
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 33
- 239000000725 suspension Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005339 levitation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model discloses a driving circuit topological structure for a PMOS (P-channel metal oxide semiconductor) tube in the field of power driving, which comprises a level shift circuit, a voltage stabilizing circuit and a push-pull circuit, wherein one input end of the level shift circuit is input with a low-voltage square wave, the other input end of the level shift circuit is connected with a power supply, the output end of the level shift circuit is connected with the output end of the voltage stabilizing circuit and one input end of the push-pull circuit, the input end of the voltage stabilizing circuit and the other input end of the push-pull circuit are both connected with the power supply, and the output end of the push-pull circuit is connected with a grid electrode of the PMOS tube. The utility model can realize the on-off control of the high-end PMOS tube through a simple level shift circuit, a voltage stabilizing circuit and a push-pull circuit without adding a suspension power supply circuit, has high reliability and wide applicability, and is particularly suitable for driving the high-voltage and high-current P-channel enhanced MOS tube.
Description
Technical Field
The utility model relates to the field of power driving, in particular to a driving circuit topological structure for a PMOS tube.
Background
In the power driving control circuit, the common power switch tube is provided with an N-communication enhancement type MOS tube (hereinafter referred to as NMOS tube) and a P-communication enhancement type MOS tube (hereinafter referred to as PMOS tube), the NMOS tube can be adopted in the application of the high-end (directly connected with a power supply) power switch tube, the PMOS tube can be adopted, when the NMOS tube is adopted, the drain electrode (D) of the NMOS tube is connected with a power supply end, the source electrode S is connected with a load, when the circuit works normally, the voltage of the source electrode S of the NMOS tube can rise necessarily, according to the requirement of NMOS tube driving, the grid electrode G of the NMOS tube must be higher than the source electrode voltage at the moment to ensure that the NMOS tube keeps in a normal on state, and when the PMOS tube is adopted at the high end, the source electrode of the high-end power switch tube is directly connected with the power supply end according to the characteristic of the PMOS tube, and the drain electrode D is connected with a load according to the requirement of PMOS tube driving, so long as the grid electrode G of the PMOS tube is lower than the source electrode S by a certain amplitude, the PMOS tube can be normally opened, and an extra suspension power supply circuit is not needed.
The applicant provides a drive circuit topology for a high-end PMOS tube aiming at the characteristics of the PMOS tube.
Disclosure of Invention
The utility model aims to provide a drive circuit topological structure for a PMOS tube, so as to solve the problems in the background technology.
In order to achieve the above purpose, the present utility model provides the following technical solutions:
the utility model provides a drive circuit topological structure for PMOS pipe, includes level shift circuit, voltage stabilizing circuit and push-pull circuit, the input of level shift circuit has the low pressure square wave, and another input is connected with power supply, and the output of voltage stabilizing circuit and one input of push-pull circuit are connected to the output, and power supply is all connected to voltage stabilizing circuit's input and another input of push-pull circuit, the grid of PMOS pipe is connected to push-pull circuit's output.
In some embodiments, the level shift circuit includes an NMOS V2 and an N-channel JFET V3, where the gate of the NMOS V2 inputs a low voltage square wave, the source is grounded, the drain is connected to the source of the N-channel JFET V3, the gate and the output of the voltage regulator circuit, and the drain of the N-channel JFET V3 is connected to a power supply.
In some embodiments, the level shift circuit includes an NMOS V2 and a resistor R1, where a low voltage square wave is input to the gate of the NMOS V2, the source is grounded, the drain is connected to one end of the resistor R1 and the output end of the voltage stabilizing circuit, and the other end of the resistor R1 is connected to a power supply.
In some embodiments, the level shift circuit includes an NPN triode V2, an N-channel JFET V3, and a resistor R1, where a base of the NPN triode V2 is connected to the low voltage square wave through the resistor R1, an emitter is grounded, a collector is connected to a source and a gate of the N-channel JFET V3, and an output terminal of the voltage stabilizing circuit, and a drain of the N-channel JFET V3 is connected to a power supply.
In some embodiments, the push-pull circuit includes an NPN triode V5 and a PNP triode V6, the bases of the NPN triode V5 and the PNP triode V6 are commonly connected to the output ends of the level shift circuit and the push-pull circuit, the collector of the NPN triode V5 is grounded, the emitter is connected to the emitter of the PNP triode V6 and the gate of the PMOS transistor, and the collector of the PNP triode V6 is grounded.
In some embodiments, the voltage stabilizing circuit comprises a voltage stabilizing tube, wherein the cathode of the voltage stabilizing tube is connected with the power supply, and the anode of the voltage stabilizing tube is connected with the output end of the level shifting circuit.
The beneficial effects are that: the utility model can realize the on-off control of the high-end PMOS tube through a simple level shift circuit, a voltage stabilizing circuit and a push-pull circuit without adding a suspension power supply circuit, has high reliability and wide applicability, and is particularly suitable for driving the high-voltage and high-current P-channel enhanced MOS tube.
Drawings
FIG. 1 is a schematic circuit diagram of embodiment 1 of the present utility model;
FIG. 2 is a schematic circuit diagram of embodiment 2 of the present utility model;
fig. 3 is a schematic circuit diagram of embodiment 3 of the present utility model.
In the figure: a 1-level shift circuit; 2-a voltage stabilizing circuit; 3-push-pull circuit.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Referring to fig. 1, an embodiment 1 of a driving circuit topology structure for PMOS transistors includes a level shift circuit 1, a voltage stabilizing circuit 2, and a push-pull circuit 3. The level shift circuit 1 includes an NMOS transistor V2 and an N-channel JFET transistor V3, the voltage regulator circuit 2 includes a voltage regulator tube V4, and the push-pull circuit 3 includes an NPN transistor V5 and a PNP transistor V6.
The grid electrode of the NMOS tube V2 is input with a low-voltage square wave, the source electrode is grounded, the drain electrode is connected with the source electrode of the N-channel JFET tube V3, the grid electrode, the positive electrode of the voltage regulator tube V4, the base electrode of the NPN triode V5 and the base electrode of the PNP triode V6, the drain electrode of the N-channel JFET tube V3 is connected with a power supply Vs, the negative electrode of the voltage regulator tube V4 is connected with the power supply Vs, the collector electrode of the NPN triode V5 is grounded, the emitter electrode of the PNP triode V6 is connected with the grid electrode of the PMOS tube V1, and the collector electrode of the PNP triode V6 is grounded.
In the embodiment, the switching on and off of the high-end high-voltage high-current PMOS tube V1 is realized by utilizing the current amplification function of the push-pull circuit 3 after the low-voltage square is input by the level shift circuit 1. The working principle is as follows:
according to the performance characteristics of the N-channel JFET, after the source S and the gate G of the N-channel JFET are connected, the N-channel JFET V3 is equivalent to a constant current tube and is always in a constant-current conducting state. When the input low-voltage square wave is at a high level, the NMOS transistor V2 is turned on, at this time, the power supply +vs forms a loop through the N-channel JFET V3, the voltage stabilizing transistor V4 and the NMOS transistor V2, and due to the voltage stabilizing effect of the voltage stabilizing transistor V4, the voltage values of the source S and the drain D of the N-channel JFET V3 drop by at least 10V relative to the power supply +vs (related to the actual voltage stabilizing value of the voltage stabilizing transistor V4, generally, not more than 20V), that is, the voltages of the base B of the NPN transistor V5 and the PNP transistor V6 drop by more than 10V relative to the power supply +vs, and the source S of the back-end PMOS transistor V1 is connected to the power supply +vs.
Because of the parasitic capacitance relationship between the grid electrode and the source electrode of the PMOS transistor, the voltage of the grid electrode G is similar to the voltage of the source electrode S in the initial state, and at the moment, the voltage of the emitter electrode E of the PNP triode V6 (namely the grid electrode G of the rear-end PMOS transistor V1) is larger than the voltage of the base electrode B of the PNP triode V6. According to the characteristic of the PNP triode, the emitter E and the base B of the PNP triode V6 are conducted, meanwhile, the voltage of the emitter E is pulled down, the voltage value is about 0.6V smaller than that of the base B, and at the moment, for the PMOS tube, the voltage of the end G of the grid electrode is 10V or more lower than that of the source S, so that the opening condition of the PMOS tube is met, and the PMOS tube V1 is in a complete conducting state.
When the input low-voltage square wave is at low level, the NMOS transistor V2 is turned off, the power supply +Vs cannot form a loop with the power supply +Vs, and the N-channel JFET transistor V3 is always in a conducting state, at this time, the voltage values of the source S and the drain D of the N-channel JFET transistor V3 are equivalent to the voltage of the power supply +Vs, namely the voltage of the base B of the NPN triode V5 and the PNP triode V6 is equal to the voltage of the power supply +Vs.
In the above state, the voltage of the gate G of the PMOS transistor V1 is pulled down to be 10V or more smaller than the voltage of the power supply +vs, at this time, for the NPN transistor V5, the base B voltage is higher than the emitter E voltage, and the base B and the emitter E of the transistor V5 are turned on, and according to the NPN transistor characteristics, the emitter E voltage approaches the base B voltage and drops by about 0.6V than the base B voltage, so at this time, the voltage of the source S of the PMOS transistor V1 is only 0.6V higher than the base B voltage (the emitter E voltage of the NPN transistor V5) and does not satisfy the turn-on voltage (at least 4V to 5V or more) of the PMOS transistor V1 is turned off.
Therefore, the on-off driving of the PMOS tube V1 can be controlled by controlling the high-low level of the low-voltage square wave through the conversion of the high-low level of the level conversion circuit and the current amplification of the push-pull circuit 3, the levitation power supply is not needed, and the control is simple and convenient and is suitable for the driving of the high-voltage high-current power PMOS tube.
In embodiment 2, as shown in fig. 2, a driving circuit topology structure for PMOS transistors includes a level shift circuit 1, a voltage stabilizing circuit 2, and a push-pull circuit 3. This embodiment differs from embodiment 1 in that: the level shift circuit 1 comprises an NMOS tube V2 and a resistor R1, wherein a grid electrode of the NMOS tube V2 is input with a low-voltage square wave, a source electrode is grounded, a drain electrode is connected with one end of the resistor R1, an anode of a voltage stabilizing tube V4, a base electrode of an NPN triode V5 and a base electrode of a PNP triode V6, and the other end of the resistor R1 is connected with a power supply Vs.
In this embodiment, the resistor R1 is used for providing the bias current for the level shift circuit 1, and the implementation principle is the same as that of embodiment 1, and will not be described again.
Embodiment 3, as shown in fig. 3, is a driving circuit topology structure for PMOS transistors, comprising a level shift circuit 1, a voltage stabilizing circuit 2, and a push-pull circuit 3. This embodiment differs from embodiment 1 in that: the level shift circuit 1 comprises an NPN triode V2, an N-channel JFET V3 and a resistor R1, wherein the base electrode of the NPN triode V2 is connected with a low-voltage square wave through the resistor R1, the emitter electrode is grounded, the collector electrode is connected with the source electrode and the grid electrode of the N-channel JFET V3, the positive electrode of the voltage regulator V4 and the base electrodes of the NPN triode V5 and the PNP triode V6, and the drain electrode of the N-channel JFET V3 is connected with a power supply Vs.
Compared with the embodiment 1, the embodiment replaces the middle and low power NMOS transistor V2 with the low power NPN transistor V2, and the NPN transistor belongs to a current control device, so that the resistor R1 is added to convert a voltage signal of the low-voltage square wave into a current signal, and the control of the NPN transistor V2 is realized. The implementation principle of this embodiment is the same as that of embodiment 1, and will not be described again.
Those skilled in the art will appreciate that in other embodiments, the voltage stabilizing circuit may be implemented using a voltage stabilizing element having a similar voltage stabilizing function in addition to the voltage stabilizing tube.
Although the present disclosure describes embodiments, not every embodiment is described in terms of a single embodiment, and such description is for clarity only, and one skilled in the art will recognize that the embodiments described in the disclosure as a whole may be combined appropriately to form other embodiments that will be apparent to those skilled in the art.
Therefore, the above description is not intended to limit the scope of the utility model; all changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (6)
1. The driving circuit topological structure for the PMOS tube is characterized by comprising a level shift circuit, a voltage stabilizing circuit and a push-pull circuit, wherein one input end of the level shift circuit is input with a low-voltage square wave, the other input end of the level shift circuit is connected with a power supply, the output end of the level shift circuit is connected with one input end of the push-pull circuit, the input end of the voltage stabilizing circuit and the other input end of the push-pull circuit are both connected with the power supply, and the output end of the push-pull circuit is connected with the grid electrode of the PMOS tube.
2. The driving circuit topology for PMOS transistor according to claim 1, wherein the level shift circuit comprises an NMOS transistor V2 and an N-channel JFET V3, the gate of the NMOS transistor V2 is input with a low voltage square wave, the source is grounded, the drain is connected to the source, gate and output terminal of the voltage stabilizing circuit of the N-channel JFET V3, and the drain of the N-channel JFET V3 is connected to a power supply.
3. The driving circuit topology structure for PMOS transistors according to claim 1, wherein the level shift circuit comprises an NMOS V2 and a resistor R1, the gate of the NMOS V2 inputs a low voltage square wave, the source is grounded, the drain is connected to one end of the resistor R1 and the output end of the voltage stabilizing circuit, and the other end of the resistor R1 is connected to a power supply.
4. The driving circuit topology structure for PMOS transistor according to claim 1, wherein the level shift circuit comprises an NPN triode V2, an N-channel JFET V3, and a resistor R1, wherein a base of the NPN triode V2 is connected to a low-voltage square wave through the resistor R1, an emitter is grounded, a collector is connected to a source and a gate of the N-channel JFET V3, and an output terminal of the voltage stabilizing circuit, and a drain of the N-channel JFET V3 is connected to a power supply.
5. The driving circuit topology structure for PMOS transistors according to claim 1, 2, 3 or 4, wherein the push-pull circuit includes an NPN transistor V5 and a PNP transistor V6, the bases of the NPN transistor V5 and the PNP transistor V6 are commonly connected to the output terminals of the level shift circuit and the push-pull circuit, the collector of the NPN transistor V5 is grounded, the emitter is connected to the emitter of the PNP transistor V6 and the gate of the PMOS transistor, and the collector of the PNP transistor V6 is grounded.
6. The driving circuit topology for PMOS transistors of claim 5, wherein said voltage regulator circuit comprises a voltage regulator tube having a negative terminal connected to a power supply and a positive terminal connected to an output terminal of a level shift circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320715978.0U CN219918900U (en) | 2023-03-31 | 2023-03-31 | Driving circuit topological structure for PMOS (P-channel metal oxide semiconductor) tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320715978.0U CN219918900U (en) | 2023-03-31 | 2023-03-31 | Driving circuit topological structure for PMOS (P-channel metal oxide semiconductor) tube |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219918900U true CN219918900U (en) | 2023-10-27 |
Family
ID=88424247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320715978.0U Active CN219918900U (en) | 2023-03-31 | 2023-03-31 | Driving circuit topological structure for PMOS (P-channel metal oxide semiconductor) tube |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219918900U (en) |
-
2023
- 2023-03-31 CN CN202320715978.0U patent/CN219918900U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102033560A (en) | Voltage regulator | |
| CN100589324C (en) | Voltage selecting circuit | |
| CN219918900U (en) | Driving circuit topological structure for PMOS (P-channel metal oxide semiconductor) tube | |
| CN115940642B (en) | Switching tube conduction speed control circuit | |
| CN115167591B (en) | Floating high-end power supply generating circuit based on zener diode | |
| CN113744690B (en) | Level conversion circuit, display driving circuit and silicon-based organic light emitting display device | |
| CN113484737B (en) | Signal adjusting unit, signal adjusting module and testing machine | |
| CN221748360U (en) | PIN diode equivalent circuit | |
| CN219577035U (en) | LINK low-voltage high-speed module improvement circuit | |
| CN115001477B (en) | Signal interface circuit for positive and negative voltage input | |
| CN220492858U (en) | Push-pull type output circuit for preventing reverse input electric leakage | |
| CN221748209U (en) | Gate drive circuit based on charge pump | |
| CN112838764B (en) | Power supply level conversion circuit and method | |
| CN109818601B (en) | Negative level selection circuit suitable for depletion type switch | |
| CN220190674U (en) | Driving circuit of switching power supply and switching power supply | |
| CN218888381U (en) | Driving circuit for outputting positive and negative asymmetric voltages | |
| CN110729895A (en) | Voltage bootstrap circuit and drive control circuit that full N type MOSFET realized | |
| CN219611599U (en) | Double-tube forward driving power supply circuit | |
| CN116137524B (en) | Comparator with high voltage input resistance | |
| CN109194319B (en) | PMOS tube driving circuit | |
| CN220325607U (en) | Radio frequency switch voltage bias circuit | |
| CN216751704U (en) | Normally closed relay | |
| CN218514365U (en) | High-frequency driving circuit of MOS (Metal oxide semiconductor) tube | |
| CN219513959U (en) | N-type power tube driving circuit and driving chip | |
| CN218733247U (en) | Reverse protection circuit and load switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |