CN219893305U - Field effect power switch driving circuit - Google Patents
Field effect power switch driving circuit Download PDFInfo
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- CN219893305U CN219893305U CN202320158815.7U CN202320158815U CN219893305U CN 219893305 U CN219893305 U CN 219893305U CN 202320158815 U CN202320158815 U CN 202320158815U CN 219893305 U CN219893305 U CN 219893305U
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- 230000005669 field effect Effects 0.000 title claims abstract description 99
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000001514 detection method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
Provided is a field effect power switch driving circuit including a driving control unit, a high level driving switch, a low level driving switch, and a clamp unit, wherein: the first and second output terminals of the drive control unit are respectively connected to the gate of the high-level drive switch and the gate of the low-level drive switch; the drain electrode of the high-level driving switch is connected to an internal power supply of the circuit, the source electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch; the source electrode of the low-level driving switch is grounded; and the clamping unit is used for controlling the voltage difference between the grid electrode of the high-level driving switch and the source electrode of the field effect power switch to be a fixed value.
Description
Technical Field
The utility model relates to the field of circuits, in particular to a field effect power switch driving circuit.
Background
Field-effect power switches represented by gallium nitride field-effect transistors and Metal Oxide Semiconductor (MOS) field-effect transistors are widely used in switching power supplies, light-emitting diode (LED) driving, motor driving, audio power amplification, and other systems, wherein the maximum saturation current that a field-effect power switch can withstand is closely related to the voltage difference between its gate and source (hereinafter referred to as "gate-source voltage").
Disclosure of Invention
The field effect power switch driving circuit according to the embodiment of the utility model comprises a driving control unit, a high-level driving switch, a low-level driving switch and a clamping unit, wherein: the first and second output terminals of the drive control unit are respectively connected to the gate of the high-level drive switch and the gate of the low-level drive switch; the drain electrode of the high-level driving switch is connected to an internal power supply of the circuit, the source electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch; the source electrode of the low-level driving switch is grounded; and the clamping unit is used for controlling the voltage difference between the grid electrode of the high-level driving switch and the source electrode of the field effect power switch to be a fixed value.
According to another embodiment of the present utility model, a field effect power switch driving circuit includes a driving control unit, a high level driving switch, a low level driving switch, and a clamp unit, wherein: the first and second output terminals of the drive control unit are respectively connected to the gate of the high-level drive switch and the gate of the low-level drive switch; the source electrode of the high-level driving switch is connected to an internal power supply of the circuit, the drain electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch; the source electrode of the low-level driving switch is grounded; and the clamping unit is used for controlling the voltage difference between the grid electrode and the source electrode of the field effect power switch to be a fixed value.
Drawings
The utility model will be better understood from the following description of specific embodiments thereof, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic diagram of a field effect power switch driving circuit according to an embodiment of the present utility model.
Fig. 2 shows waveforms of a plurality of signals associated with the field effect power switch driving circuit shown in fig. 1.
Fig. 3 shows a schematic diagram of a field effect power switch driving circuit according to another embodiment of the present utility model.
Fig. 4 shows waveforms of a plurality of signals associated with the field effect power switch driving circuit shown in fig. 3.
Detailed Description
Features and exemplary embodiments of various aspects of the utility model are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the utility model. It will be apparent, however, to one skilled in the art that the present utility model may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the utility model by showing examples of the utility model. The present utility model is in no way limited to any particular configuration set forth below, but rather covers any modification, substitution, or improvement of elements and components without departing from the spirit of the utility model. In the drawings and the following description, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present utility model. In addition, the term "a and B connected" as used herein may mean "a and B directly connected" or "a and B indirectly connected via one or more other elements".
In general, the larger the gate-source voltage of a field-effect power switch, the greater the maximum saturation current it can withstand within the allowable operating range. However, in practice, the source voltage of a field-effect power switch often increases with an increasing current flowing through it, which results in a reduced gate-source voltage of the field-effect power switch and a correspondingly smaller maximum saturation current that can be tolerated. Because of the limitation of the gate-source breakdown voltage of the field-effect power switch (especially the gate-source voltage of the gallium nitride field-effect transistor is generally required to be less than 7V), the field-effect power switch with larger maximum saturation current can be selected in practical application, but the field-effect power switch is generally more expensive.
In view of the above, a field-effect power switch driving circuit according to an embodiment of the present utility model is provided, which is capable of controlling a gate voltage of a field-effect power switch to follow a source voltage so that a gate-source voltage of the field-effect power switch remains unchanged, thereby enabling a maximum saturation current that the field-effect power switch can withstand to be unchanged with a change in the source voltage thereof.
Fig. 1 is a schematic diagram of a field effect power switch driving circuit according to an embodiment of the present utility model. As shown in fig. 1, the field effect power switch driving circuit 100 includes a driving control unit U1, a high level driving switch M1, a low level driving switch M2, and a clamp unit U2, wherein: the first and second output terminals of the drive control unit U1 are connected to the gate of the high-level drive switch M1 and the gate of the low-level drive switch M2, respectively; the drain electrode of the high-level driving switch M1 is connected to the circuit internal power supply VDD, the source electrode is connected to the drain electrode of the low-level driving switch M2 and is used for being connected to the grid electrode of the field effect power switch M0; the source electrode of the low-level driving switch M2 is grounded; the clamping unit U2 is configured to control a voltage difference between the gate of the high-level driving switch M1 and the source of the field-effect power switch M0 to be a first fixed value.
As shown in fig. 1, in some embodiments, the first terminal of the clamp unit U2 is connected to the gate of the high-level driving switch M1, the second terminal is for connection to the source of the field-effect power switch M0 and for grounding via the detection resistor R0.
As shown in fig. 1, in some embodiments, the high-level driving switch M1 and the low-level driving switch M2 may be implemented as N-type MOS field effect transistors, and the clamping unit U2 may be implemented as a zener diode.
Fig. 2 shows waveforms of a plurality of signals associated with the field effect power switch driving circuit shown in fig. 1, wherein: PWM means a Pulse Width Modulation (PWM) control signal received from the outside by the field-effect power switch driving circuit 100 for controlling on and off of the high-level driving switch M1 and the low-level driving switch M2, drv_h means a Gate driving signal for controlling on and off of the high-level driving switch M1, gate means a Gate driving signal for controlling on and off of the field-effect power switch M0, CS means a source voltage detection signal of the field-effect power switch M0, vgs means a Gate-source voltage of the field-effect power switch M0.
As can be seen in conjunction with fig. 1 and 2, the specific operation of the field effect power switch driving circuit 100 is as follows: the drive control unit U1 receives a PWM control signal from the outside and generates a gate drive signal drv_h for the high-level drive switch M1 and a gate drive signal drv_l for the low-level drive switch M2 based on the PWM control signal; when the Gate driving signal drv_h is at a high level (i.e., the high-level driving switch M1 is in an on state) and the Gate driving signal drv_l is at a low level (i.e., the low-level driving switch M2 is in an off state), the Gate driving signal Gate is at a high level (i.e., the field-effect power switch M0 is in an on state), the Gate voltage vgate=vdrv_h-Vth of the field-effect power switch M0 (vdrv_h represents the Gate voltage of the high-level driving switch M1, vth represents the Gate-source voltage when the high-level driving switch M1 is in an on state and is a fixed value); the clamping unit U2 controls the voltage difference between the grid electrode of the high-level driving switch M1 and the source electrode of the field effect power switch M0 to be a clamping voltage Vclamp; when the field-effect power switch M0 is in the on state, since the source and the drain of the field-effect power switch M0 are connected in series with the inductance element, the current flowing through the field-effect power switch M0 gradually increases, and the source voltage of the field-effect power switch M0 (i.e., the voltage generated by the current flowing through the field-effect power switch M0 at the detection resistor R0) also gradually increases; under the action of the clamp unit U2, the gate voltage of the high-level driving switch M1 and the gate voltage of the field-effect power switch M0 vary with the source voltage of the field-effect power switch M0, so that the gate-source voltage Vgs of the field-effect power switch M0 is maintained at (Vclamp-Vth).
Fig. 3 shows a schematic diagram of a field effect power switch driving circuit according to another embodiment of the present utility model. As shown in fig. 3, the field effect power switch driving circuit 300 includes a driving control unit U1, a high level driving switch M1, a low level driving switch M2, and a clamp unit U2, wherein: the first and second output terminals of the drive control unit U1 are connected to the gate of the high-level drive switch M1 and the gate of the low-level drive switch M2, respectively; the drain of the high level driving switch M1 is connected to the in-circuit power supply PVDD, the source is connected to the drain of the low level driving switch M2 and is used to connect to the gate of the field effect power switch M0; the source electrode of the low-level driving switch M2 is grounded; the clamping unit U2 is configured to control a voltage difference between the gate and the source of the field-effect power switch M0 to be a second fixed value.
As shown in fig. 3, in some embodiments, the first terminal of the clamp unit U2 is connected to the drain of the high-level driving switch M1 and the drain of the low-level driving switch M2, and the second terminal is used to connect to the source of the field-effect power switch M0 and to be grounded via the detection resistor R0.
As shown in fig. 3, in some embodiments, the high-level driving switch M1 may be implemented as a P-type MOS field effect transistor, the low-level driving switch M2 may be implemented as an N-type MOS field effect transistor, and the clamping unit U2 may be implemented as a zener diode.
Fig. 4 shows waveforms of a plurality of signals associated with the field effect power switch driving circuit shown in fig. 3, wherein: PWM means a PWM control signal received from the outside by the field-effect power switch driving circuit 300 for controlling on and off of the high-level driving switch M1 and the low-level driving switch M2, gate means a Gate driving signal for controlling on and off of the field-effect power switch M0, CS means a source voltage detection signal of the field-effect power switch M0, vgs means a Gate-source voltage of the field-effect power switch M0.
As can be seen in conjunction with fig. 3 and 4, the specific operation of the field effect power switch driving circuit 300 is as follows: the drive control unit U1 receives a PWM control signal from the outside and generates a gate drive signal drv_h for the high-level drive switch M1 and a gate drive signal drv_l for the low-level drive switch M2 based on the PWM control signal; when the Gate driving signal drv_h is at a low level (i.e., the high-level driving switch M1 is in an on state) and the Gate driving signal drv_l is at a low level (i.e., the low-level driving switch M2 is in an off state), the Gate driving signal Gate is at a high level (i.e., the field-effect power switch M0 is in an on state), the Gate voltage vgate=vcs+vclamp of the field-effect power switch M0 (Vcs represents the source voltage of the field-effect power switch M0, vclamp represents the clamp voltage of the clamp unit U2); the clamping unit U2 controls the gate-source voltage of the field effect power switch M0 to be a clamping voltage Vclamp; when the field-effect power switch M0 is in the on state, since the source and the drain of the field-effect power switch M0 are connected in series with the inductance element, the current flowing through the field-effect power switch M0 gradually increases, and the source voltage of the field-effect power switch M0 (i.e., the voltage generated by the current flowing through the field-effect power switch M0 at the detection resistor R0) also gradually increases; under the action of the clamping unit U2, the gate voltage of the field-effect power switch M0 varies with the source voltage, so that the gate-source voltage of the field-effect power switch M0 is maintained at Vclamp.
The present utility model may be embodied in other specific forms without departing from its spirit or essential characteristics. The present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the utility model being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. The field effect power switch driving circuit is characterized by comprising a driving control unit, a high-level driving switch, a low-level driving switch and a clamping unit, wherein:
the first and second output terminals of the drive control unit are connected to the gate of the high-level drive switch and the gate of the low-level drive switch, respectively;
the drain electrode of the high-level driving switch is connected to an internal power supply of the circuit, the source electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch;
the source electrode of the low-level driving switch is grounded; and is also provided with
The clamping unit is used for controlling the voltage difference between the grid electrode of the high-level driving switch and the source electrode of the field effect power switch to be a fixed value.
2. The field effect power switch driving circuit according to claim 1, wherein a first terminal of the clamping unit is connected to a gate of the high level driving switch, a second terminal is for connection to a source of the field effect power switch and for grounding via a sense resistor.
3. The field effect power switch drive circuit of claim 2 wherein the high level drive switch and the low level drive switch are implemented as N-type metal oxide semiconductor field effect transistors.
4. The field effect power switch drive circuit of claim 2, wherein the clamping unit is implemented as a zener diode.
5. The field effect power switch drive circuit of claim 2 wherein the field effect power switch is in an on state when the high level drive switch is in an on state and the low level drive switch is in an off state.
6. The field effect power switch driving circuit is characterized by comprising a driving control unit, a high-level driving switch, a low-level driving switch and a clamping unit, wherein:
the first and second output terminals of the drive control unit are connected to the gate of the high-level drive switch and the gate of the low-level drive switch, respectively;
the source electrode of the high-level driving switch is connected to an internal power supply of the circuit, the drain electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch;
the source electrode of the low-level driving switch is grounded; and is also provided with
The clamping unit is used for controlling the voltage difference between the grid electrode and the source electrode of the field effect power switch to be a fixed value.
7. The field effect power switch driving circuit of claim 6, wherein a first terminal of the clamping unit is connected to a drain of the high level driving switch, a second terminal is for connection to a source of the field effect power switch and for grounding via a sense resistor.
8. The field effect power switch drive circuit of claim 7, wherein the high level drive switch is implemented as a pmos field effect transistor and the low level drive switch is implemented as an nmos field effect transistor.
9. The field effect power switch drive circuit of claim 7, wherein the clamping unit is implemented as a zener diode.
10. The field effect power switch drive circuit of claim 7 wherein the field effect power switch is in an on state when the high level drive switch is in an on state and the low level drive switch is in an off state.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320158815.7U CN219893305U (en) | 2023-01-31 | 2023-01-31 | Field effect power switch driving circuit |
| TW112204518U TWM645046U (en) | 2023-01-31 | 2023-05-09 | Field effect power switch drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320158815.7U CN219893305U (en) | 2023-01-31 | 2023-01-31 | Field effect power switch driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219893305U true CN219893305U (en) | 2023-10-24 |
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ID=88394670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320158815.7U Active CN219893305U (en) | 2023-01-31 | 2023-01-31 | Field effect power switch driving circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN219893305U (en) |
| TW (1) | TWM645046U (en) |
-
2023
- 2023-01-31 CN CN202320158815.7U patent/CN219893305U/en active Active
- 2023-05-09 TW TW112204518U patent/TWM645046U/en unknown
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| Publication number | Publication date |
|---|---|
| TWM645046U (en) | 2023-08-11 |
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