CN219695199U

CN219695199U - Chip testing device

Info

Publication number: CN219695199U
Application number: CN202320613650.8U
Authority: CN
Inventors: 付研; 丁育林
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2023-03-24
Filing date: 2023-03-24
Publication date: 2023-09-15
Anticipated expiration: 2033-03-24

Abstract

The utility model provides a chip testing device, which comprises: the bearing device comprises a first cover plate, a second cover plate and a first cover plate, wherein a bearing part and hollowed-out parts positioned on two sides of the bearing part are arranged on the first cover plate, and a working surface of the bearing part is provided with a plurality of contact points; the base plate is arranged on the first cover plate in operation, a plurality of direct-insert pins and test points which are electrically connected with each other are arranged on the base plate, the direct-insert pins penetrate through the hollowed-out parts in operation, and the test points are electrically connected with the contact points; the second cover plate is arranged on the substrate and is used for jointly fixing and clamping the substrate with the first cover plate in a working mode, a fixing portion and a hollow-out structure are arranged on the second cover plate, the fixing portion is located on the substrate to fix the substrate, and the first portion of the hollow-out structure corresponds to the hollow-out portion. The utility model provides a chip testing device which can avoid sample loss during testing and improve testing efficiency.

Description

Chip testing device

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a chip testing device.

Background

At present, in order to shorten the packaging period and reduce the cost, a COB (chip on board) wire bonding mode is generally used for connecting a chip with a substrate, and pins on the substrate are connected with a test board in a plugging mode for testing. The FT (final test) test requires manual replacement of samples, and for products with more signal pins (more than 100), multiple pins are required to be simultaneously aligned and inserted into corresponding clamping grooves and then fixed, so that the sample loading time is long, and the test efficiency is low.

In the FT test process, frequent sample insertion and extraction is needed, the loading alignment difficulty of samples with multiple pins is high, the pins are easy to bend, deform and even drop due to insertion and extraction dislocation, the samples are lost, and inconvenience is brought to the test.

Therefore, it is necessary to provide a more efficient and reliable chip testing device, which avoids sample loss during testing and improves testing efficiency.

Disclosure of Invention

The utility model provides a chip testing device which can avoid sample loss during testing and improve testing efficiency.

One aspect of the present utility model provides a chip testing apparatus comprising: the bearing device comprises a first cover plate, a second cover plate and a first cover plate, wherein a bearing part and hollowed-out parts positioned on two sides of the bearing part are arranged on the first cover plate, and a working surface of the bearing part is provided with a plurality of contact points; the base plate is arranged on the first cover plate in operation, a plurality of direct-insert pins and test points which are electrically connected with each other are arranged on the base plate, the direct-insert pins penetrate through the hollowed-out parts in operation, and the test points are electrically connected with the contact points; the second cover plate is arranged on the substrate and is used for jointly fixing and clamping the substrate with the first cover plate in a working mode, a fixing portion and a hollow-out structure are arranged on the second cover plate, the fixing portion is located on the substrate to fix the substrate, and the first portion of the hollow-out structure corresponds to the hollow-out portion.

In some embodiments of the present utility model, the first cover plate and the second cover plate are fixed by means of a snap-fit connection.

In some embodiments of the present utility model, a first clamping groove is further formed at two ends of the first cover plate, a second clamping groove corresponding to the first clamping groove is further formed at two ends of the second cover plate, and the first cover plate and the second cover plate are fixed by clamping the first clamping groove and the second clamping groove through a buckle.

In some embodiments of the present utility model, the middle portion of the substrate further includes a wire bonding area for packaging a chip, where the chip is electrically connected to the plurality of in-line pins and the test points at the same time.

In some embodiments of the present utility model, the middle portion of the substrate further includes a wire bonding protective cover covering the wire bonding area for protecting the wire bonding area.

In some embodiments of the present utility model, the second portion of the hollowed-out structure corresponds to the wire bonding protection cover and is configured to accommodate the wire bonding protection cover.

In some embodiments of the utility model, the hollowed-out portion is an elongated structure penetrating through the first cover plate.

In some embodiments of the present utility model, the hollow structure is an H-shaped structure penetrating through the second cover plate, two long sides of the H-shape located at two sides are the first portion, and a short transverse of the H-shape located at the middle is the second portion.

In some embodiments of the utility model, the sum of the thickness of the carrier and the thickness of the substrate is equal to the thickness of the first cover plate.

In some embodiments of the utility model, the thickness of the second cover plate is the same as the thickness of the wire bonding protective cover.

The utility model provides a chip testing device, wherein a test point and a direct plug pin are simultaneously arranged on a substrate, and a contact point on a first cover plate is connected with the test points for signal transmission, so that the plug step in FT test is eliminated; because the product still needs to be subjected to aging test through the direct plug pin, the direct plug pin still remains, and the direct plug pin is positioned at the hollowed-out part, so that the direct plug pin can be exposed and not touched, the sample loss caused during the test can be avoided, and the test efficiency is improved.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present utility model. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the utility model, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale. Wherein:

fig. 1 to fig. 4 are schematic structural diagrams of a chip testing device according to an embodiment of the utility model;

fig. 5 is a schematic structural diagram of a substrate in a chip testing apparatus according to an embodiment of the utility model.

Detailed Description

The following description provides specific applications and requirements of the utility model to enable any person skilled in the art to make and use the utility model. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the utility model. Thus, the present utility model is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical scheme of the utility model is described in detail below with reference to the examples and the accompanying drawings.

In some methods, the efficiency of testing is improved by changing the form of the package, simplifying the manual operation steps. For example, the packaging form is changed into BGA, the sample is directly put into the socket during testing, the design of grooves around the socket is consistent with the size of the sample, and accurate positioning is realized, so that the solder balls at the bottom of the sample are in one-to-one correspondence with the test points on the socket, and a great amount of time alignment is not required for testers. However, although the packaging mode is good, the substrate needs to be specially designed and customized, the packaging period is long, and the cost is high. Against our original intent to quickly package. In other methods, the pin damage is avoided by reducing the number of the pins, but this reduces the test capacity and reduces the test efficiency.

In summary, there is currently no solution that can improve the testing efficiency and testing capacity, and avoid the substrate damage. Based on the above, in order to reduce the frequent pin plugging and unplugging in the FT test, reduce the damage to the sample and improve the test efficiency, the utility model provides a chip test device which meets the test requirement of products within 150 signal numbers. The utility model provides a chip testing device, wherein a test point and a direct plug pin are simultaneously arranged on a substrate, and a contact point on a first cover plate is connected with the test points for signal transmission, so that the plug step in FT test is eliminated; because the product still needs to be subjected to aging test through the direct plug pin, the direct plug pin still remains, and the direct plug pin is positioned at the hollowed-out part, so that the direct plug pin can be exposed and not touched, the sample loss caused during the test can be avoided, and the test efficiency is improved.

Fig. 1 to fig. 4 are schematic structural diagrams of a chip testing device according to an embodiment of the utility model. Fig. 1 is a schematic structural diagram of a first view angle of a chip testing device according to an embodiment of the present utility model; FIG. 2 is a schematic diagram of a second view angle of a chip testing apparatus according to an embodiment of the present utility model;

FIG. 3 is a top view of a chip testing apparatus according to an embodiment of the utility model; fig. 4 is a longitudinal section view of the chip testing apparatus according to the embodiment of the present utility model taken along G-G in fig. 3. Fig. 5 is a schematic structural diagram of a substrate in a chip testing apparatus according to an embodiment of the utility model.

The structure of the chip testing apparatus according to the embodiment of the utility model will be described in detail with reference to the accompanying drawings.

An embodiment of the present utility model provides a chip testing apparatus 100, as shown in fig. 1 to 5, including: the first cover plate 110, the first cover plate 110 is provided with a bearing part 111 and hollowed-out parts 112 positioned at two sides of the bearing part 111, and the working surface of the bearing part 111 is provided with a plurality of contact points; the base plate 120 is arranged on the first cover plate 110 in operation, a plurality of direct-insert pins 121 and test points 122 which are electrically connected with each other are arranged on the base plate 120, and when in operation, the direct-insert pins 121 penetrate through the hollowed-out parts 112, and the test points 122 are electrically connected with the contact points; the second cover plate 130 is arranged on the substrate 120 and is fixedly clamped with the first cover plate 110 together during operation, a fixing portion 131 and a hollow structure 132 are arranged on the second cover plate 130, the fixing portion 131 is positioned on the substrate 120 to fix the substrate 120, and a first portion 132a of the hollow structure 132 corresponds to the hollow portion 112.

Referring to fig. 2, the chip testing apparatus 100 includes: the first cover plate 110, a bearing portion 111 and hollow portions 112 located at two sides of the bearing portion 111 are disposed on the first cover plate 110, and a working surface of the bearing portion 111 is provided with a plurality of contact points (the plurality of contact points are located on a front surface of the first cover plate 110 and face one surface of the substrate, and are not shown in the figure).

As shown in fig. 4, the carrying portion 111 is used for carrying the substrate 120. In some embodiments of the present utility model, the sum of the thickness of the bearing 111 and the thickness of the substrate 120 is equal to the thickness of the first cover plate 110. This allows the substrate 120 to be just embedded in the first cover plate 110, and the upper surface of the substrate 120 is flush with the upper surface of the first cover plate 110. The second cover 130 may be just pressed against the substrate 120, and the substrate 120 is fixed to prevent the substrate 120 from moving up and down.

Referring to fig. 2, in some embodiments of the utility model, the hollowed-out portion 112 is an elongated structure penetrating through the first cover plate 110. The hollow portion 112 is configured to pass through the in-line pins, so that the structure of the hollow portion 112 is equivalent to the overall structure of the in-line pins.

Referring to fig. 4 and 5, the chip testing apparatus 100 includes: the base plate 120 is operatively disposed on the first cover plate 110, a plurality of direct-insertion pins 121 and test points 122 that are electrically connected with each other are disposed on the base plate 120, and during operation, the plurality of direct-insertion pins 121 pass through the hollowed-out portion 112, and the plurality of test points 122 are electrically connected with the plurality of contact points.

In the technical scheme of the utility model, a plurality of test points 122 and direct-insert pins 121 are simultaneously arranged on a substrate 120, and the test points 122 and the direct-insert pins 121 are electrically connected with a chip (the test points 122 and the direct-insert pins 121 are connected in a PCB wiring mode). Therefore, the test can be carried out by adopting the test point according to the actual requirement or by adopting the direct plug pin. For example, the step of removing the plug pins in the FT test may be performed by performing signal transmission through the contact points on the first cover plate 110 and the connection between these test points; because the product still needs to be subjected to the aging test through the direct-insert pin, the direct-insert pin is still reserved, and the direct-insert pin is positioned at the hollowed-out part 112, so that the direct-insert pin can be exposed and not touched, the sample loss caused during the test can be avoided, and the test efficiency is improved.

Referring to fig. 5, in some embodiments of the present utility model, the middle portion of the substrate 120 (the circular area located in the middle portion of the substrate 120 in fig. 5) further includes a wire bonding area 123 for packaging a chip, where the chip is electrically connected to the plurality of in-line pins and the test points at the same time.

Referring to fig. 4, in some embodiments of the present utility model, the middle portion of the substrate 120 further includes a wire-bonding protecting cover 124 covering the wire-bonding area 123, for protecting the wire-bonding area 123. Avoiding wire breakage or short circuit caused by false touch when manually replacing the sample.

In the technical scheme of the utility model, referring to fig. 5, two sides of a substrate 120 are provided with straight pins 121, two sides of metal test points 122 are provided near the middle area, and the straight pins 121 and the test points 122 are provided with PCB wiring. Therefore, the chip is connected to the back test point and the direct plug pin, and a dual-purpose structure is formed. When the FT test is needed to be frequently plugged and unplugged, the metal test point is used for connecting a test socket; when the burn-in test is performed, the BI board is connected by the in-line pins.

Referring to fig. 1, the chip testing apparatus 100 includes: the second cover plate 130 is arranged on the substrate 120 and is fixedly clamped with the first cover plate 110 together during operation, a fixing portion 131 and a hollow structure 132 are arranged on the second cover plate 130, the fixing portion 131 is positioned on the substrate 120 to fix the substrate 120, and a first portion 132a of the hollow structure 132 corresponds to the hollow portion 112.

Referring to fig. 1, 2 and 4, in some embodiments of the present utility model, the first cover plate 110 and the second cover plate 130 are fastened by means of a snap 140.

In some embodiments of the present utility model, a first clamping groove 113 is further provided at two ends of the first cover plate 110, a second clamping groove 133 corresponding to the first clamping groove 113 is further provided at two ends of the second cover plate 130, and the first cover plate 110 and the second cover plate 130 are fixed by clamping the first clamping groove 113 and the second clamping groove 133 through a buckle 140.

Referring to fig. 1, in some embodiments of the present utility model, the second portion 132b of the hollow structure 132 corresponds to the wire bonding protection cap 124, and is configured to accommodate the wire bonding protection cap 124.

In some embodiments of the present utility model, the hollowed-out structure 132 is an H-shaped structure penetrating through the second cover 130, two long sides of the H-shape are the first portion 132a, and a short transverse of the H-shape is the second portion 132b.

In some embodiments of the present utility model, the thickness of the second cover 130 is the same as the thickness of the wire bond protection cap 124.

The utility model can effectively reduce the number of plugging times during the direct plug pin test and reduce the pin damage. The utility model can simplify the difficulty of manual test and improve the test efficiency.

In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present utility model is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the utility model.

It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present utility model. Like reference numerals or like reference numerals designate like elements throughout the specification.

Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims

1. A chip testing apparatus, comprising:

the bearing device comprises a first cover plate, a second cover plate and a first cover plate, wherein a bearing part and hollowed-out parts positioned on two sides of the bearing part are arranged on the first cover plate, and a working surface of the bearing part is provided with a plurality of contact points;

the base plate is arranged on the first cover plate in operation, a plurality of direct-insert pins and test points which are electrically connected with each other are arranged on the base plate, the direct-insert pins penetrate through the hollowed-out parts in operation, and the test points are electrically connected with the contact points;

the second cover plate is arranged on the substrate and is used for jointly fixing and clamping the substrate with the first cover plate in a working mode, a fixing portion and a hollow-out structure are arranged on the second cover plate, the fixing portion is located on the substrate to fix the substrate, and the first portion of the hollow-out structure corresponds to the hollow-out portion.

2. The chip testing apparatus of claim 1, wherein the first cover plate and the second cover plate are secured by snap-fit engagement.

3. The chip testing device of claim 2, wherein the first cover plate is further provided with a first clamping groove at two ends, the second cover plate is further provided with a second clamping groove corresponding to the first clamping groove at two ends, and the first cover plate and the second cover plate are fixed by clamping the first clamping groove and the second clamping groove through a buckle.

4. The chip testing apparatus of claim 1, wherein the central portion of the substrate further comprises a wire bonding area for packaging a chip, the chip being electrically connected to the plurality of in-line pins and the test points simultaneously.

5. The chip testing apparatus of claim 4, wherein the middle portion of the substrate further comprises a wire-bonding protective cover covering the wire-bonding area for protecting the wire-bonding area.

6. The chip testing device of claim 5, wherein the second portion of the hollowed-out structure corresponds to the wire-bonding protection cap for accommodating the wire-bonding protection cap.

7. The device for testing a chip according to claim 1, wherein the hollow portion is a strip-shaped structure penetrating through the first cover plate.

8. The chip testing device of claim 6, wherein the hollow structure is an H-shaped structure penetrating through the second cover plate, two long sides of the H-shape located at two sides are the first portion, and a short transverse of the H-shape located at the middle is the second portion.

9. The chip testing apparatus of claim 1, wherein a sum of a thickness of the carrier portion and a thickness of the substrate is equal to a thickness of the first cover plate.

10. The chip testing apparatus of claim 5, wherein a thickness of the second cover plate is the same as a thickness of the wire bonding protective cover.