CN219678438U - Anti-backflow circuit and electronic equipment - Google Patents
Anti-backflow circuit and electronic equipment Download PDFInfo
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- CN219678438U CN219678438U CN202320681775.4U CN202320681775U CN219678438U CN 219678438 U CN219678438 U CN 219678438U CN 202320681775 U CN202320681775 U CN 202320681775U CN 219678438 U CN219678438 U CN 219678438U
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- 230000002265 prevention Effects 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims description 21
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000012423 maintenance Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 8
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 35
- 238000010586 diagram Methods 0.000 description 4
- 238000007599 discharging Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 1
Abstract
The utility model discloses a backflow prevention circuit and electronic equipment, comprising: the first switching circuit is connected between the first power input end and the power output end and comprises a first switching tube and a second switching tube which are connected in series; the second switching circuit is connected between the second power input end and the power output end and comprises a third switching tube which is communicated with the first switching tube and the second switching tube; the delay circuit is connected between the second switching tube and the second switching circuit; when the first power input end and the second power input end are both input with power signals, the second switch circuit can charge the delay circuit; when the power supply signal is switched from the second power supply input end to the first power supply input end, the delay circuit can supply power for the second switching tube, so that the second switching tube is conducted in a delay mode relative to the first switching tube, and current of the first power supply input end is prevented from reversely flowing to the second power supply input end in the switching process.
Description
Technical Field
The present utility model relates to the field of electronic circuits, and in particular, to an anti-backflow circuit and an electronic device.
Background
With the high-speed development of electronic products, more and more electronic devices adopt a multi-interface and multi-channel voltage power supply mode so as to meet the use requirements of different occasions. For example, an electronic device with a DC port and a USB interface is provided, the DC port is connected to the power adapter to supply power, and the USB interface can also be used as a power input terminal of the electronic device.
In the related art, when the first path of input power supply is switched to the second path of input power supply, the residual voltage of the load is released, so that the load voltage is reduced, the first path of input power supply still maintains a short-term conduction state, and the current of the second path of input power supply easily flows to the first path of input power supply, so that the problem of current backflow occurs, and the stability of the circuit is affected.
Disclosure of Invention
The embodiment of the utility model provides a backflow prevention circuit and electronic equipment, which are used for solving the problem of backflow of current during switching of two paths of input power supplies in the prior art.
The embodiment of the utility model provides a backflow prevention circuit, which comprises:
the first switching circuit is connected between the first power input end and the power output end and comprises a first switching tube and a second switching tube which are connected in series;
the second switching circuit is connected between a second power input end and the power output end and comprises a third switching tube which is connected with the second switching tube;
the delay circuit is connected between the second switching tube and the second switching circuit;
when the first power input end and the second power input end both input power signals, the first switching tube and the second switching tube are turned off, and the third switching tube is turned on, so that the power signals of the second power input end can be transmitted to the power output end, and the second switching circuit can charge the delay circuit;
when the power signal is switched from the second power input terminal to the first power input terminal, the delay circuit can supply power to the second switching tube so as to enable the second switching tube to be conducted relative to the first switch Guan Yanhou.
In some embodiments, the first switch tube is a first PMOS tube, the second switch tube is a second PMOS tube, the first switch circuit further includes a first resistor and a second resistor, a drain electrode of the first PMOS tube is connected to the first power input terminal, a source electrode of the first PMOS tube is connected to a source electrode of the second PMOS tube, and a gate electrode of the first PMOS tube is connected to the first power input terminal through the first resistor and is grounded by being pulled down by the second resistor; the drain electrode of the second PMOS tube is connected to the power output end, the grid electrode of the second PMOS tube is connected with the delay circuit, and when a power supply signal is switched from the second power input end to the first power input end, the delay circuit can supply power to the second PMOS tube so that the grid electrode of the second PMOS tube maintains high level and is conducted in a delayed mode.
In some embodiments, the delay circuit includes a first capacitor and a third resistor, one end of the first capacitor is connected to the third resistor and the gate of the second PMOS transistor, the other end of the first capacitor is grounded, and the other end of the third resistor is connected to the second power input end through the first resistor.
In some embodiments, the first switch circuit further includes a fourth resistor, one end of the fourth resistor is connected between the source of the first PMOS transistor and the source of the second PMOS transistor, and the other end of the fourth resistor is grounded.
In some embodiments, the second switching circuit further comprises a fourth switching tube connected with the third switching tube; when the power signal is switched from the second power input end to the first power input end, and the delay circuit finishes supplying power to the second switching tube, the third switching tube and the fourth switching tube are cut off, and the first switching tube and the second switching tube are conducted, so that the power signal of the first power input end can be transmitted to the power output end.
In some embodiments, the third switch tube is a third PMOS tube, the fourth switch tube is a fourth NMOS tube, the second switch circuit further includes a sixth resistor, a drain electrode of the third PMOS tube is connected to the second power input end, a source electrode of the third PMOS tube is connected to the power output end, a gate electrode of the third PMOS tube is connected to the drain electrode of the fourth NMOS tube, a gate electrode of the fourth NMOS tube is connected to the second power input end through the sixth resistor, and a source electrode of the fourth NMOS tube is grounded.
In some embodiments, the second switch circuit further includes a maintaining module, where the maintaining module is connected between the gate and the source of the third PMOS, and when the first power input end inputs a power signal, the maintaining module can maintain the gate and the source of the third PMOS at a high level, so that the third PMOS is turned off.
In some embodiments, the maintaining module includes a second capacitor and a fifth resistor that are disposed in parallel, and the second capacitor and the fifth resistor are respectively connected between the gate and the source of the third PMOS transistor.
In some embodiments, the second switching circuit further includes a seventh resistor, one end of the seventh resistor is connected to the sixth resistor and the gate of the fourth NMOS transistor, and the other end of the seventh resistor is grounded.
The embodiment of the utility model also provides electronic equipment, which comprises the anti-backflow circuit in any embodiment.
According to the anti-backflow circuit provided by the embodiment of the utility model, as the delay circuit is arranged between the second switching tube and the second switching circuit, when power signals are input to the first power input end and the second power input end, the first switching tube and the second switch Guan Jiezhi are connected, the third switching tube is connected, the power signals of the second power input end are transmitted to the power output end through the second switching circuit, and the second switching circuit can charge the delay circuit; when the power supply signal is switched from the second power supply input end to the first power supply input end, the delay circuit can supply power for the second switching tube so as to enable the second switching tube to be conducted in a delay mode relative to the first switching tube, and current of the first power supply input end is prevented from being reversely poured into the second power supply input end in the switching process; when the delay circuit finishes supplying power to the second switching tube, the third switch Guan Jiezhi and the second switching tube are turned on, and the power signal of the first power input end is transmitted to the power output end through the first switching circuit.
Drawings
Fig. 1 is a block diagram of a backflow prevention circuit according to an embodiment of the present utility model.
Fig. 2 is a schematic circuit diagram of an anti-backflow circuit according to an embodiment of the present utility model.
Detailed Description
The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are only some, but not all, embodiments of the utility model. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present utility model based on the embodiments of the present utility model.
The embodiment of the utility model provides a backflow prevention circuit, which is used for solving the problem of backflow of current during switching of two paths of input power supplies in the prior art. The following description will be made with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a block diagram of a backflow prevention circuit according to an embodiment of the present utility model. The anti-backflow circuit provided by the embodiment of the utility model comprises a first switch circuit 10, a second switch circuit 20 and a delay circuit 30. The first switching circuit 10 is connected between the first power input end Vin1 and the power output end Vout, and the first switching circuit 10 includes a first switching tube 11 and a second switching tube 12 connected in series; the second switching circuit 20 is connected between the second power input end Vin2 and the power output end Vout, the second switching circuit 20 includes a third switching tube 21, and the third switching tube 21 is connected with the second switching tube 12; the delay circuit 30 is connected between the second switching tube 12 and the second switching circuit 20.
When the first power input end Vin1 and the second power input end Vin2 are both input with power signals, the first switch tube 11 and the second switch tube 12 are turned off, the third switch tube 21 is turned on, the power signal of the second power input end Vin2 is transmitted to the power output end Vout through the second switch circuit 20, that is, the second power output end Vout provides power for the load, and the second switch circuit 20 can charge the delay circuit 30; when the power signal is switched from the second power input terminal Vin2 to the first power input terminal Vin1, the delay circuit 30 can supply power to the second switching tube 12, so that the second switching tube 12 is turned on after being delayed relative to the first switching tube 11, and the current of the first power input terminal Vin1 is prevented from being reversely fed to the second power input terminal Vin2 through the third switching tube 21 in the switching process; when the delay circuit 30 finishes supplying power to the second switching tube 12, the third switching tube 21 is turned off, the second switching tube 12 is turned on, and the power signal of the first power input terminal Vin1 is transmitted to the power output terminal Vout through the first switching circuit 10, that is, the first power output terminal Vin1 provides power to the load.
When the power signal is switched from the second power input terminal Vin2 to the first power input terminal Vin1, the load voltage drops due to the residual voltage of the load, and the third switch tube 21 still maintains a short-term on state. According to the utility model, by arranging the delay circuit 30, the delay circuit 30 can supply power to the second switching tube 12 so that the second switching tube 12 still maintains the cut-off state, and the current of the first power input end Vin1 is prevented from being reversely poured into the second power input end Vin2 in the switching process; after the residual voltage of the load is discharged, the third switching tube 21 is turned off, and the delay circuit 30 finishes supplying power to the second switching tube 12, at this time, the second switching tube 12 is turned on, and the power signal of the first voltage input end Vin1 can be transmitted to the power output end through the first switching tube 11 and the second switching tube 12.
Referring to fig. 1 in combination with fig. 2, fig. 2 is a schematic circuit diagram of a backflow prevention circuit according to an embodiment of the present utility model. The first switching tube 11 is a first PMOS tube Q1, and the second switching tube 12 is a second PMOS tube Q2. The first switch circuit 10 further includes a first resistor R1 and a second resistor R2, the drain electrode of the first PMOS transistor Q1 is connected to the first power input terminal Vin1, the source electrode of the first PMOS transistor Q1 is connected back to the source electrode of the second PMOS transistor Q2, the gate electrode of the first PMOS transistor is connected to the first power input terminal Vin1 through the first resistor R1 and grounded through the second resistor R2, the drain electrode of the second PMOS transistor Q2 is connected to the power output terminal Vout, and the gate electrode of the second PMOS transistor Q2 is connected to the delay circuit 30. When the power signal is switched from the second power input terminal Vin2 to the first power input terminal Vin1, the delay circuit 30 can supply power to the second PMOS transistor Q2, so that the gate of the second PMOS transistor Q2 maintains a high level and is turned on after delay.
In some embodiments, the delay circuit 30 includes a first capacitor C1 and a third resistor R3, one end of the first capacitor C1 is connected to the third resistor R3 and the gate of the second PMOS transistor Q2, the other end of the first capacitor C1 is grounded, and the other end of the third resistor R3 is connected to the second power input terminal Vin2 through the first resistor R1 and grounded through the second resistor R2.
The delay time of the delay circuit 30 is related to the capacity of the first capacitor C1 and the resistance of the third resistor R3, and the larger the capacity of the first capacitor C1 is, the larger the resistance of the third resistor R3 is, the longer the delay time is. Specifically, the delay time of the delay circuit 30 may be set according to the residual voltage discharging time of the load, that is, the resistance-capacitance parameters of the first capacitor C1 and the third resistor R3 are correspondingly adjusted according to the residual voltage discharging time of the load.
As shown in fig. 2, the first switch circuit 10 further includes a fourth resistor R4, one end of the fourth resistor R4 is connected between the source of the first PMOS transistor Q1 and the source of the second PMOS transistor Q2, and the other end of the fourth resistor R4 is grounded. It should be noted that, in the repeated switching process of the first PMOS transistor Q1 and the second PMOS transistor Q2, accumulated charges may be generated due to the parasitic capacitance, and the accumulated charges may be effectively discharged by setting the fourth resistor R4 between the source of the first PMOS transistor Q1 and the source of the second PMOS transistor Q2, so as to ensure the stable operation of the circuit.
In some embodiments, the second switching circuit 20 further includes a fourth switching tube 22, the fourth switching tube 22 is connected to the third switching tube 21, when the power signal is switched from the second power input terminal Vin2 to the first power input terminal Vin1, and the delay circuit 30 finishes supplying power to the second switching tube 12, the third switching tube 21 and the fourth switching tube 22 are turned off, and the first switching tube 11 and the second switching tube 12 are turned on, so that the power signal of the first power input terminal Vin1 can be transmitted to the power output terminal Vout.
The third switch tube 21 is a third PMOS tube Q3, the fourth switch tube 22 is a fourth NMOS tube Q4, the second switch circuit 20 further includes a sixth resistor R6, a drain electrode of the third PMOS tube Q3 is connected to the second power input terminal Vin2, a source electrode of the third PMOS tube Q3 is connected to the power output terminal Vout, a gate electrode of the third PMOS tube Q3 is connected to the drain electrode of the fourth NMOS tube Q4, a gate electrode of the fourth NMOS tube Q4 is connected to the second power input terminal Vin2 through the sixth resistor R6, and a source electrode of the fourth NMOS tube Q4 is grounded.
The second switch circuit 20 further includes a seventh resistor R7, one end of the seventh resistor R7 is connected to the sixth resistor R6 and the gate of the fourth NMOS transistor Q4, and the other end of the seventh resistor R7 is grounded. The sixth resistor R6 and the seventh resistor R7 form a voltage divider circuit, and the resistance values of the sixth resistor R6 and the seventh resistor R7 can be adjusted according to the on threshold voltage of the fourth NMOS transistor Q4.
When the voltage of the second power input terminal Vin2 reaches the conducting threshold voltage of the fourth NMOS transistor Q4 through the voltage division of the sixth resistor R6 and the seventh resistor R7, the gate of the fourth NMOS transistor Q4 keeps high level, the fourth NMOS transistor Q4 is conducted, the gate of the third NMOS transistor Q3 is pulled down to low level while the fourth NMOS transistor Q4 is conducted, the third NMOS transistor Q3 is conducted, and at this time, the power signal of the second power input terminal Vin2 is transmitted to the power output terminal Vout through the third NMOS transistor Q3. Meanwhile, the voltage of the second power input end Vin2 is supplied to the grid electrode of the first PMOS transistor Q1 through the first resistor R1, and is supplied to the grid electrode of the second PMOS transistor Q2 through the first resistor R1 and the third resistor R3, so that the grid electrode of the first PMOS transistor Q1 and the grid electrode of the second PMOS transistor Q2 maintain high level, the first PMOS transistor Q1 and the second PMOS transistor Q2 are cut off, and the current of the second power input end Vin2 can be prevented from flowing backwards to the first voltage input end Vin1.
In the embodiment of the present utility model, the second switch circuit 20 further includes a maintaining module 23, where the maintaining module 23 is connected between the gate and the source of the third PMOS transistor Q3, and when the first power input terminal Vin1 inputs a power signal, the maintaining module 23 can maintain the gate and the source of the third PMOS transistor Q3 at a high level, so as to cut off the third PMOS transistor Q3, and prevent the current of the first power input terminal Vin1 from being reversely fed to the second voltage input terminal Vin2 through the third PMOS transistor Q3.
The maintaining circuit comprises a second capacitor C2 and a fifth resistor R5 which are arranged in parallel, wherein the second capacitor C2 and the fifth resistor R5 are connected between the grid electrode and the source electrode of the third PMOS tube. When the first power input end Vin1 inputs a power signal, the second capacitor C2 and the fifth resistor R5 which are arranged in parallel can maintain the gate and the source of the third PMOS transistor Q3 to be at a high level, so that the third PMOS transistor Q3 is turned off, and the current of the first power input end Vin1 is prevented from flowing back to the second voltage input end Vin2 through the third PMOS transistor Q3.
In order to better understand the present utility model, the following describes the operation principle of the anti-backflow circuit according to the embodiment of the present utility model in detail with reference to fig. 1 and 2.
When the first power input end Vin1 has an input power signal and the second power input end Vin2 does not have an input power signal, the grid electrode of the first PMOS transistor Q1 and the grid electrode of the second PMOS transistor Q2 are pulled down to GND through the second resistor R2 and are at a low level, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned on, and at this time, the power signal of the first power input end Vin1 can be output to the power output end Vout through the first PMOS transistor Q1 and the second PMOS transistor Q2. Meanwhile, the second capacitor C2 and the fifth resistor R5 can maintain the gate and the source of the third PMOS transistor Q3 at high levels, so that the third PMOS transistor Q3 is turned off, and the current of the first power input terminal Vin1 is prevented from flowing back to the second voltage input terminal Vin2 through the third PMOS transistor Q3.
When the second power input end Vin2 has an input power signal and the first power input end Vin1 does not input the power signal, the voltage of the second power input end Vin2 reaches the conducting threshold voltage of the fourth NMOS transistor Q4 through the voltage division of the sixth resistor R6 and the seventh resistor R7, the grid electrode of the fourth NMOS transistor Q4 keeps high level, the fourth NMOS transistor Q4 is conducted, the grid electrode of the third NMOS transistor Q3 is pulled down to low level while the fourth NMOS transistor Q4 is conducted, the third NMOS transistor Q3 is conducted, and at the moment, the power signal of the second power input end Vin2 is transmitted to the power output end Vout through the third NMOS transistor Q3. Meanwhile, the voltage of the second power input end Vin2 makes the grid electrode of the first PMOS transistor Q1 be at a high level through the first resistor R1, and makes the grid electrode of the second PMOS transistor Q2 be at a high level through the first resistor R1 and the third resistor R3, and the first PMOS transistor Q1 and the second PMOS transistor Q2 are cut off, so that the current of the second power input end Vin2 is prevented from being reversely poured into the first voltage input end Vin1.
When the first power input end Vin1 and the second power input end Vin2 both input power signals, the voltage of the second power input end Vin2 makes the grid electrode of the first PMOS transistor Q1 be at a high level through the first resistor R1, and makes the grid electrode of the second PMOS transistor Q2 be at a high level through the first resistor R1 and the third resistor R3, the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned off, meanwhile, the voltage of the second power input end Vin2 reaches the turn-on threshold voltage of the fourth NMOS transistor Q4 through the voltage division of the sixth resistor R6 and the seventh resistor R7, the grid electrode of the fourth NMOS transistor Q4 is kept at a high level, the fourth NMOS transistor Q4 is turned on, the grid electrode of the third NMOS transistor Q3 is pulled down to be at a low level while the fourth NMOS transistor Q4 is turned on, and the power signals of the second power input end Vin2 are transmitted to the power output end Vout through the third NMOS transistor Q3.
When the second power input end Vin2 continues to input the power signal and the first power input end Vin1 stops inputting the power signal, the first PMOS transistor Q1 and the second PMOS transistor Q2 are still in the off state, the third PMOS transistor Q3 is still in the on state, and the power signal of the second power input end Vin2 is transmitted to the power output end Vout through the third NMOS transistor Q3.
When the first power input end Vin1 continues to input a power signal, the second power input end Vin2 stops inputting the power signal, the load voltage is reduced due to residual voltage of the load, the third PMOS tube Q3 still maintains a short-term conduction state, and when the second power input end Vin2 stops inputting the voltage signal, the grid electrode of the first PMOS tube Q1 is instantly pulled to be low level, the first PMOS tube Q1 is conducted, meanwhile, the first capacitor C1 supplies power to the grid electrode of the second PMOS tube Q2, the grid electrode of the second PMOS tube Q2 maintains high level, the second PMOS tube Q2 is cut off, and at the moment, the current of the first power input end Vin1 is prevented from being reversely poured to the second power input end Vin2 in the power switching process; after the residual voltage of the load is discharged, i.e. after the fourth NMOS tube Q4 cannot be conducted, the third PMOS tube Q3 is turned off, at this time, the second PMOS tube is conducted, and the power signal of the first voltage input end Vin1 can be transmitted to the power output end through the first PMOS tube Q1 and the second PMOS tube Q2.
It should be noted that, the present utility model has no voltage difference limitation on the first voltage input terminal Vin1 and the second voltage input terminal Vin2, and the anti-backflow circuit can still work normally even if the voltage values of the two power inputs are equal. When the voltage difference of the two paths of power inputs is larger than the conduction threshold voltage of the first PMOS tube Q1, only one path of high voltage is connected to the second power input end Vin2, and the other path of low voltage is connected to the first power input end Vin1, so that the normal operation of the backflow prevention circuit can be ensured.
The embodiment of the utility model also provides electronic equipment which is provided with at least two paths of input power supplies, wherein the electronic equipment comprises the anti-backflow circuit. In some embodiments, the electronic device may be a router, a set-top box, a portable notebook computer, a security device, etc., and the present utility model is not limited in particular.
In summary, in the anti-backflow circuit and the electronic device provided by the embodiments of the present utility model, since the delay circuit 30 is disposed between the second switching tube 12 and the second switching circuit 20, when the first power input end Vin1 and the second power input end Vin2 both input power signals, the first switching tube 11 and the second switching tube 12 are turned off, the third switching tube 21 is turned on, the power signals of the second power input end Vin2 are transmitted to the power output end Vout through the second switching circuit 20, and the second switching circuit 20 can charge the delay circuit 30; when the power signal is switched from the second power input terminal Vin2 to the first power input terminal Vin1, the delay circuit 30 can supply power to the second switching tube 12, so that the second switching tube 12 is turned on after being delayed relative to the first switching tube 11, and the current of the first power input terminal Vin1 is prevented from flowing back to the second power input terminal Vin2 in the switching process; after the delay circuit 30 finishes supplying power to the second switching tube 12, the third switching tube 21 is turned off, the second switching tube 12 is turned on, and the power signal of the first power input terminal Vin1 is transmitted to the power output terminal Vout through the first switching circuit 10.
In the description of the present utility model, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features.
The anti-backflow circuit and the electronic device provided by the embodiments of the present utility model are described in detail, and specific examples are applied to illustrate the principles and the implementation modes of the present utility model, and the description of the above embodiments is only used for helping to understand the method and the core idea of the present utility model; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the ideas of the present utility model, the present description should not be construed as limiting the present utility model in summary.
Claims (10)
1. A backflow prevention circuit, comprising:
the first switching circuit is connected between the first power input end and the power output end and comprises a first switching tube and a second switching tube which are connected in series;
the second switching circuit is connected between a second power input end and the power output end and comprises a third switching tube which is connected with the second switching tube;
the delay circuit is connected between the second switching tube and the second switching circuit;
when the first power input end and the second power input end both input power signals, the first switching tube and the second switching tube are turned off, and the third switching tube is turned on, so that the power signals of the second power input end can be transmitted to the power output end, and the second switching circuit can charge the delay circuit;
when the power signal is switched from the second power input terminal to the first power input terminal, the delay circuit can supply power to the second switching tube so as to enable the second switching tube to be conducted relative to the first switch Guan Yanhou.
2. The backflow prevention circuit of claim 1, wherein the first switch tube is a first PMOS tube, the second switch tube is a second PMOS tube, the first switch circuit further comprises a first resistor and a second resistor, a drain electrode of the first PMOS tube is connected to the first power input end, a source electrode of the first PMOS tube is connected to a source electrode of the second PMOS tube, and a gate electrode of the first PMOS tube is connected to the first power input end through the first resistor and is grounded through the second resistor; the drain electrode of the second PMOS tube is connected to the power output end, the grid electrode of the second PMOS tube is connected with the delay circuit, and when a power supply signal is switched from the second power input end to the first power input end, the delay circuit can supply power to the second PMOS tube so that the grid electrode of the second PMOS tube maintains high level and is conducted in a delayed mode.
3. The backflow prevention circuit according to claim 2, wherein the delay circuit comprises a first capacitor and a third resistor, one end of the first capacitor is connected with the third resistor and the grid electrode of the second PMOS tube, the other end of the first capacitor is grounded, and the other end of the third resistor is connected to the second power input end through the first resistor.
4. The anti-backflow circuit of claim 2, wherein the first switching circuit further comprises a fourth resistor, one end of the fourth resistor is connected between the source of the first PMOS transistor and the source of the second PMOS transistor, and the other end of the fourth resistor is grounded.
5. The anti-backflow circuit of claim 1, wherein the second switching circuit further comprises a fourth switching tube, the fourth switching tube connected to the third switching tube; when the power signal is switched from the second power input end to the first power input end, and the delay circuit finishes supplying power to the second switching tube, the third switching tube and the fourth switching tube are cut off, and the first switching tube and the second switching tube are conducted, so that the power signal of the first power input end can be transmitted to the power output end.
6. The backflow prevention circuit of claim 5, wherein the third switch tube is a third PMOS tube, the fourth switch tube is a fourth NMOS tube, the second switch circuit further comprises a sixth resistor, a drain electrode of the third PMOS tube is connected to the second power input end, a source electrode of the third PMOS tube is connected to the power output end, a gate electrode of the third PMOS tube is connected to a drain electrode of the fourth NMOS tube, a gate electrode of the fourth NMOS tube is connected to the second power input end through the sixth resistor, and a source electrode of the fourth NMOS tube is grounded.
7. The anti-backflow circuit of claim 6, wherein the second switching circuit further comprises a maintaining module, the maintaining module is connected between the gate and the source of the third PMOS transistor, and when the first power input terminal inputs a power signal, the maintaining module can maintain the gate and the source of the third PMOS transistor at a high level, so that the third PMOS transistor is turned off.
8. The anti-backflow circuit of claim 7, wherein the maintenance module comprises a second capacitor and a fifth resistor arranged in parallel, and the second capacitor and the fifth resistor are respectively connected between the gate and the source of the third PMOS transistor.
9. The anti-backflow circuit of claim 6, wherein the second switching circuit further comprises a seventh resistor, one end of the seventh resistor is connected to the sixth resistor and the gate of the fourth NMOS transistor, and the other end of the seventh resistor is grounded.
10. An electronic device comprising the anti-backflow circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320681775.4U CN219678438U (en) | 2023-03-29 | 2023-03-29 | Anti-backflow circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320681775.4U CN219678438U (en) | 2023-03-29 | 2023-03-29 | Anti-backflow circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219678438U true CN219678438U (en) | 2023-09-12 |
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ID=87928916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320681775.4U Active CN219678438U (en) | 2023-03-29 | 2023-03-29 | Anti-backflow circuit and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219678438U (en) |
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2023
- 2023-03-29 CN CN202320681775.4U patent/CN219678438U/en active Active
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