CN113109738B - Power-down time detection circuit and power-down time detection system - Google Patents
Power-down time detection circuit and power-down time detection system Download PDFInfo
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- CN113109738B CN113109738B CN202110274779.6A CN202110274779A CN113109738B CN 113109738 B CN113109738 B CN 113109738B CN 202110274779 A CN202110274779 A CN 202110274779A CN 113109738 B CN113109738 B CN 113109738B
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Abstract
The invention discloses a power-down time detection circuit and a power-down time detection system. The power-down time detection circuit specifically comprises a charging branch, a discharging branch, a power storage unit and an output branch. The charging branch is electrically connected with the electricity storage unit, charges the electricity storage unit when receiving a power-down signal, and stops charging the electricity storage unit when receiving a power-up signal; the discharging branch is electrically connected with the electricity storage unit and discharges electricity for the electricity storage unit; the output branch circuit is electrically connected with the power storage unit, and the power-down time detection circuit judges whether the power-down time exceeds the preset duration according to the residual electric quantity of the power storage unit and outputs a corresponding level signal. According to the invention, by judging the logic level output by the output branch, whether the delay time from the last power-down to the current power-up meets the design requirement is judged, and under the condition that the user requirement is not met, the controller takes corresponding measures to avoid the risk of motor burning caused by the fact that the time for repeatedly powering up and down the driver is too short.
Description
Technical Field
The invention relates to the field of servo motor control, in particular to a power-down time detection circuit and a power-down time detection system.
Background
Along with the continuous upgrading of industrial field environments, the requirements on the safety and reliability of industrial application fields are also higher and higher. When the servo driver is operated with a servo motor, the motor overload or traffic jam and other application conditions often occur, and under these conditions, if the time interval of repeated power-on and power-off of the driver is too short, the risk of burning out the servo motor exists. At present, no specific technical solution is available for solving the above problems in the existing servo system application.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides the power-down time detection circuit which can detect the power-down time of the driver and output a corresponding driver control signal according to the power-down time, thereby solving the problem of motor burnout caused by repeated power-up and power-down of the driver.
In a first aspect, an embodiment of the present invention provides a power-down time detection circuit, including a charging branch, a discharging branch, a power storage unit, and an output branch; wherein:
the charging branch is electrically connected with the electricity storage unit, charges the electricity storage unit when receiving a power-down signal, and stops charging the electricity storage unit when receiving a power-up signal; the discharging branch is electrically connected with the electricity storage unit and discharges electricity for the electricity storage unit; the output branch is electrically connected with the electricity storage unit; and the power-down time detection circuit judges whether the power-down time exceeds a preset duration according to the residual electric quantity of the power storage unit and outputs a corresponding level signal.
The power-down time detection circuit provided by the embodiment of the invention has at least the following beneficial effects: the method can detect whether the delay time of last power-down of the driver meets the specification requirement, so that corresponding response and related warning or logic processing can be made when the driver is powered up again, and the problem of motor burning caused by too short time interval of repeated power-up and power-down is avoided.
In the power-down time detection circuit of this embodiment, the charging branch includes a first switch branch, the first switch branch is connected in series between a first power supply and the power storage unit, and a control end of the first switch branch is electrically connected with an output end of the detection unit for detecting a power-on signal.
In the power failure time detection circuit of this embodiment, the power storage unit includes a first capacitor, and the first switch branch includes a first switch tube and a first current limiting resistor; the first switching tube, the first current limiting resistor and the first capacitor are sequentially connected in series between the first power supply and the reference ground, the control end of the first switching tube is electrically connected with the output end of the detection unit, and the connection point of the first current limiting resistor and the first capacitor forms an intermediate potential point.
In the power failure time detection circuit of this embodiment, the output branch includes a second switch branch, the second switch branch is connected in series between a second power supply and a detection end of the signal processing unit, and a control end of the second switch branch is electrically connected with the power storage unit;
when the electric quantity of the electricity storage unit is smaller than a preset value, the second switch branch is conducted, and the output branch outputs a level signal that the power-down time exceeds a preset duration; when the electric quantity of the electricity storage unit is larger than a preset value, the second switch branch is disconnected, and the output branch outputs a level signal that the power-down time does not exceed the preset duration.
In the power failure time detection circuit of this embodiment, the second switching branch includes a second switching tube, a second current limiting resistor, and a third current limiting resistor; the second switching tube and the second current limiting resistor are connected in series between the second power supply and the detection end of the signal processing unit, and the control end of the second switching tube is electrically connected with the intermediate potential point through the third current limiting resistor.
In the power-down time detection circuit of this embodiment, the discharge branch includes a first resistor; wherein the first resistor is connected in series between the intermediate potential point and a reference ground.
In the power-down time detection circuit of this embodiment, the charging branch further includes a second resistor, a third resistor, and a second capacitor; the second resistor is connected in series between the control end of the first switch tube and the output end of the detection unit, the first end of the third resistor is electrically connected with the connection point of the second resistor and the detection unit, the first end of the second capacitor is electrically connected with the connection point of the second resistor and the first switch tube, and the second end of the third resistor and the second end of the second capacitor are respectively connected with a reference ground.
In the power-down time detection circuit of this embodiment, the output branch further includes a fourth resistor, a third capacitor, and a fourth capacitor; the third capacitor is connected in series between the second power supply and the control end of the second switching tube, the first end of the fourth resistor is electrically connected with the output end of the second switching tube, the second end of the fourth resistor is connected with the reference ground, the first end of the fourth capacitor is electrically connected with the connection point of the second current limiting resistor and the signal processing unit, and the second end of the fourth capacitor is connected with the reference ground.
In the power failure time detection circuit of this embodiment, the first switching tube is a semiconductor triode; the second switching tube is a MOS tube.
In a second aspect, an embodiment of the present invention provides a power-down time detection system, including a signal processing unit, a detection unit, and a power-down time detection circuit according to the foregoing embodiment, where an output end of the detection unit is electrically connected to an input end of the power-down time detection circuit, and an output end of the power-down time detection circuit is electrically connected to a detection end of the signal processing unit, where the detection unit is configured to detect a working condition of a driver in real time, and output a power-down control signal to the power-down time detection circuit at an instant before the power-down of the driver; and the signal processing unit judges whether the power-down time of the driver exceeds a preset duration according to the level signal output by the power-down time detection circuit.
Drawings
FIG. 1 is a block diagram of a power down time detection circuit according to one embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a power down time detection circuit according to an embodiment of the present invention;
fig. 3 is a logic timing diagram of the power down time detection circuit of fig. 2 according to an embodiment.
Detailed Description
The conception and the technical effects produced by the present invention will be clearly and completely described in conjunction with the embodiments below to fully understand the objects, features and effects of the present invention. It is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present invention based on the embodiments of the present invention.
In the description of the embodiments of the present invention, if "several" is referred to, it means more than one, if "multiple" is referred to, it is understood that the number is not included if "greater than", "less than", "exceeding", and it is understood that the number is included if "above", "below", "within" is referred to. If reference is made to "first", "second" it is to be understood as being used for distinguishing technical features and not as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Referring to fig. 1, a block diagram of a power down time detection circuit according to an embodiment of the invention is shown. It specifically includes a charging branch 10, a discharging branch 30, a storage unit 20, and an output branch 40. The charging branch circuit 10 is electrically connected with the power storage unit 20, and charges the power storage unit 20 when receiving a power-down signal, and stops charging the power storage unit 20 when receiving a power-up signal; the discharging branch 30 is electrically connected with the electricity storage unit 20 and discharges electricity for the electricity storage unit 20; the output branch 40 is electrically connected to the power storage unit 20. The power-down time detection circuit of the embodiment judges whether the power-down time of the driver exceeds a preset duration according to the residual capacity of the power storage unit 20, and outputs a corresponding level signal
The power-down time detection circuit provided by the embodiment is mainly applied to repeated power-up control of a driver, the input end of the power-down time detection circuit of the embodiment is connected with the input end of the detection unit, the detection unit outputs a low level immediately before the power-down of the driver, namely, when the driver is powered up for the time, the signal received by the input end of the charging branch circuit 10 is low level, and at the moment, the charging branch circuit 10 is not conducted. Meanwhile, when the electric charge on the electricity storage unit 20 is the electric charge after the electricity storage unit 20 is charged by the power supply through the conducted charging branch circuit 10 when the driver is powered off last time, the electricity storage unit 20 discharges through the discharging branch circuit 30.
The preset duration is a minimum discharge time (or a minimum power-down time of the driver) set according to a discharge speed of the discharge circuit 30 and a stored power of the power storage unit 20, and in practical application, the discharge time of the discharge circuit 30 (i.e. the power-down time of the driver) is only greater than or equal to the preset duration, and the discharge circuit 30 can fully release the power. In this embodiment, assuming that the preset duration (the discharge time constant of the discharge branch 30) is 10s, if the last time the driver was powered down exceeds 10s (i.e. the power storage unit 20 releases enough power), when the driver is powered up this time, if the residual power or voltage on the power storage unit 20 is lower than the preset value, the output branch 40 is turned on and outputs a high level signal; if the last power-down time of the driver does not exceed 10s (i.e. the amount of power released by the power storage unit 20 is small), the power storage unit 20 is not completely discharged at this time, and the remaining power or voltage on the power storage unit 20 is higher than the preset value, the output branch 40 is disconnected and outputs a low level signal.
The signal processing unit in the driver judges whether the delay time from the last power-down to the current power-up meets the design requirement or not by judging the logic level output by the output branch 40, and under the condition that the user requirement is not met, the signal processing unit or the control center can perform corresponding processing, such as controlling the driver to keep a shutdown state, thereby avoiding the risk of motor burning caused by too short time of repeated power-up and power-down of the driver.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of an embodiment of a power-down time detection circuit according to the present invention. As shown in fig. 2, the charging branch 10 of the present embodiment includes a first switching branch, where the first switching branch is connected in series between the first power supply and the power storage unit 20, and a control end of the first switching branch is electrically connected to an output end of the detecting unit 50 for detecting a power-on signal. The output branch 40 includes a second switch branch, where the second switch branch is connected in series between the second power supply VCC2 and the detection end of the signal processing unit 60, and the control end of the second switch branch is electrically connected to the power storage unit 20. In this embodiment, when the electric quantity of the electricity storage unit 20 is smaller than a preset value, the second switch branch is turned on, and the output branch 40 outputs the level signal that the power-down time exceeds the preset duration; when the electric quantity of the electricity storage unit 20 is larger than the preset value, the second switch branch is opened, and the output branch 40 outputs a level signal that the power-down time does not exceed the preset time.
Specifically, the power storage unit 20 includes a first capacitor C1, and the first switching branch includes a first switching tube Q1 and a first current limiting resistor RS1. The first switching tube Q1, the first current limiting resistor RS1 and the first capacitor C1 are sequentially connected in series between the first power supply VCC1 and the reference ground, the control end of the first switching tube Q1 is electrically connected with the output end of the detection unit 50, and the connection point of the first current limiting resistor RS1 and the first capacitor C1 forms an intermediate potential point. The second switching branch comprises a second switching tube Q2, a second current limiting resistor RS2 and a third current limiting resistor RS3. The second switching tube Q2 and the second current limiting resistor RS2 are connected in series between the second power supply VCC2 and the detection end of the signal processing unit 60, and the control end of the second switching tube Q2 is electrically connected to the intermediate potential point through the third current limiting resistor RS3. The discharge branch 30 comprises a first resistor R1, the first resistor R1 being connected in series between the intermediate potential point and the reference ground. In this embodiment, in order to obtain a precise detection result, the first switching transistor Q1 is a semiconductor transistor; the second switching tube Q2 adopts a MOS tube.
The charging branch 10 of the present embodiment further includes a second resistor R2, a third resistor R3, and a second capacitor C1. The second resistor R2 is connected in series between the control end of the first switching tube Q1 and the output end of the detection unit 50, the first end of the third resistor R3 is electrically connected with the connection point between the second resistor R2 and the detection unit 50, the first end of the second capacitor C1 is electrically connected with the connection point between the second resistor R2 and the first switching tube Q1, and the second end of the third resistor R3 and the second end of the second capacitor C1 are respectively connected with the reference ground. The output branch 40 of the present embodiment further includes a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4. The third capacitor C3 is connected in series between the second power supply VCC2 and the control end of the second switching tube Q2, the first end of the fourth resistor R4 is electrically connected with the output end of the second switching tube Q2, the second end of the fourth resistor is connected with the reference ground, the first end of the fourth capacitor C4 is electrically connected with the connection point between the second current limiting resistor RS2 and the signal processing unit 60, and the second end of the fourth capacitor C4 is connected with the reference ground.
The schematic diagram of fig. 2 is analyzed in this embodiment in combination with the logic timing diagram of the power-down time detection circuit of fig. 3. In this embodiment, the discharging time constant of the first resistor R1 is designed to be 10s, as shown in fig. 3, when the driver is powered down (i.e. at time t2 and time t 6), the output terminal v_delay_control of the detection unit can output a low level at the moment (i.e. at time t1 and time t 5) before the power down of the driver, and in this embodiment, the time interval between t1 to t2 and between t5 and t6 is very small; when the driver is powered up again (i.e. at time t3 and time t 7), the output terminal v_delay_control of the detection unit outputs a high level instantaneously after being powered up. The invention can judge whether the power-down time of the driver is longer than the preset time according to the level signal output by the output end V_delay_MONITOR of the output branch circuit 40, if the power-down time of the driver is shorter than the preset time (for example, the time between t2 and t3 is shorter than 10 s), the V_delay_MONITOR outputs a low level; if the power-down time of the driver is longer than the preset time length(e.g., the duration between t6 and t7 is greater than 10 s), then v_delay_monitor outputs a high level. Specifically, in this embodiment, the first power supply VCC1 and the second power supply VCC2 are both 3.3V power supplies, when the driver is powered up this time (at time t3 or t 7), the signal output by the output terminal v_delay_control of the detection unit 50 is at a low level, at this time, the transistor Q1 is not turned on, and the charge on the first capacitor C1 is the charge after the capacitor is charged when the driver is powered down last time and the transistor Q1 is turned on. The first capacitor C1 discharges through the first resistor R1, if the last power-down time of the driver exceeds 10s (e.g., the duration between t6 and t7 in fig. 3 is longer than 10 s), that is, most of the electric quantity in the first capacitor C1 is released, so that when the driver is powered up this time, the voltage on the first capacitor C1 is lower than 2V (preset value), and the voltage on the MOS transistor Q2 is V GS With < -1.3V, the MOS transistor Q2 is conducted, and the output end V_delay_MONITOR of the output branch circuit 40 is at a high level; if the last power-down time of the driver does not exceed 10s (e.g., the duration between t2 and t3 in FIG. 3 is less than 10 s), the discharge of the first capacitor C1 is not completed, the voltage on the first capacitor C1 is higher than 2V, and the voltage on the MOS transistor Q2 is V GS > -1.3V, the MOS transistor Q2 is turned off, and the output terminal V_DELAY_MONITOR of the output branch 40 is low.
Therefore, in this embodiment, at the moment of powering up the driver, by determining the logic level output by the output terminal v_delay_monitor of the output branch 40, it is determined whether the DELAY time from the last power-down to the current power-up exceeds a preset duration, and when the current power-up is performed, corresponding logic control is performed. According to the embodiment, the MOS tube, the triode and the RC charge-discharge loop are adopted to form the power-down time detection circuit, so that the last power-down time of the driver can be detected in the repeated power-up application of the driver, a logic processing basis is provided for the power-up, the problem that the driver repeatedly powers up and down under the condition of too short power-down time is solved, and the risk of repeatedly powering up and down the motor is avoided.
An embodiment of the invention provides a power-down time detection system, which comprises a power supply, a signal processing unit, a detection unit and a power-down time detection circuit as shown in the corresponding embodiment of fig. 1-2. The power supply supplies power to the power-down time detection circuit, the output end of the detection unit is electrically connected with the input end of the power-down time detection circuit, the output end of the power-down time detection circuit is electrically connected with the detection end of the signal processing unit, and the detection unit is used for detecting the working condition of the driver in real time and outputting a power-down control signal to the power-down time detection circuit at the moment before the power of the driver is turned off; and the signal processing unit judges whether the power-down time of the driver exceeds a preset duration according to the level signal output by the power-down time detection circuit.
The power-down time detection system in this embodiment and the power-down time detection circuit in the corresponding embodiment of fig. 1-2 belong to the same concept, the specific implementation process is detailed in the corresponding embodiment, and the technical features in the embodiment are correspondingly applicable in the embodiment of the system, and are not repeated herein.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional units and modules according to needs. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention. Furthermore, embodiments of the invention and features of the embodiments may be combined with each other without conflict.
Claims (10)
1. The power-down time detection circuit is applied to a driver and is characterized by comprising a charging branch circuit, a discharging branch circuit, a power storage unit and an output branch circuit; wherein,,
the charging branch is electrically connected with the electricity storage unit, charges the electricity storage unit when receiving a power-on signal, and stops charging the electricity storage unit when receiving a power-off signal;
the discharging branch is electrically connected with the electricity storage unit and discharges the electricity storage unit when receiving a power-down signal;
the output branch circuit is electrically connected with the electricity storage unit, the output branch circuit comprises a second switch branch circuit, when the electric quantity of the electricity storage unit is smaller than a preset value, the second switch branch circuit is conducted, and the output branch circuit outputs a level signal that the power-down time exceeds a preset duration; when the electric quantity of the electricity storage unit is larger than a preset value, the second switch branch is disconnected, and the output branch outputs a level signal that the power-down time does not exceed the preset duration.
2. The power down time detection circuit according to claim 1, wherein the charging branch comprises a first switching branch, the first switching branch is connected in series between a first power supply and the power storage unit, and a control end of the first switching branch is electrically connected with an output end of the detection unit for detecting a power-on signal.
3. The power down time detection circuit of claim 2, wherein the power storage unit comprises a first capacitor, and the first switching branch comprises a first switching tube and a first current limiting resistor; the first switching tube, the first current limiting resistor and the first capacitor are sequentially connected in series between the first power supply and the reference ground, the control end of the first switching tube is electrically connected with the output end of the detection unit, and the connection point of the first current limiting resistor and the first capacitor forms an intermediate potential point.
4. A power down time detection circuit according to claim 3, wherein the second switching branch is connected in series between a second power supply and a detection end of the signal processing unit, and a control end of the second switching branch is electrically connected to the power storage unit.
5. The power down time detection circuit of claim 4, wherein the second switching leg comprises a second switching tube, a second current limiting resistor, and a third current limiting resistor; the second switching tube and the second current limiting resistor are connected in series between the second power supply and the detection end of the signal processing unit, and the control end of the second switching tube is electrically connected with the intermediate potential point through the third current limiting resistor.
6. The power down time detection circuit of claim 5, wherein the discharge leg comprises a first resistor; wherein the first resistor is connected in series between the intermediate potential point and a reference ground.
7. The power down time detection circuit of claim 6, wherein the charging branch further comprises a second resistor, a third resistor, and a second capacitor; the second resistor is connected in series between the control end of the first switch tube and the output end of the detection unit, the first end of the third resistor is electrically connected with the connection point of the second resistor and the detection unit, the first end of the second capacitor is electrically connected with the connection point of the second resistor and the first switch tube, and the second end of the third resistor and the second end of the second capacitor are respectively connected with a reference ground.
8. The power down time detection circuit of claim 7, wherein the output branch further comprises a fourth resistor, a third capacitor, and a fourth capacitor; the third capacitor is connected in series between the second power supply and the control end of the second switching tube, the first end of the fourth resistor is electrically connected with the output end of the second switching tube, the second end of the fourth resistor is connected with the reference ground, the first end of the fourth capacitor is electrically connected with the connection point of the second current limiting resistor and the signal processing unit, and the second end of the fourth capacitor is connected with the reference ground.
9. The power down time detection circuit according to any one of claims 5 to 8, wherein the first switching tube is a semiconductor transistor; the second switching tube is a MOS tube.
10. The power-down time detection system is characterized by comprising a signal processing unit, a detection unit and a power-down time detection circuit as claimed in any one of claims 1-9, wherein the output end of the detection unit is electrically connected with the input end of the power-down time detection circuit, the output end of the power-down time detection circuit is electrically connected with the detection end of the signal processing unit, and the detection unit is used for detecting the working condition of a driver in real time and outputting a power-down control signal to the power-down time detection circuit at the moment before the power-down of the driver; and the signal processing unit judges whether the power-down time of the driver exceeds a preset duration according to the level signal output by the power-down time detection circuit.
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| CN112259146A (en) * | 2020-10-15 | 2021-01-22 | 深圳安捷丽新技术有限公司 | Power-down protection circuit, data storage device and power-down protection method |
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| CN113109738A (en) | 2021-07-13 |
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