CN112259146A - Power-down protection circuit, data storage device and power-down protection method - Google Patents
Power-down protection circuit, data storage device and power-down protection method Download PDFInfo
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- CN112259146A CN112259146A CN202011103952.8A CN202011103952A CN112259146A CN 112259146 A CN112259146 A CN 112259146A CN 202011103952 A CN202011103952 A CN 202011103952A CN 112259146 A CN112259146 A CN 112259146A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
- H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
- H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
- H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/50—Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors
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Abstract
The utility model relates to a data storage technical field, a power down protection circuit, data storage device and power down protection method is provided, working voltage and the capacity of electric capacity management circuit acquisition electric capacity of solid state drive are monitored in real time through power detection circuit, make power control circuit according to electric capacity of electric capacity storage capacitor, control the input power and charge to electric capacity storage capacitor, and judge when the solid state drive appears losing electricity, trigger the power down protection mechanism, and adopt corresponding storage mode to preserve data in combination with electric capacity of electric capacity storage capacitor, thereby the validity of electric quantity of electric capacity storage capacitor has been guaranteed, the realization is adopted different strategies to writing in of data, the biggest possible is deposited in the conversion table of abundant user data and data page under the capacity condition of limited electric capacity.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a power down protection circuit, a data storage device, and a power down protection method.
Background
At present, for a Solid State Drive (SSD) to store data when power failure occurs, a capacitor is usually added on a board of the SSD. When the SSD system detects a power-down signal, the SSD is powered through the capacitor, so that data transmitted to the SSD by the host or a data page table of the SSD is written into a Flash memory as much as possible.
However, if the power signal is not detected accurately, the firmware of the SSD may enter the power-down process erroneously, which may result in a series of error processes (for example, when the power is detected to be abnormal, the device controller and the hardware controller may disconnect from the system bus, or even directly drop the disk). In addition, if the applied capacitor has insufficient power, the mapping table of the user data or data page stored in the cache is lost.
Therefore, the conventional solid state drive power-down technology has the problem that the mapping table of the user data or the data pages stored in the cache is lost when the system is powered down.
Disclosure of Invention
The application aims to provide a power failure protection circuit, a data storage device and a power failure protection method, and aims to solve the problem that in the existing solid state drive power failure technology, when a system is powered off, a mapping table of user data or data pages stored in a cache is lost.
The first aspect of the embodiment of the application provides a power-down protection circuit, is applied to solid state drive, be equipped with a storage capacitor on solid state drive's the integrated circuit board, power-down protection circuit includes:
a power supply detection circuit configured to monitor an operating voltage of the solid state drive in real time and output a first feedback signal;
the capacitance management circuit is connected with the storage capacitor and is configured to acquire the capacity of the storage capacitor and perform feedback; and
and the power supply control circuit is connected with an input power supply, the power supply detection circuit and the capacitor management circuit, is configured to control the input power supply to charge the storage capacitor according to the capacity of the storage capacitor, judges that a power failure protection mechanism is triggered when the solid-state drive is powered down according to the first feedback signal, and stores the user data or the mapping table of the data page in the cache in a corresponding storage mode by combining the capacity of the storage capacitor.
Therefore, the effectiveness of the electric quantity of the storage capacitor is ensured, different strategies are adopted for data writing, and enough conversion tables of user data and data pages are stored under the condition of limited capacity of the capacitor as far as possible.
In one embodiment, the method further comprises:
the capacitor tripping circuit is connected with the power supply detection circuit, the power supply control circuit and the storage capacitor, and is configured to judge whether the solid-state driver generates an instant voltage tripping phenomenon or not and output a second feedback signal;
the power supply control circuit is further configured to trigger the power-down protection mechanism when the solid-state drive is judged to be instantaneously powered down according to the second feedback signal. The capacitor trip circuit is arranged in the embodiment, so that the power failure misjudgment operation caused by instant voltage jump can be effectively prevented.
In one embodiment, the power detection circuit includes:
the LED driving circuit comprises a double operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a first LED and a second LED;
a first end of the first resistor and a first positive input end of the dual operational amplifier are connected to the input power supply, a first end of the second resistor and a first end of the first capacitor and a first negative input end of the dual operational amplifier are connected in common, a second end of the first resistor and a second end of the first capacitor are connected to ground, a second end of the second resistor, a first output end of the dual operational amplifier, a second positive input end of the dual operational amplifier and a first end of the second capacitor are connected in common, a first end of the third resistor and a first end of the fourth resistor and a second negative input end of the dual operational amplifier are connected in common, a second end of the third resistor, a first end of the fifth resistor, an anode of the first light emitting diode and a second output end of the dual operational amplifier are connected in common, a second end of the fifth resistor is connected to an anode of the second light emitting diode, the second end of the second capacitor, the second end of the fourth resistor, the cathode of the first light emitting diode and the cathode of the second light emitting diode are grounded. This embodiment defines a specific circuit configuration of the power supply detection circuit.
In one embodiment, the capacitance management circuit is implemented using a multivibrator. This embodiment specifically defines the type selection characteristic of the capacitance management circuit.
In one embodiment, the power control circuit is implemented by a single chip microcomputer. This embodiment defines in particular the model selection characteristic of the power supply control circuit.
A second aspect of the embodiments of the present application provides a data storage device, which is applied to a solid-state drive, where a board card of the solid-state drive is provided with an electric storage capacitor, and the data storage device includes:
an input power source configured to power the solid state drive; and
such as the power down protection circuit described above.
The data storage device realizes the optimized protection of data when the solid state drive is in power failure (normal power failure and abnormal power failure), stores the data of a user or a mapping table of data pages into a reliable Flash storage chip as far as possible, and can enable the solid state drive to smoothly read back the data in the power failure when the solid state drive is started next time.
A third aspect of the embodiments of the present application provides a power-down protection method, which is applied to a solid-state drive, where a board card of the solid-state drive is provided with a storage capacitor, and the power-down protection method includes:
monitoring the working voltage of the solid-state driver in real time and outputting a first feedback signal;
acquiring the capacity of the storage capacitor and feeding back the capacity;
controlling an input power supply to charge the storage capacitor according to the capacity of the storage capacitor;
and judging whether the solid state drive has power failure according to the first feedback signal, triggering a power failure protection mechanism when the solid state drive has power failure, and storing the mapping table of the user data or the data page in the cache in a corresponding storage mode by combining the capacity of the storage capacitor. The power-down protection method ensures the effectiveness of the electric quantity of the storage capacitor, realizes that different strategies are adopted for writing data, and stores enough user data and conversion tables of data pages under the condition of limited capacity of the capacitor as far as possible.
In one embodiment, the saving data in a corresponding storage mode in combination with the capacity of the storage capacitor includes:
when the capacity of the storage capacitor exceeds a preset electric quantity value, a three-layer type storage (TLC) mode is adopted to store user data or a mapping table of data pages in a cache;
and when the capacity of the storage capacitor is lower than a preset electric quantity value, storing the user data or the mapping table of the data page in the cache in a Single-Level Cell (SLC) mode. The embodiment specifically limits that different modes are correspondingly adopted to store data according to the capacity of the storage capacitor.
In one embodiment, the power down protection method further includes:
judging whether the solid state driver generates an instant voltage jump phenomenon or not, and outputting a second feedback signal;
and triggering the power failure protection mechanism when the solid state drive is judged to have instantaneous power failure according to the second feedback signal. Therefore, the power failure misjudgment operation caused by the instant voltage jump can be effectively prevented.
In one embodiment, monitoring the operating voltage of the solid state drive in real time comprises:
and judging whether the working voltage of the solid state driver is in a preset voltage range, and if not, judging that the input power supply is abnormal. The embodiment judges whether the input power supply is abnormal according to the working voltage of the solid-state drive so as to better process the power-down phenomenon of the solid-state drive.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: according to the power-down protection circuit, the data storage device and the power-down protection method, the working voltage of the solid-state drive is monitored in real time through the power supply detection circuit, the capacity of the power storage capacitor is obtained through the capacitor management circuit, the power supply control circuit controls the input power supply to charge the power storage capacitor according to the capacity of the power storage capacitor, the power-down protection mechanism is triggered when the solid-state drive is judged to be powered down, and the data is stored in a corresponding storage mode in combination with the capacity of the power storage capacitor, so that the effectiveness of the electric quantity of the power storage capacitor is guaranteed, different strategies are adopted for writing in the data, and enough user data and a conversion table of a data page are stored as far as possible under the condition of limited capacity of the capacitor.
Drawings
Fig. 1 is a schematic block diagram illustrating an architecture of a power down protection circuit according to an aspect of the present application;
fig. 2 is a schematic diagram of another structural module of a power down protection circuit provided in an aspect of the present application;
FIG. 3 is a circuit diagram illustrating an exemplary power detection circuit in a power down protection circuit according to the present disclosure;
fig. 4 is a schematic flow chart illustrating a step of a power down protection method according to another aspect of the present application;
fig. 5 is a schematic flow chart illustrating another step of a power down protection method according to another aspect of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, a schematic diagram of a structural module of a power down protection circuit according to an aspect of the present application is shown, for convenience of description, only the relevant portions of the present embodiment are shown, and the following details are described below:
the power-down protection circuit is applied to a solid-state drive 106, a storage capacitor 105 is arranged on a board card of the solid-state drive 106, and the power-down protection circuit comprises a power supply detection circuit 101, a capacitor management circuit 103 and a power supply control circuit 102.
The power detection circuit 101 is configured to monitor an operating voltage of the solid state drive 106 in real time and output a first feedback signal.
Specifically, in the scheme, the input power supply 104 is adopted to supply power to the solid state drive 106, the power supply detection circuit 101 is mainly used for detecting whether the working voltage of the solid state drive 106 is in a preset voltage range, and if so, the input power supply 104 is judged to be normal; if not, the input power supply 104 is determined to be abnormal. The preset voltage range can be set according to actual requirements.
The capacitance management circuit 103 is connected to the storage capacitor 105, and the capacitance management circuit 103 acquires and feeds back the capacitance of the storage capacitor 105.
Specifically, the capacitor management circuit 103 feeds back the remaining capacity of the storage capacitor 105 and notifies the power control circuit 102 to charge the storage capacitor 105, and after the charging is completed, the power control circuit 102 will turn off the switch of the charging path to ensure the validity of the stored electric quantity of the storage capacitor 105. It should be understood that the remaining capacity of the storage capacitor 105 is equal in size to the amount of stored power of the storage capacitor 105.
The power control circuit 102 is connected to the input power 104, the power detection circuit 101, and the capacitor management circuit 103, and the power control circuit 102 is configured to control the input power 104 to charge the storage capacitor 105 according to the capacity of the storage capacitor 105, and determine, according to the first feedback signal, that a power failure occurs in the solid state drive 106, trigger a power failure protection mechanism, and store the user data or the mapping table of the data page in the cache in a corresponding storage mode in combination with the capacity of the storage capacitor 105.
Specifically, the power control circuit 102 in this embodiment relates to two functions, on one hand, according to the capacity of the storage capacitor 105 fed back by the capacitor management circuit 103, the input power 104 is controlled to charge the storage capacitor 105; on the other hand, according to the first feedback signal output by the power detection circuit 101, it is determined that when the solid state drive 106 is powered down, a power down protection mechanism is triggered, and meanwhile, a corresponding storage mode is adopted to store the mapping table of the user data or the data page in the cache in combination with the remaining capacity of the storage capacitor 105. It should be understood that when the solid state drive 106 is powered down, the solid state drive 106 is powered through the storage capacitor 105, so as to write data transmitted by the host to the solid state drive 106 or a data page table of the solid state drive 106 into the Flash memory chip as much as possible, so that the solid state drive 106 can smoothly read back the data when the power is down at the next start-up. The power failure protection mechanism is a special data protection mode, and means that all data are stored on a disk all the time when power is lost, and are not deleted until reconstruction is completed.
Illustratively, when the solid state drive 106 is powered down and the residual capacity of the storage capacitor 105 exceeds a preset electric quantity value, a TLC mode is adopted to store the mapping table of the user data or the data page in the cache;
when the solid state drive 106 is powered down and the residual capacity of the storage capacitor 105 is lower than the preset electric quantity value, the SLC mode is adopted to store the mapping table of the user data or the data page in the cache.
It will be appreciated that in TLC mode each cell can store more data for eight charge values, requiring longer access times and therefore slower transfer speeds.
SLC mode only has two charge values of 0 and 1, and has a simple structure but high execution efficiency. SLC flash memory has the advantages of faster transfer speed, lower power consumption and longer life of the memory cells.
Therefore, the power-down protection circuit ensures the effectiveness of the electric quantity of the electric storage capacitor 105, realizes that different strategies are adopted for data writing, and stores enough user data and data page conversion tables under the condition of limited capacity of the electric storage capacitor 105 as far as possible.
Referring to fig. 2, a schematic diagram of another structural module of a power down protection circuit according to an aspect of the present application shows only a portion related to the present embodiment for convenience of description, and is detailed as follows:
on the basis of the embodiment shown in fig. 1, the power down protection circuit further includes a capacitance skipping circuit 107.
The capacitance trip circuit 107 is connected with the power detection circuit 101, the power control circuit 102 and the storage capacitor 105, and the capacitance trip circuit 107 is used for judging whether the solid state driver 106 generates an instant voltage trip phenomenon or not and outputting a second feedback signal;
the power control circuit 102 is further configured to trigger a power-down protection mechanism when it is determined that the solid-state drive 106 has an instantaneous power-down according to the second feedback signal.
Specifically, the capacitor trip circuit 107 is provided in this embodiment, so that power failure misjudgment operation caused by instantaneous voltage trip can be effectively prevented. Because of the sudden instantaneous power failure, the power failure time is very short, which may be only a few milliseconds, so that the solid state drive 106 has not yet been in time to perform power down operation, and during the power down process, if the host recovers the normal power supply, the solid state drive 106 may be subjected to a disk drop phenomenon, so that it is also necessary to provide the capacitance trip circuit 107.
Referring to fig. 3, for convenience of description, only the relevant parts of the present embodiment are shown in an exemplary circuit diagram of a power detection circuit in a power down protection circuit provided in the present application, and the following details are described below:
in one embodiment, the power detection circuit 101 includes a dual operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a first light emitting diode LED1, and a second light emitting diode LED 2.
A first terminal of the first resistor R1 is connected to the input power source 104 with a first non-inverting input terminal IN1+ of the dual operational amplifier U1, a first terminal of the second resistor R2 is connected to the first terminal of the first capacitor C1 and a first inverting input terminal IN 1-of the dual operational amplifier U1, a second terminal of the first resistor R1 is connected to the second terminal of the first capacitor C1, a second terminal of the second resistor R2, a first output terminal OUT1 of the dual operational amplifier U1, a second non-inverting input terminal IN2+ of the dual operational amplifier U1 and a first terminal of the second capacitor C2 are connected together, a first terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4 and a second inverting input terminal IN 2-of the dual operational amplifier U1, a second terminal of the third resistor R3, a first terminal of the fifth resistor R5, an anode of the first light emitting diode 1 and a second output terminal of the second operational amplifier U8672 are connected to the anode 1 of the LED1, a second terminal of the second capacitor C2, a second terminal of the fourth resistor R4, a cathode of the first light emitting diode LED1, and a cathode of the second light emitting diode LED2 are grounded.
In one embodiment, the capacitance management circuit 103 is implemented by a multivibrator, wherein the larger the capacitance value of the storage capacitor 105, the lower the oscillation frequency.
In one embodiment, the power control circuit 102 includes a main control chip, and the main control chip generally employs a Micro Controller Unit (MCU), such as a single chip microcomputer.
The application also provides a data storage device, which is applied to the solid-state drive 106, wherein a storage capacitor 105 is arranged on a board of the solid-state drive 106, and the data storage device comprises:
an input power supply 104 for powering a solid state drive 106; and
such as the power down protection circuit described above.
It should be noted that the data storage device is added with the input power supply 104 on the basis of the power down protection circuit, so that the functional description and the principle description of the power detection circuit 101, the power control circuit 102, the capacitance management circuit 103 and the capacitance skipping circuit 107 in the power down protection circuit can refer to the embodiment of fig. 1 and 3, and details are not repeated here.
Referring to fig. 4, for convenience of description, only the relevant parts of the power down protection method provided by another aspect of the present application are shown, and the following details are described below:
the application also provides a power-down protection method, which is applied to the solid-state drive, wherein the board card of the solid-state drive is provided with an electricity storage capacitor, and the power-down protection method comprises the following steps:
s100, monitoring the working voltage of the solid-state driver in real time, and outputting a first feedback signal;
specifically, an input power supply is adopted to supply power to the solid state drive, whether the working voltage of the solid state drive is in a preset voltage range or not is detected, and if yes, the input power supply is judged to be normal; if not, the input power supply is judged to be abnormal. The preset voltage range can be set according to actual requirements.
S200, acquiring the capacity of the storage capacitor and feeding back the capacity;
specifically, the capacity of the storage capacitor is fed back in real time and the storage capacitor is informed to be charged, and after charging is completed, the switch of the charging path is disconnected so as to ensure the effectiveness of the electric quantity of the storage capacitor.
S300, controlling an input power supply to charge the storage capacitor according to the capacity of the storage capacitor;
specifically, the residual capacity of the storage capacitor is ensured to be sufficient in real time, so that when the solid-state drive is powered off, enough conversion tables of user data and data pages can be stored at most possibly under the condition of limited capacity of the storage capacitor, and the phenomenon that the mapping table of the user data or the data pages stored in the cache is lost is avoided.
S400, according to the first feedback signal, judging that when the solid-state drive is powered off, triggering a power-off protection mechanism, and storing user data or a mapping table of a data page in the cache in a corresponding storage mode by combining the capacity of a storage capacitor.
It should be understood that when the solid state drive 106 is powered down, the solid state drive 106 is powered through the storage capacitor 105, so as to write data transmitted by the host to the solid state drive 106 or a data page table of the solid state drive 106 into the Flash memory chip as much as possible, so that the solid state drive 106 can smoothly read back the data when the power is down at the next start-up.
The data are stored in a corresponding storage mode by combining the capacity of the storage capacitor, and the data storage method comprises the following steps:
when the capacity of the power storage capacitor exceeds a preset electric quantity value, storing user data or a mapping table of data pages in a cache in a TLC mode;
and when the capacity of the storage capacitor is lower than a preset electric quantity value, storing the user data or the mapping table of the data page in the cache in an SLC mode.
The power-down protection method ensures the effectiveness of the electric quantity of the storage capacitor, realizes that different strategies are adopted for writing data, and stores enough user data and conversion tables of data pages under the condition of limited capacity of the capacitor as far as possible.
As shown in fig. 5, based on the embodiment shown in fig. 4, the power down protection method further includes the following steps:
s500, judging whether the solid state drive generates an instant voltage jump phenomenon or not, and outputting a second feedback signal;
and S600, triggering a power-down protection mechanism when the solid-state drive is judged to have instantaneous power-down according to the second feedback signal.
Therefore, the power failure misjudgment operation caused by the instant voltage jump can be effectively prevented.
In one embodiment, monitoring the operating voltage of the solid state drive in real time comprises:
and judging whether the working voltage of the solid-state drive is in a preset voltage range, and if not, judging that the input power supply is abnormal.
The embodiment judges whether the input power supply is abnormal according to the working voltage of the solid-state drive so as to better process the power-down phenomenon of the solid-state drive.
Therefore, the power-down protection circuit, the data storage device and the power-down protection method have the advantages that:
1. the capacitor trip circuit 107 is arranged, so that power failure misjudgment operation caused by instant voltage jump can be effectively prevented;
2. through capacity detection of the storage capacitor 105, information of the current storage capacitor 105 can be acquired in real time through firmware, and the effectiveness of the electric quantity of the capacitor can be guaranteed through feedback;
3. different strategies can be adopted for data writing through firmware algorithms, and as far as possible, enough conversion tables of user data and data pages can be stored under the condition of limited capacity of the storage capacitor 105.
With reference to fig. 1 to 5, the working principle of the power down protection circuit, the data storage device and the power down protection method is as follows:
firstly, after the solid state drive 106 is powered on, the power detection circuit 101 and the capacitance management circuit 103 operate normally; the capacitance management circuit 103 starts to feed back the capacity of the storage capacitor 105 and informs the power supply control circuit 102 to charge the storage capacitor 105, and after the charging is completed, the switch of the charging path is disconnected, and real-time capacitance capacity is fed back periodically to inform the power supply control circuit 102 whether to charge the storage capacitor 105;
in the normal operation process of the power detection circuit 101, the voltage range of the solid state drive 106 is monitored in real time, and if the voltage is within the preset range, the input power 104 is normal; if the voltage is not within the preset range and the capacitance skipping circuit 107 also displays abnormity, the input power supply 104 is abnormal;
when the power detection circuit 101 detects that the input power 104 is abnormal, a power interruption signal is sent to the main control chip of the solid-state driver 106 through the power control circuit 102;
after the main control chip of the solid state drive 106 receives the interrupt signal, the information of the capacitor management circuit 103 is read, the information of the current storage capacitor 105 is obtained, and a power-down protection mechanism is triggered, and through an internal software algorithm of the solid state drive 106, according to the capacity of the storage capacitor 105 and the size of the data which is not currently written, a data writing strategy is determined, for example: when the capacity of the storage capacitor 105 is sufficient, the data block is written in the TLC mode according to the TLC mode, and when the remaining capacity of the storage capacitor 105 is reduced, the subsequent data is written in the SLC mode. Preferentially writing data, and if the data has residual capacity after being written, writing a page conversion table of the data block into a Flash memory chip in an SLC mode;
when the power detection circuit 101 detects that the input power 104 is recovered, the power control circuit 102 sends a power recovery interrupt signal to the main control chip of the solid state drive 106, and the solid state drive 106 controller starts to charge the storage capacitor 105 according to the information fed back by the capacitor management circuit 103 and the capacitor skipping circuit 107.
To sum up, the power-down protection circuit, the data storage device and the power-down protection method provided by the application monitor the working voltage of the solid-state drive in real time through the power detection circuit and acquire the capacity of the storage capacitor through the capacitor management circuit, so that the power control circuit controls the input power supply to charge the storage capacitor according to the capacity of the storage capacitor, and judges that when the solid-state drive loses power, a power-down protection mechanism is triggered, and the corresponding storage mode is adopted to store data in combination with the capacity of the storage capacitor, thereby ensuring the validity of the electric quantity of the storage capacitor, realizing that different strategies are adopted for writing in data, and storing enough user data and a conversion table of data pages as far as possible under the capacity condition of the limited capacitor. Meanwhile, a capacitor trip circuit is arranged, so that power failure misjudgment operation caused by instant voltage jump can be effectively prevented.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. The utility model provides a power-fail protection circuit, is applied to solid state drive, be equipped with a accumulate electric capacity on solid state drive's the integrated circuit board, its characterized in that, power-fail protection circuit includes:
a power supply detection circuit configured to monitor an operating voltage of the solid state drive in real time and output a first feedback signal;
the capacitance management circuit is connected with the storage capacitor and is configured to acquire the capacity of the storage capacitor and perform feedback; and
and the power supply control circuit is connected with an input power supply, the power supply detection circuit and the capacitor management circuit, is configured to control the input power supply to charge the storage capacitor according to the capacity of the storage capacitor, judges that a power failure protection mechanism is triggered when the solid-state drive is powered down according to the first feedback signal, and stores the user data or the mapping table of the data page in the cache in a corresponding storage mode by combining the capacity of the storage capacitor.
2. The power down protection circuit of claim 1, further comprising:
the capacitor tripping circuit is connected with the power supply detection circuit, the power supply control circuit and the storage capacitor, and is configured to judge whether the solid-state driver generates an instant voltage tripping phenomenon or not and output a second feedback signal;
the power supply control circuit is further configured to trigger the power-down protection mechanism when the solid-state drive is judged to be instantaneously powered down according to the second feedback signal.
3. The power down protection circuit of claim 1, wherein the power supply detection circuit comprises:
the LED driving circuit comprises a double operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a first LED and a second LED;
a first end of the first resistor and a first positive input end of the dual operational amplifier are connected to the input power supply, a first end of the second resistor and a first end of the first capacitor and a first negative input end of the dual operational amplifier are connected in common, a second end of the first resistor and a second end of the first capacitor are connected to ground, a second end of the second resistor, a first output end of the dual operational amplifier, a second positive input end of the dual operational amplifier and a first end of the second capacitor are connected in common, a first end of the third resistor and a first end of the fourth resistor and a second negative input end of the dual operational amplifier are connected in common, a second end of the third resistor, a first end of the fifth resistor, an anode of the first light emitting diode and a second output end of the dual operational amplifier are connected in common, a second end of the fifth resistor is connected to an anode of the second light emitting diode, the second end of the second capacitor, the second end of the fourth resistor, the cathode of the first light emitting diode and the cathode of the second light emitting diode are grounded.
4. The power down protection circuit of claim 1, wherein the capacitance management circuit is implemented using a multivibrator.
5. The power-down protection circuit according to claim 1, wherein the power control circuit is implemented by a single chip microcomputer.
6. A data storage device is applied to a solid-state drive, and a storage capacitor is arranged on a board card of the solid-state drive, and the data storage device comprises:
an input power source configured to power the solid state drive; and
the power down protection circuit of any of claims 1-5.
7. A power-down protection method is applied to a solid-state drive, and a board card of the solid-state drive is provided with a storage capacitor, and is characterized by comprising the following steps:
monitoring the working voltage of the solid-state driver in real time and outputting a first feedback signal;
acquiring the capacity of the storage capacitor and feeding back the capacity;
controlling an input power supply to charge the storage capacitor according to the capacity of the storage capacitor;
and judging whether the solid state drive has power failure according to the first feedback signal, triggering a power failure protection mechanism when the solid state drive has power failure, and storing the mapping table of the user data or the data page in the cache in a corresponding storage mode by combining the capacity of the storage capacitor.
8. The power-fail protection method of claim 7, wherein the saving data in the corresponding storage mode in combination with the capacity of the storage capacitor comprises:
when the capacity of the power storage capacitor exceeds a preset electric quantity value, storing user data or a mapping table of data pages in a cache in a TLC mode;
and when the capacity of the storage capacitor is lower than a preset electric quantity value, storing the user data or the mapping table of the data page in the cache in an SLC mode.
9. The power down protection method of claim 7, further comprising:
judging whether the solid state driver generates an instant voltage jump phenomenon or not, and outputting a second feedback signal;
and triggering the power failure protection mechanism when the solid state drive is judged to have instantaneous power failure according to the second feedback signal.
10. The power fail safeguard method of claim 7, wherein monitoring the operating voltage of the solid state drive in real time comprises:
and judging whether the working voltage of the solid state driver is in a preset voltage range, and if not, judging that the input power supply is abnormal.
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| CN202011103952.8A CN112259146A (en) | 2020-10-15 | 2020-10-15 | Power-down protection circuit, data storage device and power-down protection method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113109738A (en) * | 2021-03-15 | 2021-07-13 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN113687710A (en) * | 2021-10-26 | 2021-11-23 | 西安羚控电子科技有限公司 | Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle |
-
2020
- 2020-10-15 CN CN202011103952.8A patent/CN112259146A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113109738A (en) * | 2021-03-15 | 2021-07-13 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN113109738B (en) * | 2021-03-15 | 2023-08-04 | 苏州汇川技术有限公司 | Power-down time detection circuit and power-down time detection system |
| CN113687710A (en) * | 2021-10-26 | 2021-11-23 | 西安羚控电子科技有限公司 | Power failure processing method and system for flight control management computer of fixed-wing unmanned aerial vehicle |
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