CN213399501U - Power-down holding circuit and electronic equipment - Google Patents
Power-down holding circuit and electronic equipment Download PDFInfo
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- CN213399501U CN213399501U CN202022869203.8U CN202022869203U CN213399501U CN 213399501 U CN213399501 U CN 213399501U CN 202022869203 U CN202022869203 U CN 202022869203U CN 213399501 U CN213399501 U CN 213399501U
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- 239000003990 capacitor Substances 0.000 claims abstract description 53
- 230000015654 memory Effects 0.000 claims abstract description 38
- 238000007599 discharging Methods 0.000 claims abstract description 36
- 238000001514 detection method Methods 0.000 claims abstract description 24
- 238000012544 monitoring process Methods 0.000 claims description 11
- 230000014759 maintenance of location Effects 0.000 claims description 6
- 238000013500 data storage Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003745 diagnosis Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
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Abstract
The utility model provides a power down holding circuit and electronic equipment falls power down holding circuit and includes: the device comprises a first direct current-direct current voltage converter, a second direct current-direct current voltage converter, an MCU (microprogrammed control unit), a nonvolatile memory, a volatile memory, a power failure detection module and a capacitor charging and discharging circuit; and when the power supply is normal, the super capacitor in the capacitor charging circuit is charged, and after power failure, the super capacitor in the capacitor charging circuit supplies power to the MCU, the nonvolatile memory and the volatile memory. And after the power failure detection module detects that the power supply fails, the power failure detection module sends a signal to the MCU, so that the MCU writes the data to be stored into the nonvolatile memory, and the reliability of data storage is improved.
Description
Technical Field
The utility model relates to a data fall the electric technical field of preserving, more specifically say, relate to a fall electric holding circuit and electronic equipment.
Background
The data power-down storage function of the electronic equipment refers to timely storing data under the condition of unexpected power failure. At present, the following schemes are stored in the electronic device when data is powered down:
1. the data are stored by using nonvolatile memories such as EEPROM, FLASH, F-RAM and the like, and because the devices have write-in service life, only some data which are not changed frequently can be written in during normal work, and when the electronic equipment is powered off suddenly, the data have the risk of write-in errors.
2. Battery powered SRAM is used. Although this scheme has the advantages of high writing speed and unlimited times, the battery needs to be replaced periodically, and data is lost when the battery is replaced.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a power down holding circuit and electronic equipment intends to improve the reliability of data storage when falling the electricity.
In order to achieve the above object, the following solutions are proposed:
in a first aspect, a power down hold circuit is provided, including: the device comprises a first direct current-direct current voltage converter, a second direct current-direct current voltage converter, an MCU (microprogrammed control unit), a nonvolatile memory, a volatile memory, a power failure detection module and a capacitor charging and discharging circuit;
the input end of the first direct current-direct current voltage converter is connected with a power supply, and the output end of the first direct current-direct current voltage converter is respectively connected with the input end of the capacitor charging and discharging circuit and the input end of the second direct current-direct current voltage converter;
the output end of the capacitor charging and discharging circuit is connected with the input end of the second direct current-direct current converter;
a first output end of the second direct current-direct current converter is connected with a power supply end of the MCU, a second output end of the second direct current-direct current converter is connected with a power supply end of the nonvolatile memory, and a third output end of the second direct current-direct current converter is connected with a power supply end of the volatile memory;
the input end of the power failure detection module is connected with the power supply, and the output end of the power failure detection module is connected with the interrupt end of the MCU;
the capacitor charging and discharging circuit comprises a super capacitor, a charging control circuit connected between the input end of the capacitor charging and discharging circuit and a discharging control circuit connected between the output end of the capacitor charging and discharging circuit and the super capacitor.
Preferably, the charge control circuit includes: the first load switch and the current limiting resistor are connected in series.
Preferably, the first load switch specifically includes: SGM 2566B.
Preferably, the discharge control circuit includes: and the conduction direction of the first diode points to the output end of the capacitor charging and discharging circuit.
Preferably, the second load switch specifically includes: SGM 2566B.
Preferably, the power failure detection module includes:
one end of the first resistor is connected with the power supply;
the second resistor is connected with one end of the first resistor, and the other end of the second resistor is grounded;
a PFI pin is connected to a monitoring chip on a connecting line of the first resistor and the second resistor, a VCC pin of the monitoring chip is connected to a power supply voltage, and a PFO pin of the monitoring chip is connected to an output end of the power failure detection module;
a second diode connected between the PFI pin and ground, the conduction direction of the second diode pointing to the PFI pin; and the number of the first and second groups,
a third resistor connected between the supply voltage and the PFO pin.
Preferably, the monitoring chip specifically includes: SGM706-TYS 8G/TR.
Preferably, the volatile memory is specifically: DDR 3.
Preferably, the nonvolatile memory is specifically: one of FLASH and F-RAM.
In a second aspect, an electronic device is provided, which includes the power down holding circuit as in any one of the first aspect.
Compared with the prior art, the technical scheme of the utility model have following advantage:
the power down holding circuit and the electronic device provided by the technical scheme have the advantages that the power down holding circuit comprises: the device comprises a first direct current-direct current voltage converter, a second direct current-direct current voltage converter, an MCU (microprogrammed control unit), a nonvolatile memory, a volatile memory, a power failure detection module and a capacitor charging and discharging circuit; and when the power supply is normal, the super capacitor in the capacitor charging circuit is charged, and after power failure, the super capacitor in the capacitor charging circuit supplies power to the MCU, the nonvolatile memory and the volatile memory. And after the power failure detection module detects that the power supply fails, the power failure detection module sends a signal to the MCU, so that the MCU writes the data to be stored into the nonvolatile memory, and the reliability of data storage is improved.
Furthermore, the super capacitor is charged and discharged by using the load switch SGM2566B with low internal resistance, high current and backflow prevention, so that the charging and discharging efficiency of the super capacitor is improved, the charging and discharging circuit of the super capacitor is simplified, and the cost is saved.
Furthermore, when power is down, FLASH or F-RAM is adopted for data storage, and compared with MRAM, the cost is saved.
Of course, it is not necessary for any particular product to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a power down holding circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a capacitor charging/discharging circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a load switch SGM2566B according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a power down detection module provided by an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, the power down holding circuit provided for this embodiment includes: the device comprises a first direct current-direct current voltage converter 11, a second direct current-direct current voltage converter 12, an MCU13, a nonvolatile memory 14, a volatile memory 15, a power failure detection module 16 and a capacitance charging and discharging circuit 17. The capacitor charging and discharging circuit 17 includes a super capacitor C1, a charging control circuit 171 connected between the input terminal of the capacitor charging and discharging circuit 17 and the super capacitor C1, and a discharging control circuit 172 connected between the output terminal of the capacitor charging and discharging circuit 17 and the super capacitor C1.
The input end of the first dc-dc voltage converter 11 is connected to a power supply, which is a 24V power supply in this embodiment; the output end of the first dc-dc voltage converter 11 is connected to the input end of the capacitor charging and discharging circuit 17 and the input end of the second dc-dc voltage converter 12, respectively. The output end of the capacitor charging and discharging circuit 17 is connected with the input end of the second dc-dc converter 12.
A first output end of the second dc-dc converter 12 is connected to a power supply end of the MCU 13; a second output end of the second DC-DC converter 12 is connected with a power supply end of the nonvolatile memory 14; a third output terminal of the second dc-dc converter 12 is connected to a supply terminal of the volatile memory 15.
The input end of the power failure detection module 16 is connected with a power supply; the output end of the power down detection module 16 is connected with the interrupt end of the MCU 13.
The working principle of the power-down holding circuit provided by the embodiment is as follows:
when the power supply is normally powered, data needing to be kept in a power-down state runs in the volatile memory 15, and the MCU13 can read and write the data in the volatile memory 15; if the super capacitor C1 needs to be charged, the super capacitor C1 is charged by the voltage converted by the first dc-dc converter 11 through the charging and discharging circuit 17. When the power supply is powered off, the power down detection module 16 outputs a power down signal to an interrupt end (i.e., an interrupt pin) of the MCU13 to trigger an interrupt service routine of the MCU13, and at this time, the MCU13 stops all tasks and writes data to be held in power down into the nonvolatile memory 14; after the power supply is powered off, the super capacitor C1 supplies power to the loads such as the MCU13, the nonvolatile memory 14 and the volatile memory 15 through the discharge control circuit 172 and the second DC-DC converter 12 respectively, so that the loads continue to work; in the process of supplying power to the load by the super capacitor C1, the discharging control circuit 172 controls the discharging process of the super capacitor C1, and the second dc-dc converter 12 converts the voltage to provide the required voltage for the MCU13, the nonvolatile memory 14, and the volatile memory 15, respectively. When the power is turned on again, the MCU13 reads data from the non-volatile memory 14 and writes it to the volatile memory 15, thereby implementing a power-down data retention function.
In some embodiments, the volatile memory is specifically: DDR 3.
In some embodiments, the non-volatile memory is specifically: one of FLASH and F-RAM.
In some embodiments, the charge control circuit 171 includes a first load switch and a current limiting resistor connected in series; the discharge control circuit 172 includes: a second load switch and a first diode connected in parallel. The conducting direction of the first diode is directed to the output terminal of the capacitor charging and discharging circuit 17. Referring to fig. 2, a schematic diagram of the capacitor charging and discharging circuit 17 is shown when the first load switch U1 and the second load switch U2 are both SGM2566B, and the input terminal and the output terminal of the capacitor charging and discharging circuit 17 are the same terminal. The EN/NFAULT pin of the first load switch U1 is connected with the input end of the capacitor charging and discharging circuit 17 through a resistor R4; two VOUT pins of the first load switch U1 are connected with the anode of a super capacitor C1 through a current limiting resistor R5; the two VIN pins and the VBIAS pin of the first load switch U1 are connected to an input terminal of the capacitor charging and discharging circuit 17. Two VIN pins and a VBIAS pin of the second load switch U2 are both connected with the positive electrode of the first diode D1; two VOUT pins of the second load switch U2 are both connected with the negative electrode of the first diode D1; the EN/NFAULT pin of the second load switch U2 is connected to the anode of the super capacitor C1 through a resistor R6.
The first diode D1 is embodied as SS26A in the present embodiment.
The internal structure of the load switch SGM2566B is schematically illustrated in fig. 3. Due to the low internal resistance of the load switch SGM2566B, when the discharge current reaches 2A, the voltage drop is only 34mV, so that the effective discharge time of the super capacitor C1 is prolonged. The load switch SGM2566B is mainly characterized in that (1) the internal MOS impedance is 17m omega, and the output current can reach 6A; (2) when the output voltage is higher than the input voltage by 3mV, the output is turned off.
In some embodiments, the power loss detection module 16 includes: a first resistor R1, a second resistor R2, a third resistor R3, a second diode D2 and a monitor chip U3, see fig. 4 in particular. One end of the first resistor R1 is connected to the power supply as the input end D +24V _ IN of the power down detection module 16, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded. The third resistor R3 is connected between the PFO pin of the monitoring chip U3 and the power supply voltage D + 3.3V. The second diode D2 is connected between the PFI pin of the monitor chip U3 and ground, and the conduction direction of the second diode D2 points to the PFI pin of the monitor chip U3.
The PFI pin of the monitor chip U3 is connected to the connection line of the first resistor R1 and the second resistor R2. The VCC pin of the monitoring chip U3 is connected to the supply voltage D +3.3V, and the PFO pin of the monitoring chip U3 is connected to the output terminal D +24_ MONITOR of the power-down detection module 16. The monitoring chip may specifically be: SGM706-TYS 8G/TR. The second diode D2 may be specifically BZT52C5V 1.
For each resistor in fig. 2 and fig. 4, an optional form is given only by way of example, in practical application, each resistor may not only be a single resistor, but also replace each resistor in the embodiment shown in fig. 2 and fig. 4 by respectively adopting a mode of connecting a plurality of resistors in series, connecting a plurality of resistors in parallel, or combining a plurality of resistors in series and parallel according to actual requirements, which is not specifically limited this time and is within the protection scope of the present invention.
The embodiment also provides an electronic device comprising any one of the power-down holding circuits. The electronic device can be a computer, a mobile phone, a medical diagnosis device and the like.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such device. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in a device that comprises the element.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description of the disclosed embodiments of the invention enables one skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A power down hold circuit, comprising: the device comprises a first direct current-direct current voltage converter, a second direct current-direct current voltage converter, an MCU (microprogrammed control unit), a nonvolatile memory, a volatile memory, a power failure detection module and a capacitor charging and discharging circuit;
the input end of the first direct current-direct current voltage converter is connected with a power supply, and the output end of the first direct current-direct current voltage converter is respectively connected with the input end of the capacitor charging and discharging circuit and the input end of the second direct current-direct current voltage converter;
the output end of the capacitor charging and discharging circuit is connected with the input end of the second direct current-direct current converter;
a first output end of the second direct current-direct current converter is connected with a power supply end of the MCU, a second output end of the second direct current-direct current converter is connected with a power supply end of the nonvolatile memory, and a third output end of the second direct current-direct current converter is connected with a power supply end of the volatile memory;
the input end of the power failure detection module is connected with the power supply, and the output end of the power failure detection module is connected with the interrupt end of the MCU;
the capacitor charging and discharging circuit comprises a super capacitor, a charging control circuit connected between the input end of the capacitor charging and discharging circuit and a discharging control circuit connected between the output end of the capacitor charging and discharging circuit and the super capacitor.
2. The power down hold circuit of claim 1, wherein the charge control circuit comprises:
the first load switch and the current limiting resistor are connected in series.
3. The power down retention circuit of claim 2, wherein the first load switch is specifically:
SGM2566B。
4. the power down hold circuit of claim 1, wherein the discharge control circuit comprises:
and the conduction direction of the first diode points to the output end of the capacitor charging and discharging circuit.
5. The power-down retention circuit according to claim 4, wherein the second load switch is specifically:
SGM2566B。
6. the power down hold circuit of claim 1, wherein the power down detection module comprises:
one end of the first resistor is connected with the power supply;
the second resistor is connected with one end of the first resistor, and the other end of the second resistor is grounded;
a PFI pin is connected to a monitoring chip on a connecting line of the first resistor and the second resistor, a VCC pin of the monitoring chip is connected to a power supply voltage, and a PFO pin of the monitoring chip is connected to an output end of the power failure detection module;
a second diode connected between the PFI pin and ground, the conduction direction of the second diode pointing to the PFI pin; and the number of the first and second groups,
a third resistor connected between the supply voltage and the PFO pin.
7. The power-down retention circuit according to claim 6, wherein the monitor chip specifically comprises:
SGM706-TYS8G/TR。
8. the power-down retention circuit according to claim 1, wherein the volatile memory is specifically:
DDR3。
9. the power down retention circuit according to any one of claims 1 to 8, wherein the nonvolatile memory is specifically:
one of FLASH and F-RAM.
10. An electronic device comprising the power down hold circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022869203.8U CN213399501U (en) | 2020-12-02 | 2020-12-02 | Power-down holding circuit and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022869203.8U CN213399501U (en) | 2020-12-02 | 2020-12-02 | Power-down holding circuit and electronic equipment |
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| CN213399501U true CN213399501U (en) | 2021-06-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114003173A (en) * | 2021-09-30 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Power-down protection system of storage device and storage device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114003173A (en) * | 2021-09-30 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Power-down protection system of storage device and storage device |
| CN114003173B (en) * | 2021-09-30 | 2023-08-18 | 苏州浪潮智能科技有限公司 | Power-down protection system of storage device and storage device |
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