CN217509017U - Power supply delay circuit and USB earphone - Google Patents
Power supply delay circuit and USB earphone Download PDFInfo
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- CN217509017U CN217509017U CN202221262650.XU CN202221262650U CN217509017U CN 217509017 U CN217509017 U CN 217509017U CN 202221262650 U CN202221262650 U CN 202221262650U CN 217509017 U CN217509017 U CN 217509017U
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Abstract
The application is applicable to the technical field of USB earphones, and provides a power supply time delay circuit, which comprises a power supply input end, a power supply output end, a charging circuit, a first switch circuit and a second switch circuit: the charging circuit is connected with the power input end, the first switch circuit is connected with the charging circuit, the second switch circuit is connected with the first switch circuit, the second switch circuit is connected with the power input end, and the second switch circuit is connected with the power output end. Therefore, the technical problem that the cost of the implementation scheme for safety certification of the power supply delay circuit inrush current in the prior art is high is solved.
Description
Technical Field
The application belongs to the technical field of USB earphones, and particularly relates to a power supply delay circuit and a USB earphone.
Background
In the prior art, in order to permit sale, part of USB earphones require inrush current safety certification, the inrush current safety certification means that the current cannot be too large within 100ms of inserting the USB, otherwise the certification cannot pass, and some of the inrush current safety certification are difficult to realize through software or the cost is increased through the software.
Other projects are implemented by adding a special inhibit IC, which also increases the cost of the overall project.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a power supply delay circuit and a USB earphone, and can solve the technical problem that the cost of an inrush current safety certification implementation scheme in the prior art is high.
In a first aspect, an embodiment of the present application provides a power supply delay circuit, where the power supply delay circuit includes:
the power supply input end is used for accessing a power supply signal;
a power supply output terminal;
the charging circuit is connected with the power supply input end and is used for being charged when the power supply input end is connected with the power supply signal and generating a pre-charging signal;
the first switch circuit is connected with the charging circuit and used for receiving the pre-charging signal and generating a switch control signal when the voltage of the pre-charging signal is greater than a preset voltage value;
and the second switch circuit is connected with the first switch circuit, the power supply input end and the power supply output end, and is used for receiving the switch control signal and conducting according to the switch control signal so as to output the power supply signal to the power supply output end.
In a possible implementation manner of the first aspect, the voltage of the pre-charge signal is greater than a preset voltage value when the charging circuit is charged for a first preset time period, where the first preset time period is greater than 100ms and less than 300 ms.
In a possible implementation manner of the first aspect, the charging circuit includes a first capacitor and a first resistor, a first end of the first resistor is an input end of the charging circuit, a second end of the first resistor is connected to the first end of the first capacitor, a connection node thereof is an output end of the charging circuit, and a second end of the first capacitor is grounded.
In a possible implementation manner of the first aspect, the power supply delay circuit further includes a first voltage divider circuit, and the first voltage divider circuit is disposed between the controlled terminal and the input terminal of the second switch circuit.
In a possible implementation manner of the first aspect, the first switch circuit includes a first switch tube and a second resistor, a first end of the second resistor is an input end of the first switch circuit, a second end of the second resistor is connected to a controlled end of the first switch tube, a first end of the first switch tube is grounded, and a second end of the first switch tube is an output end of the first switch circuit.
In a possible implementation manner of the first aspect, the second switch circuit includes a second switch tube, a controlled end of the second switch tube is a controlled end of the second switch circuit, a first end of the second switch tube is a first end of the second switch circuit, and a second end of the second switch tube is a second end of the second switch circuit.
In a possible implementation manner of the first aspect, the power supply delay circuit further includes a discharging circuit, an output end of the discharging circuit is grounded, and an input end of the discharging circuit is connected to an output end of the charging circuit;
the discharging circuit is used for providing a discharging loop when the charging circuit discharges.
In a possible implementation manner of the first aspect, the discharge circuit includes a first diode, a cathode of the first diode is an output terminal of the discharge circuit, and an anode of the first diode is an input terminal of the discharge circuit.
In a second aspect, an embodiment of the present application provides a USB headset, where the USB headset includes the power supply delay circuit as described above.
In a possible implementation manner of the second aspect, the USB headset further includes a power supply and a headset operating circuit, an output end of the power supply is connected to a power supply input end of the power supply delay circuit, and a power supply end of the headset operating circuit is connected to a power supply output end of the power supply delay circuit.
Compared with the prior art, the embodiment of the application has the advantages that:
by the scheme, the charging circuit can be charged directly through hardware, namely when the power supply input end is connected with a power supply signal, and generates a pre-charge signal, the first switch circuit generates a switch control signal when the voltage of the pre-charge signal is greater than a preset voltage value, the second switch circuit is turned on according to the switch control signal to output the power signal to the power output terminal, so that the charging time can be determined by setting the parameters of the charging circuit, the voltage of the pre-charging signal of the charging circuit is directly greater than the preset voltage value after the set charging time, namely, the second switch circuit is ensured not to be conducted in the charging time of the USB plug-in, namely the current flowing at the moment is zero, thereby directly meeting inrush current safety certification through a scheme with lower cost and simpler hardware circuit, therefore, the technical problem that the implementation scheme of inrush current safety certification in the prior art is high in cost is solved through the scheme.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a block diagram of a power delay circuit according to an embodiment of the present application;
FIG. 2 is a circuit diagram of a power delay circuit according to an embodiment of the present application;
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The utility model discloses a solve among the prior art power delay circuit inrush current safety standard authentication's the higher technical problem of implementation scheme cost. The utility model provides a power delay circuit and USB earphone.
In an embodiment, fig. 1 shows a block schematic diagram of a power delay circuit provided in the present application, where the power delay circuit includes a power input terminal VIN, a power output terminal OUT, a charging circuit 10, a first switch circuit 20, and a second switch circuit 30: the input end of the charging circuit 10 is connected to the power input end VIN, the controlled end of the first switch circuit 20 is connected to the output end of the charging circuit 10, the input end of the first switch circuit 20 is grounded, the controlled end of the second switch circuit 30 is connected to the output end of the first switch circuit 20, the first end of the second switch circuit 30 is connected to the power input end VIN, and the second end of the second switch circuit 30 is connected to the power output end OUT.
The power input end VIN is connected with a power signal, and the charging circuit 10 is charged when connected with the power signal and generates a pre-charging signal; the first switch circuit 20 receives the pre-charge signal, and generates a switch control signal when the voltage of the pre-charge signal of the charging circuit 10 is greater than a preset voltage value; the second switch circuit 30 is turned on according to the switch control signal to output the power signal to the power output terminal. Through the scheme, when the power supply input end VIN is connected with the power supply signal, the charging circuit 10 is charged, the first switch circuit 20 outputs the switch control signal to control the second switch circuit 30 to conduct when the voltage of the pre-charging signal of the charging circuit 10 is greater than the preset voltage value, so that the charging time can be determined by setting the parameters of the charging circuit 10, which can be directly determined according to the charging formula of the capacitor, it is not described herein any more, so that the voltage of the charging circuit 10 is directly greater than the predetermined voltage value after the set charging time, i.e. to ensure that the second switch circuit 30 is not conducted during the charging time of the USB plug, i.e. the current flowing at this time is zero, therefore, the inrush current security certification can be directly met by a scheme with lower cost and simpler hardware circuit, therefore, the technical problem that the implementation scheme of inrush current safety certification in the prior art is high in cost is solved through the scheme.
In a possible implementation manner of the first aspect, the voltage of the pre-charge signal is greater than a preset voltage value when the charging circuit is charged for a first preset time period, where the first preset time period is greater than 100ms and less than 300 ms.
The time for charging the charging circuit 10 to the preset voltage value is set within a range of more than 100ms and less than 300ms, so that the circuit where the power supply delay circuit is located can meet safety certification, and timely power supply can be guaranteed. It should be noted that, the first preset time period at this time is also the charging time.
In a possible implementation manner of the first aspect, referring to fig. 2, the charging circuit 10 includes a first capacitor C1 and a first resistor R1, a first end of the first resistor R1 is an input end of the charging circuit 10, a second end of the first resistor R1 is connected to a first end of the first capacitor C1, a connection node thereof is an output end of the charging circuit 10, and a second end of the first capacitor C1 is grounded.
The first capacitor C1 is used as an energy storage device, discharging and charging can be achieved, when charging is conducted, voltage at two ends gradually rises until the preset voltage is met, the first resistor R1 has a voltage division effect, voltage division can be achieved when the voltage of a power supply is too high, and the highest voltage of the first capacitor C1 cannot exceed the safety value.
In a possible implementation manner of the first aspect, the power supply delay circuit further includes a first voltage dividing circuit 40, and the first voltage dividing circuit 40 is disposed between the controlled terminal and the input terminal of the second switch circuit 30. A certain degree of biasing resistance for the first switching tube Q1 may be achieved. The first voltage dividing circuit 40 may be replaced with a third resistor R3.
In a possible implementation manner of the first aspect, the first switch circuit 20 includes a first switch tube Q1 and a second resistor R2, a first end of the second resistor R2 is an input end of the first switch circuit 20, a second end of the second resistor R2 is connected to a controlled end of the first switch tube Q1, a first end of the first switch tube Q1 is grounded, and a second end of the first switch tube Q1 is an output end of the first switch circuit 20.
It should be noted that the first switching transistor Q1 may be implemented by an NPN transistor, and the second resistor R2 is used as a voltage dividing resistor.
In a possible implementation manner of the first aspect, referring to fig. 2, the second switch circuit 30 includes a second switch tube Q2, the controlled terminal of the second switch tube Q2 is the controlled terminal of the second switch circuit 30, the first terminal of the second switch tube Q2 is the first terminal of the second switch circuit 30, and the second terminal of the second switch tube Q2 is the second terminal of the second switch circuit 30.
The second switching tube Q2 may be implemented by a PMOS tube. It should be noted that, at this time, an NMOS transistor may be set, and the output signal value after the first switch circuit 20 is turned on may be changed correspondingly, or another turn-on scheme may be implemented.
In a possible implementation manner of the first aspect, the power supply delay circuit further includes a discharging circuit 50, an output terminal of the discharging circuit 50 is grounded, and an input terminal of the discharging circuit 50 is connected to the output terminal of the charging circuit 10.
Wherein the discharging circuit 50 provides a discharging loop when the charging circuit 10 discharges. At this moment, the discharge time can be controlled within a short time, and the first switch tube Q1 can be quickly turned back to the off state, so that the effect of delaying the effective output of the power supply can be achieved even if the USB is continuously and quickly plugged.
In one possible implementation manner of the first aspect, the discharge circuit 50 includes a first diode D1, a cathode of the first diode D1 is an output terminal of the discharge circuit 50, and an anode of the first diode D1 is an input terminal of the discharge circuit 50.
The first diode D1 is grounded, so that a loop can be formed quickly, and the diode has the characteristic of one-way conduction, thereby avoiding the erroneous discharge.
The working principle of the present invention is described below with reference to fig. 1 and 2:
at the power-on moment, a power supply charges a first capacitor C1 through a first resistor R1, when the charging time reaches 270ms, the voltage rise of a B electrode of a first switch tube Q1 is larger than that of an E electrode, the first switch tube Q1 is conducted, the second switch tube Q2 is controlled to be conducted after the first switch tube Q1 is conducted, the power supply is effectively output to supply power to a system, and the delay of the whole process is about 270 m.
At the moment of power failure, the first capacitor C1 discharges through the first diode D1, the discharge time can be controlled within 5ms, and the first switch tube Q1 can quickly return to the off state, so that the effect of delaying the effective output of the power supply can be achieved even if the USB is continuously and quickly plugged. By the scheme, the technical problem that the cost of the implementation scheme for safety certification of the power supply delay circuit inrush current in the prior art is high is solved. And quick discharge can be realized, and the product quality and reliability are improved.
Corresponding to the power supply delay circuit of the above embodiment, the embodiment of the application also provides a USB headset, which includes the power supply delay circuit.
It should be noted that, because the utility model discloses USB earphone has contained foretell power delay circuit's all embodiments, consequently the utility model discloses USB earphone has foretell power delay circuit's all beneficial effects, and it is no longer repeated here.
In a possible implementation manner of the second aspect, the USB headset further includes a power supply and a headset operating circuit, an output terminal of the power supply is connected to the power input terminal VIN of the power supply delay circuit, and a power supply terminal of the headset operating circuit is connected to the power output terminal OUT of the power supply delay circuit.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A power delay circuit, comprising:
the power supply input end is used for accessing a power supply signal;
a power supply output terminal;
the charging circuit is connected with the power supply input end and is used for being charged when the power supply input end is connected with the power supply signal and generating a pre-charging signal;
the first switch circuit is connected with the charging circuit and used for receiving the pre-charging signal and generating a switch control signal when the voltage of the pre-charging signal is greater than a preset voltage value;
and the second switch circuit is connected with the first switch circuit, the power supply input end and the power supply output end, and is used for receiving the switch control signal and conducting according to the switch control signal so as to output the power supply signal to the power supply output end.
2. The power delay circuit of claim 1, wherein the voltage of the pre-charge signal is greater than a predetermined voltage value when the charging circuit is charged for a first predetermined period of time, wherein the first predetermined period of time is greater than 100ms and less than 300 ms.
3. The power delay circuit of claim 1, wherein the charging circuit comprises a first capacitor and a first resistor, a first terminal of the first resistor is an input terminal of the charging circuit, a second terminal of the first resistor is connected to a first terminal of the first capacitor, a connection node thereof is an output terminal of the charging circuit, and a second terminal of the first capacitor is grounded.
4. The power delay circuit of claim 1, further comprising a first voltage divider circuit disposed between the controlled terminal and the input terminal of the second switch circuit.
5. The power delay circuit of claim 1, wherein the first switch circuit comprises a first switch tube and a second resistor, a first end of the second resistor is an input end of the first switch circuit, a second end of the second resistor is connected to a controlled end of the first switch tube, a first end of the first switch tube is grounded, and a second end of the first switch tube is an output end of the first switch circuit.
6. The power delay circuit of claim 1, wherein the second switch circuit comprises a second switch tube, the controlled terminal of the second switch tube is the controlled terminal of the second switch circuit, the first terminal of the second switch tube is the first terminal of the second switch circuit, and the second terminal of the second switch tube is the second terminal of the second switch circuit.
7. The power delay circuit of any one of claims 1-6, further comprising a discharge circuit, an output of the discharge circuit being coupled to ground, an input of the discharge circuit being coupled to an output of the charging circuit;
the discharging circuit is used for providing a discharging loop when the charging circuit discharges.
8. The power delay circuit of claim 7, wherein the discharge circuit comprises a first diode, a cathode of the first diode being an output of the discharge circuit, and an anode of the first diode being an input of the discharge circuit.
9. A USB headset characterized in that it comprises a power supply delay circuit according to any of claims 1-8.
10. The USB headset of claim 9, further comprising a power source and a headset operating circuit, an output of the power source being connected to the power input of the power delay circuit, a power supply terminal of the headset operating circuit being connected to the power output of the power delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221262650.XU CN217509017U (en) | 2022-05-24 | 2022-05-24 | Power supply delay circuit and USB earphone |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221262650.XU CN217509017U (en) | 2022-05-24 | 2022-05-24 | Power supply delay circuit and USB earphone |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217509017U true CN217509017U (en) | 2022-09-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221262650.XU Active CN217509017U (en) | 2022-05-24 | 2022-05-24 | Power supply delay circuit and USB earphone |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217509017U (en) |
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2022
- 2022-05-24 CN CN202221262650.XU patent/CN217509017U/en active Active
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