CN209375223U - power down delay circuit - Google Patents

Abstract

The utility model relates to the field of power supply of electronic equipment, in particular to a power-off delay circuit capable of storing electric energy and extending the working time of electronic equipment. The power-down delay circuit includes a DC/DC power supply, the input terminal and output terminal of the DC/DC power supply are respectively connected to the VIN terminal and the VOUT terminal, and a charging branch is connected between the VIN terminal and the DC/DC power supply , a discharge branch is connected between the VOUT terminal and the DC/DC power supply; the charging branch and the discharge branch are connected through a power storage and discharge unit. The power-down delay circuit of the utility model improves and prolongs the working time of the electronic equipment through the cooperation of the DC/DC power supply, the charging branch circuit, the discharging branch circuit and the power storage and discharging unit Deng, facilitates the storage of data, and reduces the loss.

Description

power down delay circuit

technical field

The utility model relates to the field of power supply of electronic equipment, in particular to a power-off delay circuit capable of storing electric energy and extending the working time of electronic equipment.

Background technique

At present, the driving instrument, acquisition driver, intelligent power distribution control box and other equipment configured on the car, the data of the driving instrument is saved and the pointer is reset to zero when the power is off, the acquisition driver and the intelligent power distribution control box need to save data, due to the number of writes to the memory The current traditional solution is to save data regularly. The defect of the strategy of saving data regularly is that data loss will occur. When the time point of power failure and the time point of timing are too different, Larger data will be lost, so a device is needed to replenish electric energy in time when the power is cut off, so as to prolong the working time of electronic equipment.

Utility model content

The technical problem to be solved by the utility model is: to provide a power-off delay circuit, which improves and prolongs the working time of the electronic equipment, facilitates data storage and reduces losses.

The utility model is realized through the following technical solutions: the power-down delay circuit includes a DC/DC power supply, the input end and the output end of the DC/DC power supply are respectively connected with a VIN end and a VOUT end, and the VIN end and the DC A charging branch is connected between the /DC power supply, and a discharging branch is connected between the VOUT terminal and the DC/DC power supply; the charging branch and the discharging branch are connected through a power storage and discharge unit.

Further, in order to better implement the present utility model, the following settings are adopted in particular: the storage and discharge unit includes resistors R1, R2, R3, R4 and R5 connected in sequence, and the resistors R1, R2, R3, R4 and R5 are respectively connected in parallel with capacitors C1, C2, C3, C4 and C5; one end of R1 is connected to R2, the other end is connected to the charging branch, and the connection between the discharging branch and C4 is the same as C5 connect.

Further, in order to better implement the utility model, the following configuration is particularly adopted: the resistors R1, R2, R3, R4 and R5 are respectively connected in parallel with Zener diodes D1, D2, D3, D4 and D5.

Further, in order to better implement the utility model, the following configuration is particularly adopted: the charging branch includes electronic switch DK1, diode D6 and electronic switch DK3, and the discharging branch includes DK2, diode D7 and DK4; The input terminal of DK1 is connected to the input terminal of the DC/DC power supply, the output terminal of DK1 is connected to the input terminal of DK2, the positive pole of D6, and the negative pole of D7, and the output terminal of DK2 is connected to the output terminal of the DC/DC power supply; The negative pole is connected to the input terminal of electronic switch DK3 and the output terminal of DK4; said DK1 and DK3 are mutually exclusive with DK2 and DK4 respectively.

Furthermore, in order to better implement the utility model, the following configuration is particularly adopted: a current-limiting resistor R6 is connected between the D6 and the DK3.

Further, in order to better implement the utility model, the following settings are particularly adopted: the resistance values of the resistors R1, R2, R3, R4 and R5 are equal, and the resistance values of the capacitors C1, C2, C3, C4 and C5 are Capacitance is equal.

Further, in order to better implement the utility model, the following configuration is particularly adopted: the parameters of the Zener diodes D1, D2, D3, D4 and D5 are equal.

Further, in order to better implement the utility model, the following settings are particularly adopted: the DC/DC power supply is a 28V to 5V power supply.

The utility model has the following advantages and beneficial effects: the utility model adds a power-off delay circuit in the electronic equipment, which is used for data storage of the electronic equipment and zero reset of the pointer in the driving instrument when the electronic equipment is powered off each time. enough power. The power-down delay circuit of the utility model improves and prolongs the working time of the electronic equipment through the cooperation of the DC/DC power supply, the charging branch circuit, the discharging branch circuit and the power storage and discharging unit Deng, facilitates the storage of data, and reduces the loss.

Description of drawings

The drawings described here are used to provide a further understanding of the embodiments of the utility model, constitute a part of the application, and do not constitute a limitation to the embodiments of the utility model.

Fig. 1 is the circuit structural diagram of the power-down delay circuit of the present utility model;

Fig. 2 is a schematic diagram of an equivalent circuit when the charging branch works;

Fig. 3 is a schematic diagram of an equivalent circuit when the discharge branch works.

Detailed ways

In order to make the purpose, technical solutions and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the examples and accompanying drawings. The schematic implementation of the utility model and its description are only used to explain the utility model Novelty, not as a limitation to the utility model.

Example:

As shown in Figures 1 to 3, the power-down delay circuit of the present invention includes a DC/DC power supply, and the input and output terminals of the DC/DC power supply are connected to VIN and VOUT respectively. A charging branch is connected between the VOUT terminal and the DC/DC power supply, and a discharging branch is connected between the VOUT terminal and the DC/DC power supply; the charging branch and the discharging branch are connected through a power storage and discharge unit.

The utility model adds a power-down delay circuit in the electronic equipment, and is used for providing sufficient electric energy for data storage of the electronic equipment and zero reset of the pointer in the driving instrument when the electronic equipment is powered off each time. The power-down delay circuit of the utility model improves and prolongs the working time of the electronic equipment through the cooperation of the DC/DC power supply, the charging branch circuit, the discharging branch circuit and the power storage and discharging unit Deng, facilitates the storage of data, and reduces the loss.

The utility model has the advantage that it is only judged that the equipment has been powered off when the input voltage is very low, which will not cause malfunction of the equipment due to power supply noise, and can ensure short charging and long discharge time, and the utility model belongs to High-voltage charging and low-voltage discharging ensure that the power of the capacitor is fully used for equipment use, and there will be no step-down loss of LDO power supply or DC/DC power supply. Ensure efficient use of energy.

As a preference, on the basis of the above-mentioned embodiments, in order to better implement the utility model, the storage and discharge unit includes resistors R1, R2, R3, R4 and R5 connected in sequence, and the resistors R1, R2 , R3, R4 and R5 are respectively connected in parallel with capacitors C1, C2, C3, C4 and C5; one end of R1 is connected to R2, and the other end is connected to the charging branch, and the discharging branch and C4 are the same as C5 connection at the connection. Further, the resistors R1 , R2 , R3 , R4 and R5 are also connected in parallel with Zener diodes D1 , D2 , D3 , D4 and D5 . It is worth noting that resistors R1/R2, R3, R4, and R5 provide a charging circuit for charging each capacitor, and diodes D1, D2, D3, D4, and D5 provide a threshold for each capacitor charging voltage to ensure that the device is powered. The lower capacitor will not be overcharged.

As a preference, on the basis of the above embodiments, in order to better implement the utility model, the charging branch includes electronic switch DK1, diode D6 and electronic switch DK3, and the discharging branch includes DK2, diode D7 and DK4; the input terminal of DK1 is connected to the input terminal of the DC/DC power supply, the output terminal of DK1 is connected to the input terminal of DK2, the positive pole of D6, and the negative pole of D7, and the output terminal of DK2 is connected to the output terminal of the DC/DC power supply ; The negative pole of D6 is connected to the input terminal of the electronic switch DK3 and the output terminal of DK4; the DK1 and DK3 are mutually exclusive with DK2 and DK4 respectively. Preferably, a current-limiting resistor R6 is connected between the D6 and the DK3. As shown in the figure, D6, R6, DK1, and DK3 form a charging circuit, and DK2, DK4, and D7 form a discharging circuit; when the equipment is powered normally, DK1 and DK3 are turned on, DK2 and DK4 are turned off, and the input current passes through DK1, D6, R6, DK3 charge each capacitor. When the input power of the device is disconnected, DK1 and DK3 are disconnected, DK2 and DK4 are turned on, the capacitor is discharged, and the device is powered through DK4, D7 and DK2.

Preferably, the resistance values of the resistors R1 , R2 , R3 , R4 and R5 are equal, and the capacitance values of the capacitors C1 , C2 , C3 , C4 and C5 are equal. Preferably, the parameters of the Zener diodes D1, D2, D3, D4 and D5 are equal. After this design, it can facilitate the construction and maintenance of the entire circuit structure, each resistor can be freely exchanged, each capacitor can be freely exchanged, and each Zener diode can also be freely exchanged.

Preferably, the DC/DC power supply is a 28V to 5V power supply. When the system has power, the charging circuit charges with 28V. When discharging, because the discharge branch is connected to the connection between C4 and C5, the discharge voltage is the voltage of C5, which is about 5V. When the power of C5 is not enough, it can be from C1, C2, C3 and C4 obtain power and continue to discharge, which greatly prolongs the power supply time after power failure, facilitates the storage of various data by electronic equipment, and reduces losses.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present utility model in detail. Within the protection scope of the utility model, any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the utility model shall be included in the protection scope of the utility model.

Claims (8)

1. power down delay circuit, it is characterised in that: including DC/DC power supply, the input terminal and output end of the DC/DC power supply connect respectively Be connected to the end VIN and the end VOUT, be connected with charging paths between the end VIN and DC/DC power supply, the end VOUT and Discharge paths are connected between DC/DC power supply；The charging paths are connected with discharge paths by storage discharge cell.

2. power down delay circuit according to claim 1, it is characterised in that: the storage discharge cell includes successively connecting Resistance R1, R2, R3, R4 and the R5 connect, described resistance R1, R2, R3, R4 and R5 be parallel with respectively capacitor C1, C2, C3, C4 and C5；Described one end R1 is connect with R2, and the other end is connect with the charging paths, and the discharge paths and C4 are same The junction of C5 connects.

3. power down delay circuit according to claim 2, it is characterised in that: described resistance R1, R2, R3, R4 and the R5 It is also parallel with zener diode D1, D2, D3, D4 and D5 respectively.

4. power down delay circuit according to claim 1, it is characterised in that: the charging paths include electronic switch DK1, diode D6 and electronic switch DK3, the discharge paths include DK2, diode D7 and DK4；The DK1's The input terminal of input termination DC/DC power supply, the output end of DK1 are connected with the cathode of the input terminal of DK2, the anode of D6, D7, DK2 Output end connection DC/DC power supply output end；The cathode of D6 is connected with the output end of electronic switch DK3 input terminal, DK4；Institute The DK1 and DK3 stated respectively with DK2 and DK4 mutual exclusion.

5. power down delay circuit according to claim 4, it is characterised in that: connected between the D6 and the DK3 Limited leakage resistance R6.

6. power down delay circuit according to claim 3, it is characterised in that: described resistance R1, R2, R3, R4 and the R5 Resistance value it is equal, the capacitance of described capacitor C1, C2, C3, C4 and C5 are equal.

7. power down delay circuit according to claim 6, it is characterised in that: described zener diode D1, D2, D3, the D4 And the parameter of D5 is equal.

8. power down delay circuit according to claim 1, it is characterised in that: the DC/DC power supply is that 28V turns 5V electricity Source.